June 2019
L011804
Wiring Diagrams
Input Pin Descriptions
Pin #
Description
CBL-AA4031
Wire Color
1
Direction
Brown
2
Clock
Red
3
On/Off
Orange
4
MS2
Yellow
5
MS1
Green
6
12VDC-24VDC
Blue
7
0VDC (Gnd)
Violet
Input Pin Descriptions
Pin #
Description
CBL-AA4033
Wire Color
1
Phase A
Brown
2
Phase
Ā
Red
3
Phase B
Orange
4
Phase B
Yellow
Microstep Resolution Truth Table
MS1
MS2
Resolution
Active
Active
Full Step
Inactive (Open)
Active
Half Step
Active
Inactive (Open)
Quarter Step
Inactive (Open) Inactive (Open)
Eighth Step
Direction:
Logic “1” CW
Logic
“0”
CCW
Clock
:
Active - 1 Step
Inactive (open) - Reduce Current Mode
On/Off:
Active - Off
Inactive (open) - On
Notes:
Opens Inputs are inactive and internally pulled up to
+5VDC for JP1 position 1-2 (Sinking)
Open Inputs are inactive and internally pulled down
to 0VDC for JP1 position 2-3 (sourcing)
A. Minimum Command Active Time Before Clock
Pulse (Data Set-Up Time)...200nS
B. Minimum Command Active Time After Clock Pulse
(Data Hold Time).....200nS
C. Minimum Clock Pulse Width.......................1.0uS
D. Minimum Clock Inactive Time....................1.0uS
Maximum Clock Frequency...........................500kHz
With JP1 in position 1-2 (sinking) the inputs are considered inactive of Logic “1” if left open, or active or
Logic “0” if grounded. With JP1 in position 2-3 (sourcing) the inputs are considered inactive or Logic “0”
if left open, and active or Logic “1” if pulled to 3.5 - 24VDC.
Control Inputs (Pins 1, 2, 3, 4, 5):
July 2018
