Ampro Little Board 700, Reference Manual

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Chapter 3 Hardware
30 Reference Manual LittleBoard 700
PC/104 Interface (J1A,B,C,D)
The PC/104 Bus uses a 104-pin 100 mil header interface. This interface header will carry all of the
appropriate PC/104 signals operating at clock speeds up to 8MHz. This interface header accepts
stackable modules and is located on the top of the board.
Table 3-5. PC/104 Interface Pin/Signal Descriptions (J1A)
Pin # Signal Description (J1 Row A)
1 (A1) IOCHCHK* bus NMI input
2 (A2) SD7 Data bit 7
3 (A3) SD6 Data bit 6
4 (A4) SD5 Data bit 5
5 (A5) SD4 Data bit 4
6 (A6) SD3 Data bit 3
7 (A7) SD2 Data bit 2
8 (A8) SD1 Data bit 1
9 (A9) SD0 Data bit 0
10 (A10) IOCHRDY Processor Ready Ctrl
11 (A11) AEN Address Enable - This signal is reserved for the ISA Bus and is asserted
during DMA cycles to prevent I/O slaves from misinterpreting DMA
cycles as valid I/O cycles.
12 (A12) SA19 Address bit 19
13 (A13) SA18 Address bit 18
14 (A14) SA17 Address bit 17
15 (A15) SA16 Address bit 16
16 (A16) SA15 Address bit 15
17 (A17) SA14 Address bit 14
18 (A18) SA13 Address bit 13
19 (A19) SA12 Address bit 12
20 (A20) SA11 Address bit 11
21 (A21) SA10 Address bit 10
22 (A22) SA9 Address bit 9
23 (A23) SA8 Address bit 8
24 (A24) SA7 Address bit 7
25 (A25) SA6 Address bit 6
26 (A26) SA5 Address bit 5
27 (A27) SA4 Address bit 4
28 (A28) SA3 Address bit 3
29 (A29) SA2 Address bit 2
30 (A30) SA1 Address bit 1
31 (A31) SA0 Address bit 0
32 (A32) GND Ground
Notes:
The shaded area denotes power or ground. The signals marked with * = Negative true logic.