PC27E
Page 19
The 12 bit data word is not coded in pure binary, but in a form of 2s complement where the
most significant bit is inverted. The transfer functions for bipolar and unipolar operation are
given in figure 5.
N.B.
Under software sampling it is not possible to detect the status of each sample, so
the user must insert a delay between starting the conversion and reading the first byte,
typically >10µs.
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FIG. 5 ANALOG TO DIGITAL CONVERTER OUTPUT CODE
6.6
Programming Hints
6.6.1
Settling Time of Input Stages
When switching to another analog input channel, the settling time of the multiplexer plus the
amplifier stages is less than 10 µSecs to within 0.1% of full scale. As the A to D Converter
incorporates a sample and hold circuit, careful programming can allow the analog settling
time to overlap A to D conversion time for maximum throughput.
