manualshive.com logo in svg

AMLOGIC S905D3, Quick Reference Manual, Page: 8 / 72

Share
Download
AMLOGIC S905D3 Quick Reference Manual Download Page 8

0.6 (2019–07–25)

Amlogic Proprietary and Confidential

Copyright © Amlogic. All rights reserved.

3

3 Features Summary

CPU Sub-system

●

●

Quad core ARM Cortex-A55 CPU

●

●

ARMv8-A architecture with Neon and Crypto extensions

●

●

8-stage in-order full dual issue pipeline

●

●

Unified system L3 cache

●

●

Build-in Cortex-M4

Optional

core for always on processing

●

●

Build-in Cortex-M3 core for system control processing

●

●

Advanced TrustZone security system

●

●

Application based traffic optimization using internal QoS-based switching fabrics

Neural Network Processing Unit(NPU)

Optional

●

●

1.2 TOPS NN inference accelerator

●

●

Supports all major deep learning frameworks including TensorFlow and Caffe

3D Graphics Processing Unit

●

●

ARM G31 MP2 GPU

●

●

4-wide warps, dual texture pipe, 2x 4-wide execution engines (EE)

●

●

Concurrent multi-core processing

●

●

OpenGL ES 3.2, Vulkan 1.1 and OpenCL 2.0 support

S905D3

Memory Interface

System Interface

Video Output Unit

D

e

-i

n

te

rl

a

c

e

r

S

c

a

la

r

H

D

R

P

ro

c

e

s

s

in

g

HDMI 2.1

Core and Fabric

TrustZone Security

Input/Output Interfaces

USB 

HOST

USB 
OTG

SDIO3.0

I2C

UART

SPI

PWM

SAR 
ADC

SDXC/
SDHC/

SD

L3Cache

MMU

Audio Output Unit

TDM / I2S

HDMI 2.1

SPDIF

IR 

Rx & Tx

PLLs

PMU

JTAG

Temp

Sensor

PerfMon

Audio Input Unit

SPDIF

DDR3/4/3L & 

LPDDR3/4 Memory 

Controller

eMMC/NAND Flash 

Controller

SPI 

Flash Controller

2.5D Graphic

Processing

Crypto
Engine

Secured NV 

storage

Power 

Management

Processor

10/100M 
Ethernet 

PHY

CVBS

TDM / I2S

Cortex-A55

32KB I/D-Cache

NEON/VFP

Cortex-A55

32KB I/D-Cache

NEON/VFP

Cortex-A55

32KB I/D-Cache

NEON/VFP

Cortex-A55

32KB I/D-Cache

NEON/VFP

PDM x8

Stereo Audio DAC

E

n

h

a

n

c

e

m

e

n

t

L2 Cache

MMU

Mali-G31 MP2

Video Input Unit

2x Tsin

Demux

MIPI-CSI

MIPI DSI

Giga 

Ethernet 

MAC

USB SS/ 

PCIe 2.0

USB 3.0 / PCIe 2.0 *

ISO7816

* Supported configuration: PCIe 2.0 port + USB 2.0  Host, or USB  3.0 port without PCIe

A06ST01

NPU

#

Cortex-M4

#

AVE-10

V

A

D

# Optional for special part no.

S905D3 Quick Reference Manual

3 Features Summary

Preliminary Version

Confidential for Wesion!

Summary of Contents for S905D3

Page 1: ...S905D3 Quick Reference Manual Revision 0 6 Release Date 2019 07 25 P r e l i m i n a r y V e r s i o n C o n f i d e n t i a l f o r W e s i o n...

Page 2: ...his document or in the product described in this document at any time This product is not intended for use in medical life saving or life sustaining applications Circuit diagrams and other information...

Page 3: ...ion Version 0 4 2019 04 10 This is the forth release Compare with last version the following part has been modified Section Change Description 3 Update SOC diagram 4 3 Update eARC_N eARC_P description...

Page 4: ...thernet Timing Compare with last version the following part has been modified Section Change Description 5 11 Add Power consumption data Version 0 1 2019 02 21 This is the first release Compare with l...

Page 5: ...Specifications For DIO_xmA 41 5 5 2 Open Drain GPIO Specifications For DIO_OD 42 5 5 3 DDR3 DDR3L DDR4 LPDDR3 LPDDR4 SDRAM Specifications 43 5 6 Recommended Oscillator Electrical Characteristics 44 5...

Page 6: ...s reserved 1 1 About This Document This document is applicable to S905D3 SoC series please contact your Amlogic sales representative for more detail S905D3 Quick Reference Manual 1 About This Document...

Page 7: ...ing It includes dedicated hardware video decoder and encoder AVE 10 is capable of decoding 4Kx2K reso lution video at 60fps with complete Trusted Video Path TVP for secure applications and supports fu...

Page 8: ...ideo Output Unit De interlacer Scalar HDRProcessing HDMI 2 1 Core and Fabric TrustZone Security Input Output Interfaces USB HOST USB OTG SDIO3 0 I2C UART SPI PWM SAR ADC SDXC SDHC SD L3Cache MMU Audio...

Page 9: ...ncoders Support multi video decoder up to 4x1080P 60fps Supports multiple secured video decoding sessions and simultaneous decoding and encoding Video Picture Decoding VP9 Profile 2 up to 4Kx2K 60fps...

Page 10: ...p 1080i p and 4Kx2K 4 lane MIPI DSI interface resolution up to 1920 1080 Audio Decoder and Input Output Supports MP3 AAC WMA RM FLAC Ogg Dolby DigitalOptional Dolby Digital PlusOptional DTSOp tional a...

Page 11: ...ilt in 10bit SAR ADC with 4 input channels A set of General Purpose IOs with built in pull up and pull down System Peripherals and Misc Interfaces Integrated general purpose timers counters DMA contro...

Page 12: ...Confidential Copyright Amlogic All rights reserved 7 Package FCBGA 16 1mmx14 3mm 0 6mm ball pitch RoHS compliant S905D3 Quick Reference Manual 3 Features Summary P r e l i m i n a r y V e r s i o n C...

Page 13: ...Amlogic All rights reserved 8 4 Pinout Specification 4 1 Pin Out Diagram top view Figure 4 1 Pinout Diagram topview 4 2 Pin Order S905D3 Quick Reference Manual 4 Pinout Specification P r e l i m i n...

Page 14: ...PIOC_3 E24 DVSS E26 VDDIO_C E28 GPIOC_1 E30 PCIE_CLK_n E32 DVSS E34 PCIE_TXP E36 ENET_EXTRES E38 USBHOST_A_DP E40 DVSS E42 DVSS E44 HDMITX_2N E46 DVSS G1 DDR_DQ21 G3 DDR_DQ20 G5 DVSS G8 DDR_DQ27 G11 D...

Page 15: ...CVBS_IOUT W1 AC_33 W3 AC_29 W5 AC_32 W7 AC_37 W9 AC_30 W11 PVREF W36 CVBS_COMP W38 GPIOH_5 W40 GPIOH_4 W42 DVSS W44 eARC_P W46 eARC_N Y14 VDDQ Y16 DVSS Y18 DVSS Y20 VDD_EE Y22 DVSS Y24 AVSS_HCSL Y26...

Page 16: ...9 AC_16 AL11 AC_3 AL36 DSI_CEXT AL38 DSI_R1K AL40 DSI_R600 AM3 AC_2 AM5 AC_36 AM27 VDD_EE AM42 DSI_D2N AM44 DSI_D2P AN14 DVSS AN16 DVSS AN18 DVSS AN20 VDDCPU AN22 VDDCPU AN24 DVSS AN30 DVSS AN32 VDD18...

Page 17: ...GPIOZ_13 BF1 DDR_DQ6 BF3 DVSS BF5 DDR_DQ5 BF7 DVSS BF10 DVSS BF13 GPIOAO_3 BF16 GPIOAO_11 BF19 BOOT_15 BF22 BOOT_9 BF25 VDDIO_X BF28 TEST_N BF31 GPIOX_17 BF34 GPIOX_11 BF36 GPIOZ_0 BF39 GPIOZ_14 BF42...

Page 18: ...PIOZ_6 DIO Up General purpose input output bank Z signal 6 VDDIO_Z NC GPIOZ_7 DIO Up General purpose input output bank Z signal 7 VDDIO_Z NC GPIOZ_8 DIO Up General purpose input output bank Z signal 8...

Page 19: ...ose input output bank A signal 14 VDDIO_A NC GPIOA_15 DIO Up General purpose input output bank A signal 15 VDDIO_A NC VDDIO_A P Power supply for GPIO bank A NC BOOT Refer to Table 4 3 for functional m...

Page 20: ...ut output bank C signal 5 VDDIO_C NC GPIOC_6 DIO UP General purpose input output bank C signal 6 VDDIO_C NC GPIOC_7 OD 5V Z General purpose input output bank C signal 7 VDDIO_C NC VDDIO_C P Power supp...

Page 21: ...output bank H signal 2 VDDIO_H NC GPIOH_3 OD5V Z General purpose input output bank H signal 3 VDDIO_H NC GPIOH_4 DIO DOWN General purpose input output bank H signal 4 VDDIO_H NC GPIOH_5 DIO DOWN Gene...

Page 22: ..._AO To 3 3V GPIOE Refer to Table 4 8 for functional multiplex information GPIOE_0 DIO Z General purpose input output bank E signal 0 VDD18_ AO_XTAL NC GPIOE_1 DIO Z General purpose input output bank E...

Page 23: ...put 3 3V NC HDMITX_ CKN AO HDMI TMDS clock negative output 3 3V NC HDMI_ REXT A HDMI output strength setting resistor 3 3V NC HDMI_ CEXT A HDMI TX external filter cap 3 3V NC AVDD18_ HDMI P Analog pow...

Page 24: ...PHY address command control signal bit 18 VDDQ NC AC_20 DO DDR PHY address command control signal bit 20 VDDQ NC AC_21 DO DDR PHY address command control signal bit 21 VDDQ NC AC_22 DO DDR PHY address...

Page 25: ...DDR_DQ3 DIO DRAM data bus bit 3 VDDQ To DRAM DDR_DQ4 DIO DRAM data bus bit 4 VDDQ To DRAM DDR_DQ5 DIO DRAM data bus bit 5 VDDQ To DRAM DDR_DQ6 DIO DRAM data bus bit 6 VDDQ To DRAM DDR_DQ7 DIO DRAM dat...

Page 26: ...IO DRAM data bus bit 31 VDDQ NC DDR_DQM0 DIO DRAM data mask 0 VDDQ To DRAM DDR_DQM1 DIO DRAM data mask 1 VDDQ To DRAM DDR_DQM2 DIO DRAM data mask 2 VDDQ NC DDR_DQM3 DIO DRAM data mask 3 VDDQ NC DDR_ D...

Page 27: ...3 3V AVDD18_ USB P 1 8V Power supply for USB To 1 8V Ethernet ENET_ATP AIO Ethernet PHY analog test pin AVDD18_ NET NC ENET_ EXTRES A Ethernet PHY external resistor connection AVDD18_ NET NC ENET_RXN...

Page 28: ...DD18_ MIPICSI NC CSI_D0_P AIO MIPI CSI data 0 positive input AVDD18_ MIPICSI NC CSI_D1_N AI MIPI CSI data 1 negative input AVDD18_ MIPICSI NC CSI_D1_P AI MIPI CSI data 1 positive input AVDD18_ MIPICSI...

Page 29: ...NC AVDD0V8_ USB_PCIE AP Analog 0 8V power supply for USB and PCIE To VDD_ EE AVDD18_ PCIE AP Analog 1 8V power supply for PCIE To 1 8V HCSL_ REXT AIO PCIE reference clk output strength setting resisto...

Page 30: ...nput pin DO Digital output pin DIO Digital input output pin OD 5V 5V input tolerant open drain OD output pin need external pull up A Analog setting or filtering pin AI Analog input pin AO Analog outpu...

Page 31: ...LK TDMC_ SLV_FS PDM_ DCLK GPIOZ_7 ETH_ RXD3_ RGMII TSIN_B_ DIN1 TDMC_ SCLK SDCARD_ CMD TDMC_ SLV_SCLK I2C_EE_ M0_SDA GPIOZ_8 ETH_ RGMII_TX_ CLK TSIN_B_ DIN2 MCLK_1 I2C_EE_ M0_SCL GPIOZ_9 ETH_ TXEN TSI...

Page 32: ...GPIOA_15 IR_REMOTE_ INPUT I2C_EE_M3_SCL Table 4 3 BOOT_x Multi Function Pin Pin Name Func1 Func2 Func3 BOOT_0 EMMC_D0 BOOT_1 EMMC_D1 BOOT_2 EMMC_D2 BOOT_3 EMMC_D3 NOR_HOLD BOOT_4 EMMC_D4 NOR_D BOOT_5...

Page 33: ...CARD_ D1 GPIOX_2 SDIO_D2 PDM_DIN2 TSIN_A_ VALID SDCARD_ D2 GPIOX_3 SDIO_D3 PDM_DIN3 TSIN_A_ CLK PWM_D SDCARD_ D3 GPIOX_4 SDIO_CLK PDM_ DCLK SDCARD_ CLK GPIOX_5 SDIO_CMD MCLK_1 PWM_C SDCARD_ CMD GPIOX_...

Page 34: ...TS SPI_B_MISO PWM_F TDMB_D3 TDMB_DIN3 GPIOH_6 ISO7816_ CLK UART_EE_ C_RX SPI_B_SS0 I2C_EE_M1_ SDA IR_ REMOTE_ OUT GPIOH_7 ISO7816_ DATA UART_EE_ C_TX SPI_B_SCLK I2C_EE_M1_ SCL PWM_B GPIOH_8 Table 4 7...

Page 35: ...RT_AO_B_CTS PWMAO_B I2C_AO_M0_SCL GPIOE_1 UART_AO_A_RTS UART_AO_B_RTS PWMAO_D I2C_AO_M0_SDA GPIOE_2 CLK12_24 CLK25_EE PWM_A Table 4 9 DDR AC Multi Function Pin Pin Name LPDDR3 LPDDR4 DDR3 DDR4 AC_0 CK...

Page 36: ...NC ODT0 ODT0 AC_37 NC NC ODT1 ODT1 AC_38 NC NC CS_N1 CS_N1 DDR_RSTn NC RESET_N RESET_N RESET_N PVREF PVREF PVREF PVREF PVREF PZQ PZQ PZQ PZQ PZQ Table 4 10 PCIE IO Multi Function Pin Pin Name Func1 F...

Page 37: ...tput in AO domain UART_AO_A_RX DI UART Port A data input in AO domain UART_AO_ A_ CTS DI UART Port A Clear To Send Signal in AO domain UART_AO_A _ RTS DO UART Port A Ready To Send Signal in AO domain...

Page 38: ...arallel TS input port B data 2 TSIN_B_DIN3 DI Parallel TS input port B data 3 TSIN_B_DIN4 DI Parallel TS input port B data 4 TSIN_B_DIN5 DI Parallel TS input port B data 5 TSIN_B_DIN6 DI Parallel TS i...

Page 39: ...clock output Master mode in EE domain I2C_EE _M1_SDA DIO I2C bus port 1 data input output Master mode in EE domain I2C_EE_M2_SCL DO I2C bus port 2 clock output Master mode in EE domain I2C_EE _M2_SDA...

Page 40: ..._WP DIO SPI NOR Write protection output 4 bit mode data I O 2 NOR_HOLD DIO SPI bus hold output 4 bit mode data I O 3 Table 4 22 HDMI Interface Signal Description Signal Name Type Description HDMITX_SD...

Page 41: ...r mode MCLK_1 DO Master clock output 1 for I2S master mode TDMA_DIN0 DI Data input 0 of TDM port A TDMA_DIN1 DI Data input 1 of TDM port A TDMA_D0 DIO Data input output 0 of TDM port A TDMA_D1 DIO Dat...

Page 42: ..._D3 DIO Data input output 3 of TDM port C TDMC_D4 DIO Data input output 4 of TDM port C TDMC_D5 DIO Data input output 5 of TDM port C TDMC_SCLK DO Bit clock output of TDM port C TDMC_FS DO Frame sync...

Page 43: ...ce transmit data 2 ETH_TXD1 DO Ethernet RMII RGMII interface transmit data 1 ETH_TXD0 DO Ethernet RMII RGMII interface transmit data 0 ETH_RX_DV DI Ethernet RMII RGMII interface receive data valid sig...

Page 44: ...rating Conditions Symbol Parameter Min Typ Max Unit VDDCPU Voltage for Cortex A55 CPU 0 681 1 032 V VDD_EE and other 0 8V domain Voltage for GPU core logic 0 77 0 8 0 9 V VDDQ DDR3 DDR3L DDR4 LPDDR LP...

Page 45: ...tual voltage supplies to VDDIO HV mode should not be lower than 2 9V 4 For operating temperature good heat sink may be needed to guarantee Tj max spec 5 3 Ripple Voltage Specifications Please check be...

Page 46: ...onmental Conditions Natural Convection Still Air JESD51 8 Integrated Circuit Thermal Test Method Environmental Conditions Junction to Board JESD51 12 Guidelines for Reporting and Using Electronic Pack...

Page 47: ...in voltage close to 0V 6 Test condition GPIO pin voltage close to VDDIO 3 3V 5 5 2 Open Drain GPIO Specifications For DIO_OD Symbol Parameter Min Typ Max Unit ViH OD5V High level input voltage 1 5 5 5...

Page 48: ...VDDQ voltage in sleep mode is defined by memory DC specifications DDR3 DDR3L mode Symbol Parameter Min Typ Max Unit VIH DC input voltage high Vref 0 100 VDDQ V VIL DC input voltage low VSSQ Vref 0 10...

Page 49: ...40 140 280 ohm DC Specifications LPDDR4 mode Symbol Parameter Min Typ Max Unit VOH DC output logic high 0 9 VDDQ V VOL DC output logic low 0 1 VDDQ V RTT Input termination resistance to VDDQ 216 240 2...

Page 50: ...around 0 9V Xin range 0 3V to 2 1V Therefore Following suggestion for input clock Suggestion 1 Without DC blocking capacitor use a higher Vpp output TCXO The high voltage should be higher than 1 35V V...

Page 51: ...1 3 s tHIGH HIGH period of the SCL clock 4 0 6 s tSu STA Setup time for START 4 7 0 6 s tSu DAT Setup time for SDA 250 100 ns tSu STO Setup time for STOP 4 0 6 s tHd STA Hold time for START 4 0 6 s t...

Page 52: ...Unit tPERIOD Cycle time data transfer mode 5 ns SR Slew rate 1 125 V ns tCKDCD Duty cycle distortion 0 0 3 ns tCKMPW Minimum pulse width 2 2 ns tISU input set up time 1 4 ns tIH input hold time 0 8 n...

Page 53: ...le 5 3 HS200 Timing Specification Symbol Parameter Min Max Unit tPERIOD Cycle time data transfer mode 5 ns tISU output set up time 1 4 ns tIH output hold time 0 8 ns Figure 5 4 EMMC HS400 Data Intput...

Page 54: ...x Unit tPERIOD Cycle time data transfer mode 5 ns SR Slew rate 1 125 V ns tCKDCD Duty cycle distortion 0 0 2 ns tCKMPW Minimum pulse width 2 ns tRQ Input skew 0 4 ns tRQH input hold skew 0 4 ns Figure...

Page 55: ...t valid window TVW from last system Tuning procedure TPH is 2600ps for T from 25 C to 125 C during operation 350 T 20deg C 1550 T 90deg C ps tVW Valid Data Simple window 0 575 UI Figure 5 6 SDIO SDR10...

Page 56: ...ed to CLK Symbol Parameter Min Max Unit tIS input set up time 1 4 ns tIH input hold time 0 8 ns Note SD card interface uses SDIO protocol 5 7 3 NAND Timing Specification Nand timing specifications are...

Page 57: ...Async Waveform for Sequential Data Read Cycle After Read EOD Mode Table 5 8 Nand Timing Specifications Symbol Parameter Asynchronous mode 5 Min Max Unit tCLS CLE setup time 10 ns tCLH CLE hold time 5...

Page 58: ...tRLOH RE low to data hold time EDO 5 ns tRP RE pulse width 10 ns tREH RE high hold time 7 ns tRC RE cycle time 20 ns 5 7 4 SPICC Timing Specification Figure 5 11 SPICC Timing Diagram Table 5 9 SPICC M...

Page 59: ...SPIFC Timing Specification Figure 5 12 SPIFC Serial Input Timing Diagram Figure 5 13 SPIFC Out Timing Diagram Table 5 10 SPIFC Master Timing Specification Symbol Parameter Clock 41 7MHz Min Max Unit f...

Page 60: ...In Hold Time 3 ns tSHQZ Output Disable Time relative to CS 8 ns tCLQV Clock Low to Output Valid 6 ns tCLQX Output Hold Time 1 ns 5 7 6 Ethernet Timing Specification Figure 5 14 Management Data Timing...

Page 61: ...U TXD TX_ EN setup time to rising edge of RMII clock 1 8 10 ns To PHY tOHD TXD TX_ EN hold time to rising edge of RMII clock 1 4 10 ns To PHY tISU RXD DV setup time to rising edge of RMII clock 1 0 10...

Page 62: ..._DV skew between these 5 sig nals PHY in ternal delay disabled 0 5 0 5 ns From PHY When PHY internal delay is enabled check setup hold timing When PHY internal delay is disabled check signal skew Figu...

Page 63: ...sing edge of RGMII clock no clock de lay added 0 8 ns From PHY RXD DV hold time to rising edge of RGMII clock clock delay added 2 7 ns From PHY 5 7 7 Audio Timing Specification There are two modes for...

Page 64: ...SCLK 0 4 T tRC Edge time of SCLK 0 8 ns tdly Delay from SCLK to WS 2 3 5 tsuin Setup time of Din 4 ns thdin Hold time of Din 4 ns Note Measure Pointrefers to VIH ViL parameter of Normal GPIO Specifica...

Page 65: ...T tLC Low level of SCLK 0 4 T tRC Edge time of SCLK 0 8 ns tsu in Setup time of WS Din 4 ns thd in Hold time of WS Din 4 ns tdly Delay between SCLK and Dout 2 12 15 ns Note Measure Pointrefers to VIH...

Page 66: ...s Note 1 Default PDM_SYS_CLOCK 133MHz 2 For Sample position please refer to PDM register PDM_CHAN_CTRL PDM_CHAN_ CTRL1 SELECT H SELECT L SELECT H T 1 fCLOCK 50 50 50 T 2 T 2 Vih Vil Vih Vil Vil Vih Hi...

Page 67: ...high internal CPU will try to boot from nand eMMC first if fails then try to boot from SD CARD still fails then try to boot from USB PC External 4 7K ohm pull down resistors can be used to change the...

Page 68: ...1 0 SPI_NOR NAND eMMC SD Card USB 8 1 1 1 NAND eMMC SD Card USB Note If GPIOC is not work as SDIO port please do not pull CARD_DET GPIOC_6 low when system booting up to avoid romcode trying to boot fr...

Page 69: ...20 POR Specifications Parameter Symbol Min Typ Max Unit Reset threshold voltage Vth 2 6 2 7 2 8 V Reset delay time tDELAY 109 170 218 ms 5 10 Recommended Power on sequence Example power on sequence S...

Page 70: ...reference schematics 5 11 Power Consumption Note Value listed here is estimated typical max value tested Enough margin in circuit needs to be reserved Symbol Maximum Current Note VDDCPU 2 5 A VDD_EE 1...

Page 71: ...mA 5 Internal external pull down resistor consumes more current 5 12 Storage and Baking Conditions The processor is moisture sensitive device of MSL level 3 defined by IPC JEDEC J STD 020 Please follo...

Page 72: ...e SoC comes in a 52x46 ball matrix FCBGA RoHS package The mechanical dimensions are given in millimeters as the following figures Figure 6 1 Dimensions Figure 6 2 Dimension Specification S905D3 Quick...

Reviews:

No comments