![background image](http://html1.mh-extra.com/html/amd/sp5100/sp5100_data-book_2921669015.webp)
44409
Rev.
1.70
October 10
AMD SP5100 Databook
SP5100 Power on Sequence and Timing
15
T1
T2A
S5
S5
G3
G3
S0
S5 STRAPS
VBA
T
VBAT
RTC clock In
+3.3V_S5
1.2V_S5
RSMRST#
S 0 power rails
SB PWR_ GOOD
A_RST#
S0 STRAPS
KBRST#
T8B
PCIRST#
PCIE_ RCLKP/N
T2
PCICLK[5:0]
( See Note 1)
NB_ PWRGD
T7
T7A
LDT_PG
( See Note 5)
T11
T8A
T9
T9A
LDT_STP#
( Note 8)
Wake Event
SLP_S5#/
SLP_S3#
T13
T8D
LDT_RST#
ALLOW_ LDTSTP
WAKE#
PWR_BTN#
PS PWOK
T13A
T7B
( See Note 4)
T8C
( See Note 6)
RTCCLK out
T3
T10
System clocks
( See Note 1 & 2)
T4
T9B
Note 11
Figure 3-1: SP5100 Power Up/Down Sequence