AMD Geode LX 600 Data Book Download

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AMD Geode™ LX Processors Data Book

AMD Geode™ LX Processors
Data Book

February 2009

Publication ID: 33234H

Summary of Contents for Geode LX 600

Page 1: ...AMD Geode LX Processors Data Book AMD Geode LX Processors Data Book February 2009 Publication ID 33234H...

Page 2: ...roducts are not designed intended authorized or warranted for use as components in systems intended for surgical implant into the body or in other applications intended to support or sustain life or i...

Page 3: ...cessor 17 2 6 Display Controller 18 2 7 Video Processor 18 2 8 Video Input Port 18 2 9 GeodeLink PCI Bridge 18 2 10 Security Block 19 3 0 Signal Definitions 21 3 1 Buffer Types 23 3 2 Bootstrap Option...

Page 4: ...ns 513 6 13 GeodeLink Control Processor 533 6 14 GeodeLink Control Processor Register Descriptions 539 6 15 GeodeLink PCI Bridge 566 6 16 GeodeLink PCI Bridge Register Descriptions 572 7 0 Electrical...

Page 5: ...e Data Flow 291 Figure 6 19 Color Compare Operation 292 Figure 6 20 Graphics Filter Block Diagram 293 Figure 6 21 Flicker Filter and Line Buffer Path 295 Figure 6 22 Interlaced Timing Settings 298 Fig...

Page 6: ...55 GLCP Block Diagram 533 Figure 6 56 Processor Clock Generation 536 Figure 6 57 GIO Interface Block Diagram 537 Figure 6 58 GLPCI Block Diagram 566 Figure 6 59 Atomic MSR Accesses Across the PCI Bus...

Page 7: ...tion Register Set 91 Table 5 3 Segment Register Selection Rules 92 Table 5 4 EFLAGS Register 93 Table 5 5 System Register Set 94 Table 5 6 Control Registers Map 95 Table 5 7 CR4 Bit Descriptions 96 Ta...

Page 8: ...lay Encodings 283 Table 6 35 Cursor Color Key Alpha Interaction 284 Table 6 36 Video Bandwidth 286 Table 6 37 YUV 4 2 0 Video Data Ordering 287 Table 6 38 YUV 4 2 2 Video Data Ordering 287 Table 6 39...

Page 9: ...PLL PW1 and IRQ13 vary 557 Table 6 89 Format for Accessing the Internal PCI Configuration Registers 569 Table 6 90 PCI Device to AD Bus Mapping 570 Table 6 91 Standard GeodeLink Device MSRs Summary 57...

Page 10: ...ction with EAX 80000001h 629 Table 8 21 CPUID Instruction Codes with EAX 80000001h 630 Table 8 22 CPUID Instruction with EAX 80000002h 80000003h or 80000004h 631 Table 8 23 CPUID Instruction with EAX...

Page 11: ...details and suggestions for this device see the supporting documentation i e application notes schematics etc on the AMD Embedded Developer Sup port Web site http wwwd amd com dev NDA required Figure...

Page 12: ...pical 500 MHz max power LX 700 0 8W processor Unterminated Total Dissipated Power TDP 3 1W 1 3W typical 433 MHz max power LX 600 0 7W processor Unterminated Total Dissipated Power TDP 2 8W 1 2W typica...

Page 13: ...VOP Hardware video up down scalar Graphics video alpha blending and color key muxing Digital VOP SD and HD or TFT outputs Legacy RGB mode VOP supports SD and HD 480p 480i 720p and 1080i VESA 1 1 2 0 a...

Page 14: ...14 AMD Geode LX Processors Data Book Overview 33234H...

Page 15: ...er Unit consists of a single issue 8 stage pipeline and all the necessary support hardware to keep the pipe line running efficiently The instruction pipeline in the integer unit consists of eight stag...

Page 16: ...The FPU is a pipelined machine with dynamic scheduling of instructions to mini mize stalls due to data dependencies It performs out of order execution and register renaming It is designed to support a...

Page 17: ...exed ROPs 256 src dest pattern 256 2 src dest and pattern BLT Buffers FIFOs in Graphics Processor FIFOs in Graphics Processor BLT Splitting Managed by hardware Managed by hardware Video Synchronized B...

Page 18: ...85 Hz 1600x1200x32 bpp at 100 Hz 2 7 2 TFT Controller The TFT Controller converts the digital RGB output of a Video Mixer block to the digital output suitable for driving a TFT flat panel LCD The flat...

Page 19: ...the optional EEPROM memory for storing unique IDs and or security keys The AES and EEPROM sections have separate control registers but share a single set of interrupt registers The AES module has two...

Page 20: ...20 AMD Geode LX Processors Data Book Architecture Overview 33234H...

Page 21: ...0 CIS SUSPA STRAP TDP TDN System Memory Display TFT Option VDDEN VIP_HSYNC DRGB 25 24 VID 9 8 DOTCLK VOPCLK VSYNC VOP_VSYNC HSYNC VOP_HSYNC GREEN BLUE RED LDEMOD VIP_VSYNC SYSREF TLA 1 0 REQ 2 0 VID...

Page 22: ...ote 2 VOP 7 0 O DOTCLK O DOTCLK O DOTCLK O DOTCLK O DOTCLK O VOPCLK O HSYNC O HSYNC O HSYNC O HSYNC O VOP_HSYNC O VOP_HSYNC O VSYNC O VSYNC O VSYNC O VSYNC O VSYNC O VOP_VSYNC O DISPEN O DISPEN O VOP_...

Page 23: ...s pin PU PD Indicates if an internal programmable pull up or pull down resistor may be present Current High Low mA This column gives the current source sink capacities when the voltage at the pin is h...

Page 24: ...ystem MHz options including a PLL bypass option Refer to Table 6 87 on page 556 for programming Table 3 4 Ball Type Definitions Mnemonic Definition A Analog I Input ball I O Bidirectional ball CAVSS C...

Page 25: ...0 DQ2 SDK0P SDK2P DQ61 DQ57 DQ56 DQ5 DQ1 VSS VMEM MVREF DQ0 DQ4 VSS VSS VMEM DQM7 DQS7 VSS VMEM DQ62 VSS VSS VSS VSS VSS VCORE VCORE VCORE VCORE DAVDD BLUE DAVSS VCORE DAVDD GREEN DAVSS DAVDD DVREF DA...

Page 26: ...DQ29 I O DDR C10 DQ25 I O DDR C11 DQ30 I O DDR C12 VSS GND C13 MA3 I O DDR C14 VMEM PWR C15 MA2 I O DDR C16 MA0 I O DDR C17 MA1 I O DDR C18 VMEM PWR C19 DQS4 I O DDR C20 BA1 I O DDR C21 VSS GND C22 DQ...

Page 27: ...VSS GND P17 VSS GND P18 VCORE PWR P19 VCORE PWR P28 VSS GND P29 VMEM PWR P30 DQ62 I O DDR P31 VSS GND R1 VSS GND R2 VSS GND R3 VSS GND R4 VSS GND R13 VSS GND R14 VSS GND R15 VSS GND R16 VSS GND R17 VS...

Page 28: ...31 VIO PWR AH1 DRGB20 O PD 24 Q5 AH2 DRGB21 O PD 24 Q5 AH3 DRGB22 O PD 24 Q5 AH4 VSS GND AH5 DRGB11 O PD 24 Q5 VOP12 O AH6 VSS GND AH7 DRGB0 O PD 24 Q5 VOP7 O AH8 DRGB6 O PD 24 Q5 VOP1 O AH9 VSS GND A...

Page 29: ...VSS GND AK31 VIO PWR AL1 VSS GND AL2 VIO PWR AL3 DRGB10 O PD 24 Q5 VOP13 O AL4 DRGB13 O PD 24 Q5 VOP10 O AL5 VIO PWR AL6 DRGB2 O PD 24 Q5 VOP5 O AL7 DRGB5 O PD 24 Q5 VOP2 O AL8 VIO PWR AL9 DRGB30 I O...

Page 30: ...P2 DQ1 N2 DQ2 M3 DQ3 K2 DQ4 P3 DQ5 N1 DQ6 L3 DQ7 K1 DQ8 J2 DQ9 J1 DQ10 F3 DQ11 E3 DQ12 J3 DQ13 G1 DQ14 F2 DQ15 F1 DQ16 D2 DQ17 B4 DQ18 B6 DQ19 C8 DQ20 D1 DQ21 A4 DQ22 A7 DQ23 B7 DQ24 B9 DQ25 C10 DQ26...

Page 31: ...8 SDCLK2P M28 SDCLK3N H28 SDCLK3P J28 SDCLK4N D24 SDCLK4P D23 SDCLK5N D21 SDCLK5P D20 STOP AJ25 SUSPA AC31 SYSREF Y31 TCLK AC2 TDBGI AB2 TDBGO AB4 TDI AB3 TDN AK17 TDO AC1 TDP AL17 TLA0 B15 TLA1 B13 T...

Page 32: ...AH12 AH14 AH16 AH18 AH20 B2 AH23 AH26 AH28 AJ16 AK2 AK5 AK8 AK11 AK14 AK16 B3 AK18 AK21 AK24 AK27 AK30 AL1 AL16 AL31 B14 B18 B29 B30 C1 C2 C4 A5 C12 C21 C28 C30 C31 D3 D7 D10 D14 D16 A8 D18 D22 D25 D2...

Page 33: ...he GLCP I O companion interface uses the CIS signal to create a serial bus It contains INTR SUSP NMI INPUT_DIS OUTPUT_DIS and SMI For details see GIO_PCI Serial Protocol on page 538 SUSPA AC31 Strap I...

Page 34: ...curate die temperature measurements a dual current source remote sensor such as the National Semiconductor LM82 should be used Single cur rent source sensors may not yield the desired level of accurac...

Page 35: ...D27 C26 I O up to 200 Mb s 2 5 Row Address Strobe RAS CAS WE and CKE are encoded to support the different SDRAM commands RAS0 is used with CS0 and CS1 RAS1 is used with CS2 and CS3 CAS 1 0 E29 E28 I...

Page 36: ...scription TCLK AC2 I 0 66 MHz 3 3 Test Clock JTAG test clock TMS AA4 I 0 66 Mb s 3 3 Test Mode Select JTAG test mode select TDI AB3 I 0 66 Mb s 3 3 Test Data Input JTAG serial test data input TDO AC1...

Page 37: ...bus com mand During the data phase C BE are used as byte enables The byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data C BE0 applies to byte 0 LSB...

Page 38: ...e beginning and duration of an access FRAME is asserted to indicate a bus transaction is beginning While FRAME is asserted data transfers continue When FRAME is de asserted the transaction is in the f...

Page 39: ...er that an agent desires use of the bus Each mas ter has its own REQ line REQ priorities are based on the arbitration scheme chosen REQ2 is reserved for the interface with the AMD Geode CS5536 compani...

Page 40: ...acklight Enable VDDEN AE2 I O PD 0 162 Mb s 3 3 LCD VDD FET Control When this output is asserted high VDD voltage is applied to the panel This signal is intended to control a power FET to the LCD pane...

Page 41: ...oltage Reference Connect this pin to a 1 235V voltage reference DRSET Y1 A Analog N A DAC Current Setting Resistor 1 21K 1 to DAVSS DAVDD 3 0 W4 V4 V1 U1 APWR Analog 3 3 DAC Analog Power Connection DA...

Page 42: ...ORE See Table 3 6 on page 30 PWR N A 1 2 Core Power Connection Total of 32 VIO See Table 3 6 on page 30 PWR N A 3 3 I O Power Connection Total of 30 VMEM See Table 3 6 on page 30 PWR N A 2 5 Memory Po...

Page 43: ...D during reset VSYNC Video Driven low during RESET low HSYNC DISPEN DOTCLK DRGB 23 0 LDEMOD VDDEN CKE 1 0 DDR VID 7 0 PD Video Inputs during RESET low VIPCLK CIS System TDBGI Debug TMS TDI TCLK SYREF...

Page 44: ...44 AMD Geode LX Processors Data Book Signal Definitions 33234H...

Page 45: ...from the CPU Core 4 1 MSR Set The AMD Geode LX processor incorporates two GLIUs into its device architecture Except for the configuration registers that are required for x86 compatibility all internal...

Page 46: ...the same GeodeLink architecture with one GLIU being in that device Hence in a AMD Geode LX proces sor CS5536 system there are a total of three GLIUs two in the processor and one in the companion devic...

Page 47: ...es in a AMD Geode LX processor CS5536 system with the CPU Core as the source module Included in the table is the MSR port address for module access using the GLCP and GLPCI as the source module Howeve...

Page 48: ...the device s request on address bits 31 12 with a logical AND with PMASK bits of the descriptor register bits 19 0 are equal to the PBASE bits on the descriptor register bits 39 20 Also checks that th...

Page 49: ...ors are set up to route the special cycles to the appropriate device i e GLCP GLPCI etc The I O descriptors are configured to default to the appropriate device on reset The PCI special cycles are mapp...

Page 50: ...LIU0 00000000_00000002h GLIU1 00000000_00000004h Page 55 GLIU0 10002002h GLIU1 40002002h R W GLD SMI MSR GLD_MSR_SMI 00000000_00000001h Page 56 GLIU0 10002003h GLIU1 40002003h R W GLD Error MSR GLD_MS...

Page 51: ...Action STATISTIC_ACTION 0 00000000_00000000h Page 73 GLIU0 100000A3h GLIU1 400000A3h Reserved GLIU0 100000A4h GLIU1 400000A4h WO Descriptor Statistic Counter STATISTIC_CNT 1 00000000_00000000h Page 7...

Page 52: ...0000D2h R W Data Compare Mask Low DA_COMPARE_MASK_LO 0 00000000_00000000h Page 78 GLIU0 100000D3h GLIU1 400000D3h R W Data Compare Mask High DA_COMPARE_MASK_HI 0 00000000_00000000h Page 79 GLIU0 10000...

Page 53: ...1000002Bh R W P2D Range Offset Descriptor P2D_RO P2D_RO 2 0 00000000_000FFFFFh Page 83 1000002Ch R W P2D Swiss Cheese Descriptor P2D_SC P2D_SC 0 00000000_00000000h Page 84 1000002Dh 1000003Fh R W P2D...

Page 54: ...Descriptors IOD_BM 000000FF_FFF00000h Page 86 100000E3h 100000E8h R W IOD Swiss Cheese Descriptors IOD_SC 00000000_00000000h Page 87 100000E9h 100000FFh R W IOD Reserved Descriptors GLIU1 400000E0h 40...

Page 55: ...ce revision See AMD Geode LX Processors Specification Update document for value MSR Address GLIU0 10002001h GLIU1 40002001h Type R W Reset Value GLIU0 00000000_00000002h GLIU1 00000000_00000004h GLD_M...

Page 56: ...stic Counter 2 GLIU0 MSR 100000A8h GLIU1 MSR 400000A8h event Write 1 to clear writing 0 has no effect SMASK3 bit 3 must be low to generate SMI and set flag 34 SFLAG2 SMI Flag2 If high records that an...

Page 57: ..._LO2 DA_COMPARE_VAL_HI2 GLIU0 MSR 100000D8h 100000D9h GLIU1 MSR 400000D8h 400000D9h event Write 1 to clear writing 0 has no effect EMASK13 bit 13 must be low to generate ERR and set flag 44 EFLAG12 Da...

Page 58: ...igh records that an ERR was generated due an unexpected address synchronous error Write 1 to clear writing 0 has no effect EMASK1 bit 1 must be low to generate ERR and set flag 32 EFLAG0 Unexpected Ty...

Page 59: ...4 bit 36 and to allow a Statis tic Counter 1 GLIU0 MSR 100000A4h GLIU1 MSR 400000A4h event to generate an ERR 3 EMASK3 Statistic Counter Error Mask 0 Write 0 to enable EFLAG3 bit 35 and to allow a Sta...

Page 60: ...c 00 Disable clock gating Clocks are always on 01 Enable hardware clock gating Clock goes off whenever this module s circuits are not busy 10 11 Reserved MSR Address GLIU0 10002005h GLIU1 40002005h Ty...

Page 61: ...iptions Bit Name Description 63 16 RSVD Reserved 15 14 PAE0 Port Active Enable for Port 0 GLIU0 GLIU GLIU1 GLIU 00 OFF Master transactions are disabled 01 LOW Master transactions limited to 1 outstand...

Page 62: ...in arbitration Only applies when arbitrating matching priorities 0 Disable 1 Enable 62 PIPE_DIS Pipelined Arbitration Disabled 0 Pipelined arbitration enabled and GLIU is not limited to one outstandin...

Page 63: ...s reported in bit 1 8 ASMI_MASK0 Asynchronous SMI Mask for Port 0 GLIU0 GLIU GLIU1 GLIU Write 0 to allow Port 0 to generate an ASMI ASMI status is reported in bit 0 7 ASMI_FLAG7 RO Asynchronous SMI Fl...

Page 64: ...R status is reported in bit 2 9 AERR_MASK1 Asynchronous Error Mask for Port 1 GLIU0 GLMC GLIU1 Interface to GLIU0 Write 0 to allow Port 1 to generate an AERR AERR status is reported in bit 1 8 AERR_MA...

Page 65: ...8 7 6 5 4 3 2 1 0 NP2D_BMK NP2D_SC NP2D_RO NP2D_R NP2D_BMO NP2D_BM PHY_CAP Bit Descriptions Bit Name Description 63 RSVD Reserved 62 60 NSTAT_CNT Number Of Statistic Counters 59 57 NDBG_DA_CMP Number...

Page 66: ...ns Bit Name Description 63 56 NOOUT_RESP7 Number of Outstanding Responses on Port 7 GLIU0 Not Used GLIU1 Not Used 55 48 NOOUT_RESP6 Number of Outstanding Responses on Port 6 GLIU0 Not Used GLIU1 SB 47...

Page 67: ...GP GLIU1 VIP 39 32 NOOUT_WDATA4 Number of Outstanding Write Data on Port 4 GLIU0 DC GLIU1 GLPCI 31 24 NOOUT_WDATA3 Number of Outstanding Write Data on Port 3 GLIU0 CPU Core GLIU1 GLCP 23 16 NOOUT_WDAT...

Page 68: ...erface to GLIU0 If high indicates that Port 1 is a slave port If low Port 1 is a master slave port 0 P0_SLAVE_ONLY Port 0 Slave Only GLIU0 GLIU GLIU1 GLIU If high indicates that Port 0 is a slave port...

Page 69: ...Not Used Write 1 to disable slave transactions to Port 7 6 SLAVE_DIS6 Slave Transactions Disable for Port 6 GLIU0 Not Used GLIU1 SB Write 1 to disable slave transactions to Port 6 5 SLAVE_DIS5 Slave...

Page 70: ...39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD THROT_EN THRESH ARB2 Bit Descriptions Bit Name Description 63 4 RSVD Reserved 3...

Page 71: ...00000000_00000000h MSR Address GLIU0 100000A8h GLIU1 400000A8h Type R W Reset Value 00000000_00000000h MSR Address GLIU0 100000ACh GLIU1 400000ACh Type R W Reset Value 00000000_00000000h STATISTIC_CN...

Page 72: ...000ADh GLIU1 400000ADh Type R W Reset Value 00000000_00000000h STATISTIC_MASK 0 3 Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 IOD_MASK...

Page 73: ...1 0 RSVD PREDIV WRAP ZERO_AERR ZXERO_ASMI ALWAYS_DEC HIT_AERR HIT_ASMI HIT_DEC HIT_LDEN STATISTIC_ACTION 0 3 Bit Descriptions Bit Name Description 63 24 RSVD Reserved 23 8 PREDIV Pre Divider Used if...

Page 74: ...able 1 Enable 0 HIT_LDEN Load Counter on Descriptor Hit The descriptor hits are ANDed with the masks and then all ORed together 0 Disable 1 Enable STATISTIC_ACTION 0 3 Bit Descriptions Bit Name Descri...

Page 75: ...U0 100000C1h GLIU1 400000C1h Type R W Reset Value 00000000_00000000h MSR Address GLIU0 100000C3h GLIU1 400000C3h Type R W Reset Value 00000000_00000000h MSR Address GLIU0 100000C5h GLIU1 400000C5h Typ...

Page 76: ...h Type R W Reset Value 00001FFF_FFFFFFFFh MSR Address GLIU0 100000D8h GLIU1 400000D8h Type R W Reset Value 00001FFF_FFFFFFFFh MSR Address GLIU0 100000DCh GLIU1 400000DCh Type R W Reset Value 00001FFF_...

Page 77: ...h Type R W Reset Value 0000000F_FFFFFFFFh MSR Address GLIU0 100000D9h GLIU1 400000D9h Type R W Reset Value 0000000F_FFFFFFFFh MSR Address GLIU0 100000DDh GLIU1 400000DDh Type R W Reset Value 0000000F_...

Page 78: ...00D6h Type R W Reset Value 00000000_00000000h MSR Address GLIU0 100000DAh GLIU1 400000DAh Type R W Reset Value 00000000_00000000h MSR Address GLIU0 100000DEh GLIU1 400000DEh Type R W Reset Value 00000...

Page 79: ...LIU0 100000DFh GLIU1 400000DFh Type R W Reset Value 00000000_00000000h DA_COMPARE_MASK_HI 0 3 Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33...

Page 80: ...a hit based on the other settings in this register 000 Port 0 GLIU0 GLIU GLIU1 GLIU 001 Port 1 GLIU0 GLMC GLIU1 Interface to GLIU0 010 Port 2 GLIU0 Interface to GLIU1 GLIU1 VP 011 Port 3 GLIU0 CPU Co...

Page 81: ...VP 011 Port 3 GLIU0 CPU Core GLIU1 GLCP 100 Port 4 GLIU0 DC GLIU1 GLPCI 101 Port 5 GLIU0 GP GLIU1 VIP 110 Port 6 GLIU0 Not Used GLIU1 SB 111 Port 7 GLIU0 Not Used GLIU1 Not Used 60 PCMP_BIZ Compare B...

Page 82: ...GLIU0 GLMC GLIU1 Interface to GLIU0 010 Port 2 GLIU0 Interface to GLIU1 GLIU1 VP 011 Port 3 GLIU0 CPU Core GLIU1 GLCP 100 Port 4 GLIU0 DC GLIU1 GLPCI 101 Port 5 GLIU0 GP GLIU1 VIP 110 Port 6 GLIU0 Not...

Page 83: ...011 Port 3 GLIU0 CPU Core GLIU1 GLCP 100 Port 4 GLIU0 DC GLIU1 GLPCI 101 Port 5 GLIU0 GP GLIU1 VIP 110 Port 6 GLIU0 Not Used GLIU1 SB 111 Port 7 GLIU0 Not Used GLIU1 Not Used 60 PCMP_BIZ Compare Bizz...

Page 84: ...t 5 GLIU0 GP GLIU1 VIP 110 Port 6 GLIU0 Not Used GLIU1 SB 111 Port 7 GLIU0 Not Used GLIU1 Not Used 60 PCMP_BIZ Compare Bizzaro Flag 0 Consider only transactions whose Bizzaro flag is low as a potentia...

Page 85: ...40h 4000004Fh Type R W Reset Value 00000000_00000000h SPARE_MSR x Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 SPARE_MSR 31 30 29 28 27...

Page 86: ...it based on the other settings in this register 000 Port 0 GLIU0 GLIU GLIU1 GLIU 001 Port 1 GLIU0 GLMC GLIU1 Interface to GLIU0 010 Port 2 GLIU0 Interface to GLIU1 GLIU1 VP 011 Port 3 GLIU0 CPU Core G...

Page 87: ...erved Write as read 31 24 EN Enable for Hits to IDID1 or else SUBP Setting these bits enables hits to IDID1 If not enabled subtractive port is selected per GLD_MSR_CONFIG bits 2 0 MSR GLIU0 10002001h...

Page 88: ...88 AMD Geode LX Processors Data Book GLIU Register Descriptions 33234H...

Page 89: ...ssor to begin execution in the lowest 1 MB of address space Table 5 1 lists the CPU Core registers and illustrates how they are initialized Table 5 1 Initialized Core Register Controls Register Regist...

Page 90: ...in front of the opcode For example the use of prefixes allows a 32 bit operand to be used with 16 bit code or a 16 bit operand to be used with 32 bit code The Processor Core Instruction Set see Table...

Page 91: ...the processor will execute This register is auto matically incremented by the processor as execution progresses The EFLAGS register contains control bits used to reflect the status of previously execu...

Page 92: ...n the stack during procedure calls Local data may also be placed on the stack and accessed with BP This register provides a mechanism to access stack data in high level languages 5 3 2 Segment Registe...

Page 93: ...ted mode IOPL indicates the maximum current privilege level CPL permitted to execute I O instructions without generating an exception 13 fault or consulting the I O permission bit map IOPL also indica...

Page 94: ...ation Lookaside Buffers TLBs In Circuit Emulation ICE Provide for a alternative accessing path to support an ICE CPU identification Allow the BIOS and other software to identify the specific CPU and s...

Page 95: ...ating mode of the L1 and L2 caches LCD and LWT Local Cache Disable and Local Write through bits in the Translation Lookaside Buffer control the mode on a page by page basis Additionally memory configu...

Page 96: ...truction enabled for all CPL states 1 RDTSC instruction enabled for CPL 0 only 1 0 RSVD Reserved Set to 0 always returns 0 when read Table 5 8 CR3 Bit Descriptions Bit Name Description 31 12 PDBR Page...

Page 97: ...privilege level 0 2 WP 1 forces a fault on a write to a read only page from any privilege level 15 6 RSVD Reserved 5 NE Numerics Exception NE 1 to allow FPU exceptions to be handled by interrupt 16 NE...

Page 98: ...cts of Various Combinations of EM TS and MP Bits CR0 3 1 Instruction Type TS EM MP WAIT ESC 0 0 0 Execute Execute 0 0 1 Execute Execute 1 0 0 Execute Fault 7 1 0 1 Fault 7 Fault 7 0 1 0 Execute Fault...

Page 99: ...h R W GLD SMI MSR GLD_MSR_SMI Not Used 00000000_00000000h Page 109 00002003h R W GLD Error MSR GLD_MSR_ERROR Not Used 00000000_00000000h Page 109 00002004h R W GLD Power Management MSR GLD_MSR_PM Not...

Page 100: ...R W SS Segment Selector Flags Register SS_SEL_MSR xxxxxxxx_xxxxxxxxh Page 131 00001323h R W DS Segment Selector Flags Register DS_SEL_MSR xxxxxxxx_xxxxxxxxh Page 131 00001324h R W FS Segment Selector...

Page 101: ...d Debug Registers 5 and 4 MSR XDR5_XDR4_MSR FFFFFFFF_00000000h Page 138 00001353h R W Extended Debug Registers 7 and 6 MSR XDR7_XDR6_MSR xxxxxxxx_xxxxxxxxh Page 138 00001354h R W Extended Debug Regist...

Page 102: ...00000000_00000000h Page 148 00001414h R W General Register Temp 4 MSR GR_TEMP4_MSR 00000000_00000000h Page 148 00001415h R W General Register Temp 5 MSR GR_TEMP5_MSR 00000000_00000000h Page 148 00001...

Page 103: ...MSR RCONF_BYPASS_MSR 00000000_00000101h Page 165 Warm Start Value 00000000_00000219h 0000180Bh R W Region Configuration A0000 BFFFF MSR RCONF_A0_BF_MSR 01010101_01010101h Page 165 Warm Start Value 191...

Page 104: ...DC_DATA_MSR 00000000_00000000h Page 173 00001892h R W Data Cache Tag MSR DC_TAG_MSR 00000000_00000000h Page 173 00001893h R W Data Cache Tag with Increment MSR DC_TAG_I_MSR 00000000_00000000h Page 174...

Page 105: ...ller Extended Debug Registers 1 and 0 MSR BXDR1_BXDR0_MSR 00000000_00000000h Page 194 00001951h R W Bus Controller Extended Debug Registers 3 and 2 MSR BXDR3_BXDR2_MSR 00000000_00000000h Page 194 0000...

Page 106: ...6_MSR xxxxxxxx_xxxxxxxxh Page 205 00001A4Dh R W Exponent of R6 MSR FPU_ER6_MSR 00000000_0000xxxxh Page 206 00001A4Eh R W Mantissa of R7 MSR FPU_MR7_MSR xxxxxxxx_xxxxxxxxh Page 205 00001A4Fh R W Expone...

Page 107: ...05A1h Page 207 00003009h R W Extended Feature Flags CPUID9_MSR C0C0A13D_00000000h Page 207 0000300Ah R W CPU Marketing Name 1 CPUIDA_MSR 4D542865_646F6547h Page 207 0000300Bh R W CPU Marketing Name 2...

Page 108: ..._ID Device ID Identifies device 0864h 7 0 REV_ID Revision ID Identifies device revision See AMD Geode LX Processors Specification Update document for value MSR Address 00002001h Type R W Reset Value 0...

Page 109: ...er Management MSR GLD_MSR_PM This register is not used in the CPU Core module 5 5 1 6 GLD Diagnostic Bus Control MSR GLD_MSR_DIAG This register is reserved for internal use by AMD and should not be wr...

Page 110: ...s Controller Configuration 0 Register MSR 00001900h contains configuration bits that determine if TSC counts during SMM DMM or Suspend modes Writes to this register clears the upper DWORD to 0 The low...

Page 111: ...44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD PERF_CNT1 High Byte 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PERF_CNT1 Low DWORD PERF_CNT1_MSR Bit Descriptions...

Page 112: ...11 10 9 8 7 6 5 4 3 2 1 0 G D RSVD P DPL S X C R A CS_SEL TI RPL SYS_CS_MSR Bit Descriptions Bit Name Description 63 32 RSVD Reserved 31 G RO Granularity Read Only Code segment limit granularity is 4...

Page 113: ...45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ESP SYS_SP_MSR Bit Descriptions Bit Name Description 63 32 RSVD Re...

Page 114: ...ounters 21 16 RSVD Reserved Write as read 15 8 PC0_UMASK Performance Event Counter 0 Unit Mask Selects sub events 00h All sub events counted 7 0 PC0_EVENT Performance Event Counter 0 Event Select Valu...

Page 115: ...I_SER RSVD II_IMFLSH RSVD CC_L0 RSVD DMM_DIS RSVD CC_PS RSVD STRONG RSVD RS RSVD CC_INVL RSVD CC_L1 IF_CONFIG_MSR Bit Descriptions Bit Name Description 63 48 RSVD Reserved 47 BETD Branch Tree Messagin...

Page 116: ...lized Default 1 IM Interface waits until IM responds to a request before IM Interface issues the next request Note Enabling IM Interface serialization reduces performance 15 RSVD Reserved 14 II_IMFLSH...

Page 117: ...ess CC_L1 is enabled bit 0 1 then the return stack has no effect 3 RSVD Reserved 2 CC_INVL COF Cache Invalidation 0 Translation Look aside Buffer TLB invalidations do not invalidate the COF cache Defa...

Page 118: ...alue 00000000_00000000h IF_INVALIDATE_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 119: ...ess of the RAM loca tion 0 255 When accessing the L0 COF cache indexes 0 1 refer to the 2 tag entries 4 5 refer to the 2 source addresses 8 9 refer to the 2 target addresses and 12 13 refer to the 2 r...

Page 120: ...for Level 0 COF Cache Tag 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7...

Page 121: ...41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TARGET 31 0 IF_TEST_DATA_MSR Bit Descriptions for Level 0 COF Cache Target Bit...

Page 122: ...D Valid Instruction Decode Speculative ID speculative return stack entries that are valid The lease significant entry is the next to be popped from the stack Default 0 15 8 IF_SPEC_VLD Valid Instructi...

Page 123: ...cache is enabled reading IF_BIST_MSR does not cause BIST to be run and returns zero After BIST has been run by reading IF_BIST_MSR the contents of the IF Tag RAMs is invalidated cleared MSR Address 0...

Page 124: ...00000000h XC_CONFIG_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11...

Page 125: ...Busy Read Only FP is reporting that it is not idle 11 IP_BUSY RO Instruction Pipeline Busy Read Only IP is reporting that it is not idle 10 DM_BUSY RO Data Memory Subsystem Busy Read Only DM is repor...

Page 126: ...YPE3 Exception Type 3 14 10 TYPE2 Exception Type 2 9 5 TYPE1 Exception Type 1 4 0 TYPE0 Exception Type 0 Note 1 Table 5 14 shows the definition of the types in the XC_HIST MSR Table 5 14 XC_HIST_MSR E...

Page 127: ...ddress for Exception 1 11 0 UADDR0 Microcode Address for Exception 0 Most recent exception MSR Address 00001250h Type R W Reset Value 00000000_00000002h ID_CONFIG_MSR Register Map 63 62 61 60 59 58 57...

Page 128: ...on 63 6 RSVD RO Reserved Read Only 5 SMI_EXTL Enable External ASMI Pin Enable external asynchronous SMIs 0 Disable 1 Enable 4 SMI_IO Enable I O Generated SMI Enable SMIs caused by an I O instruction 0...

Page 129: ...on of each instruc tion If DMI_STALL is 1 debug stall occurs after the successful execution of each instruction 8 DMI_STALL DMI Stall 0 If not in DMM DMI conditions cause DMIs 1 DMI conditions cause a...

Page 130: ...DMI Control Register Bit Descriptions Continued Bit Name Description MSR Address 00001310h Type R W Reset Value xxxxxxxx_xxxxxxxxh MSR Address 00001311h Type R W Reset Value xxxxxxxx_xxxxxxxxh MSR Add...

Page 131: ...s 00001322h Type R W Reset Value xxxxxxxx_xxxxxxxxh MSR Address 00001323h Type R W Reset Value xxxxxxxx_xxxxxxxxh MSR Address 00001324h Type R W Reset Value xxxxxxxx_xxxxxxxxh MSR Address 00001325h Ty...

Page 132: ...ator LDT GDT 1 0 RPL Requestor Privilege Level MSR Address 0000132Bh Type R W Reset Value 00000000_00000000h SMM_HDR_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42...

Page 133: ...00000000h DMM_HDR_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 1...

Page 134: ...h Type R W Reset Value xxxxxxxx_xxxxxxxxh MSR Address 00001331h Type R W Reset Value xxxxxxxx_xxxxxxxxh MSR Address 00001332h Type R W Reset Value xxxxxxxx_xxxxxxxxh MSR Address 00001333h Type R W Res...

Page 135: ...ruction MSR Address 00001340h Type R W Reset Value xxxxxxxx_xxxxxxxxh DR1_DR0_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 DR1 31 30...

Page 136: ...G0 L0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD FFFFh BT BS BD RSVD FFh B3 B2 B1 B0 DR7_DR6_MSR Bit Descriptions Bit Name Description 63 62 LEN3 Break...

Page 137: ...0000h XDR1_XDR0_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 XDR1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

Page 138: ...PREFIX_MASK4 Prefix Mask Value for Extended Breakpoint 4 55 32 OPCODE_MASK4 Opcode Mask Value for Extended Breakpoint 4 31 PN REPNE REPNZ Prefix Value for Extended Breakpoint 4 30 PR REP REPE REPZ Pr...

Page 139: ...d 38 E6 Extended Breakpoint 6 Enable 37 E5 Extended Breakpoint 5 Enable 36 E4 Extended Breakpoint 4 Enable 35 E3 Extended Breakpoint 3 Enable 34 E2 Extended Breakpoint 2 Enable 33 E1 Extended Breakpoi...

Page 140: ...6 5 4 3 2 1 0 PREFIX_VALUE5 OPCODE_VALUE5 PN PR PL PC PS PO PA PF XDR9_XDR8_MSR Bit Descriptions Bit Name Description 63 56 PREFIX_MASK5 Prefix Mask Value for Extended Breakpoint 5 55 32 OPCODE_MASK5...

Page 141: ...42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD IO_PORT XDR11_XDR10_MSR Bit Descriptions Bit Name Description 63 16 RS...

Page 142: ...49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WB_IP WB_IP_MSR Bit Descriptions Bit Name Description 6...

Page 143: ...26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WB_LIP WB_LIP_MSR Bit Descriptions Bit Name Description 63 32 RSVD Reserved 31 0 WB_LIP WB Stage Linear Instruction Pointer MSR...

Page 144: ...6 35 34 33 32 C3_LIP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C2_LIP C3_C2_LIP_MSR Bit Descriptions Bit Name Description 63 32 C3_LIP CS 3 Linear Instructi...

Page 145: ...FPENV_IP_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7...

Page 146: ...FPENV_DP_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6...

Page 147: ..._CONFIG_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6...

Page 148: ...e R W Reset Value 00000000_00000000h MSR Address 0000140Ch Type R W Reset Value 00000000_00000000h MSR Address 0000140Dh Type R W Reset Value 00000000_00000000h MSR Address 0000140Eh Type R W Reset Va...

Page 149: ...7 6 5 4 3 2 1 0 RSVD 0 ID RSVD 0 AC VM RF RSVD 0 NT IOPL OF DF IF TF SF ZF RSVD 0 AF RSVD 0 PF RSVD 1 CF EFLAG_MSR Bit Descriptions Bit Name Description 63 22 RSVD Reserved Default 0 21 ID Identificat...

Page 150: ...1 Locked 23 17 RSVD Reserved 16 DRT Dynamic Retention Test Allow dynamic retention test for BIST of tag array 0 Disable Default 1 Enable 15 12 RSVD Reserved Default 0 11 ABSE Aborts for Speculative In...

Page 151: ...isable Default 1 Enable 6 RSVD Reserved Always write zero 5 L0D L0 Cache Disable 0 Disable Default 1 Enable 4 L0IN L0 Cache Invalidate 0 Disable Default 1 Enable 3 RSVD Reserved 2 SER Serialize Cache...

Page 152: ...der bits of an 11 bit counter The LINE field bits 6 0 forms the low seven bits of the counter This field increments when the LINE field overflows on a access to IC_TAG_I_MSR MSR 00001713h This field i...

Page 153: ...1 Bit 46 Ways 15 8 more recent than ways 7 0 Bit 45 Ways 15 12 more recent than ways 11 8 Bit 44 Ways 15 14 more recent than ways 13 12 Bit 43 Way 15 more recent than way 14 Bit 42 Way 13 more recent...

Page 154: ...pt read write of this register causes an auto increment on the IC_INDEX_MSR MSR 00001710h MSR Address 00001714h Type RO Reset Value xxxxxxxx_xxxxxxxxh L0_IC_DATA_MSR Register Map 63 62 61 60 59 58 57...

Page 155: ...ing Furthermore the L1 Instruction TLB is flushed on any mode change so a debug handler would no longer see the TLB con tents prior to the DMI Thus the L1 Instruction TLB accesses are intended only to...

Page 156: ...more recent than entries 4 7 Bit 23 Entry 14 more recent than entry 15 Bit 22 Entry 13 more recent than entry 15 Bit 21 Entry 13 more recent than entry 14 Bit 20 Entry 12 more recent than entry 15 Bit...

Page 157: ...48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 LINADDR RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PHYSADDR WS RSVD CD RSVD US RSVD V ITB_ENTRY_MSR...

Page 158: ...00001730h Type RO Reset Value 00000000_0000000xh IM_BIST_TAG_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25...

Page 159: ...DM to escape a snoop deadlock by timing out a snoop request to the DM tag machine 0 Disable 1 Enable Default 47 RSVD Reserved Default 0 46 44 WSREQ Number of Outstanding Write Serialized Requests The...

Page 160: ...fetched and non prefetched ways Only the non prefetched ways would be evicted into the L2 Default 0 14 EVCTONRPL Evict Clean Lines on Replacement This bit should be set when an external L2 cache is op...

Page 161: ...ates snoops on stores for detecting self modified code 0 Generate snoops Default 1 Disable snoops 3 NOFWD Forward Data from Bus Controller Enable forwarding of data directly from bus control ler if a...

Page 162: ...e when a fill is issued for an even cache line but no auto prefetch is issued for a fill on an odd cache line For example when a fill request is issued for address 0h a prefetch will be issued for add...

Page 163: ...sable Mask used to disable individual cache arrays way groups in the DM to save power or to avoid array defects When an array is disabled the DM will not read or write the data array or tag array asso...

Page 164: ...nstruction If all ways are locked PREFETCHNTA is effectively disabled Use this field to prevent data prefetch operations from polluting too much of the cache Default 0 MSR Address 00001808h Type R W R...

Page 165: ...t 2 WP Bit 1 WA Bit 0 CD See Region Properties on page 170 for further details MSR Address 0000180Bh Type R W Reset Value 01010101_01010101h Warm Start Value 19191919_19191919h RCONF_A0_BF_MSR Registe...

Page 166: ...FF 55 48 RPD8 Region Properties for 000D8000 000DBFFF 47 40 RPD4 Region Properties for 000D4000 000DAFFF 39 32 RPD0 Region Properties for 000D0000 000D3FFF 31 24 RPCC Region Properties for 000CC000 00...

Page 167: ...details MSR Address 0000180Eh Type R W Reset Value 00000001_00000001h Warm Start Value xxxxx001_xxxxx005h RCONF_SMM_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 4...

Page 168: ...11 10 9 8 7 6 5 4 3 2 1 0 DMMBASE RSVD RPDMM_EN DMM_NORM RCONF_DMM_MSR Register Bit Descriptions Bit Name Description 63 44 DMMTOP Top of DMM Top of DMM region 4 KB granularity inclusive 43 40 RSVD Re...

Page 169: ...x000_xxxxx0xxh MSR Address 00001814h Type R W Reset Value 00000000_00000000h Warm Start Value xxxxx000_xxxxx0xxh MSR Address 00001815h Type R W Reset Value 00000000_00000000h Warm Start Value xxxxx000...

Page 170: ...ed Writes to the region are discarded 1 x x x x 0 Undefined State Unpredictable behavior occurs x 1 x x x 0 Undefined State Unpredictable behavior occurs x x x x 1 1 Undefined State Unpredictable beha...

Page 171: ...der is not preserved ideal for use with frame buffers Write serialize Limit the number of outstanding writes to the value of the WSREQ field in DM_CONFIG0_MSR MSR 00001800h 46 44 0 1 1 0 0 1 Write bur...

Page 172: ...1890h Type R W Reset Value 00000000_00000000h DC_INDEX_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23...

Page 173: ...buffer The buffer is filled from the cache data array on a read to DC_TAG_MSR MSR 00001892h or DC_TAG_I_MSR MSR 00001893h and the buffer is written to the cache data array on a write to DC_TAG_MSR or...

Page 174: ...cent than way 14 Bit 38 Way 13 more recent than way 12 Bit 37 Way 11 more recent than way 10 Bit 36 Way 9 more recent than way 8 Bit 35 Way 7 more recent than way 6 Bit 34 Way 5 more recent than way 4...

Page 175: ...0 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SNOOP_ADD SNOOP_MSR Bit Descriptions Bit Name Description 63 32 RSVD Reserved Write...

Page 176: ...12 15 Bit 16 Entries 4 7 more recent than entries 12 15 Bit 15 Entries 4 7 more recent than entries 8 11 Bit 14 Entries 0 3 more recent than entries 12 15 Bit 13 Entries 0 3 more recent than entries 8...

Page 177: ...Flag If the page is cacheable a 1 indicates the write allocate flag If the page is non cacheable a 1 indicates the write serialize flag 32 WC Write combine Flag When this page is marked as non cacheab...

Page 178: ...00000000_00000000h L2TLB_INDEX_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15...

Page 179: ...more recent than entries 4 7 Bit 51 DTE entries 0 3 more recent than entries 8 11 Bit 50 DTE entries 4 7 more recent than entries 8 11 Bit 49 DTE entry 8 more recent than entry 9 Bit 48 DTE entry 8 m...

Page 180: ...58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 LINADDR RSVD WP WA_WS WC LINADDR RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 181: ...ntry in the TLB is valid If SEL bits in L2TLB_INDEX MSR 1x MSR 0000189Ch 17 16 1x 63 44 LINADDR Linear Address Address 32 22 53 32 RSVD RO Reserved Read Only 31 12 PHYSADDR Physical Address Address 32...

Page 182: ...00000000_00000000h DM_BIST_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 TAGCMP TAGDAT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1...

Page 183: ...ion BC_CONFIG0_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...

Page 184: ...C_DMM Time Stamp Counter Counts during DMM 0 Disable Default 1 Enable 5 TSC_SUSP Time Stamp Counter Counts during Suspend 0 Disable Default 1 Enable 4 TSC_SMM Time Stamp Counter Counts during SMM 0 Di...

Page 185: ..._LOCK MSR_LOCK_MSR Bit Descriptions Bit Name Description 63 1 RSVD Reserved Write as read 0 MSR_LOCK Lock MSRs The CPU Core MSRs above 0xFFF with the exception of the MSR_LOCK register itself are lock...

Page 186: ...te real time measurement that includes these times BC_CONFIG0_MSR MSR 00001900h contains configuration bits that determine if the RTSC counts during Suspend mode It always counts during SMM and DMM mo...

Page 187: ...Gating Enable If set the L2 tags would be clocked only when accessed Otherwise the tags would be clocked whenever the bus controller clocks are active Default 0 7 L2_PASS_ IOMSR L2 Cache always Pass I...

Page 188: ...D L2_IDLE L2_STATUS_MSR Bit Descriptions Bit Name Description 63 1 RSVD Reserved 0 L2_IDLE L2 Cache Idle Returns 1 if the L2 cache controller is idle Default 1 MSR Address 00001922h Type R W Reset Val...

Page 189: ...0000000_00000000h L2_TAG_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13...

Page 190: ...RSVD L2_MRU RSVD L2_VALID MSR Address 00001926h Type R W Reset Value 00000000_00000000h L2_BIST_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35...

Page 191: ...ntion Timer BIST Enable Enable the data retention timer for the MRU BIST 0 Disable Default 1 Enable 4 BIST_MRU_EN L2 Cache Most Recently Used BIST Enable Start MRU BIST on a write 0 Disable Default 1...

Page 192: ...ag state machine to reset Caution Extremely destructive use only to poke around on hard hangs Default 0 15 RSVD Reserved 14 12 IMEVCT_INVAL _CODE Instruction Memory Subsystem Eviction Invalidate Code...

Page 193: ...TED PMODE_MSR Bit Descriptions Bit Name Description 63 19 RSVD Reserved 18 IRS_IF Reserved Instruction Fetch Reserved for possible future clock gating of IF Default 0 17 IRS_IMTAG Reserved Instruction...

Page 194: ...efault 0 31 0 BXDR0_PHYS_ ADDR Address Match Value for BXDR0 This field specifies addresses that must match the physical address currently in the bus controller in order to trigger the extended break...

Page 195: ...N0 RSVD E3 E2 E1 E0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD T3 T2 T1 T0 BXDR6_BXDR7_MSR Bit Descriptions Bit Name Description BXDR7 63 60 TYPE3 Exten...

Page 196: ...e 1 Enable 32 E0 Extended Breakpoint 0 Enable Allows extended breakpoint 0 to be enabled 0 Disable 1 Enable BXDR6 31 4 RSVD Reserved 3 T3 Extended Breakpoint 3 Triggered A 1 Indicates that extended br...

Page 197: ...ug Register 0 MSR BDR0_MSR Bus Controller Debug Register 1 MSR BDR1_MSR Bus Controller Debug Register 2 MSR BDR2_MSR Bus Controller Debug Register 3 MSR BDR3_MSR MSR Address 00001970h Type R W Reset V...

Page 198: ...11 10 9 8 7 6 5 4 3 2 1 0 RSVD T3 T2 T1 T0 BDR6_MSR Bit Descriptions Bit Name Description 63 4 RSVD Reserved Default 0 3 T3 Breakpoint 3 Triggered A 1 Indicates that breakpoint 3 has triggered Write...

Page 199: ...ects the type of extended breakpoint 2 See TYPE3 bits 31 28 for decode 23 20 TYPE1 Breakpoint 1 Type Selects the type of extended breakpoint 1 See TYPE3 bits 31 28 for decode 19 16 TYPE0 Breakpoint 0...

Page 200: ...Description 63 1 RSVD Reserved Default 0 0 EN Enable Enable the array control values in this register to be used instead of those pro vided by the clock modules 0 Disable 1 Enable MSR Address 00001981...

Page 201: ...uction Memory Subsystem Data 0 Delay Control Default 82 11 6 IMTAG1 Instruction Memory Subsystem Tag 1 Delay Control Default F 5 0 IMTAG0 Instruction Memory Subsystem Tag 0 Delay Control Default F MSR...

Page 202: ...control bits in the x87 Mode Control register of the FPU Instruction Set and causes the FPU to operate as if the precision control is set to single precision 00 0 Disable 1 Enable limit to single prec...

Page 203: ...63 12 RSVD Reserved Write as read 11 0 FPU_CW FPU Control Word MSR Address 00001A11h Type R W Reset Value 00000000_00000000h FPU_SW_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47...

Page 204: ...2 1 0 RSVD FPU_BUSY FPU_BUSY_MSR Bit Descriptions Bit Name Description 63 1 RSVD Reserved Reads back as 0 0 FPU_BUSY FPU Busy Software must check that the FPU is Idle before accessing MSRs 00001A10h 0...

Page 205: ...xxxh MSR Address 00001A48h Type R W Reset Value xxxxxxxx_xxxxxxxxh MSR Address 00001A4Ah Type R W Reset Value xxxxxxxx_xxxxxxxxh MSR Address 00001A4Ch Type R W Reset Value xxxxxxxx_xxxxxxxxh MSR Addre...

Page 206: ...00001A49h Type R W Reset Value 00000000_0000xxxxh MSR Address 00001A4Bh Type R W Reset Value 00000000_0000xxxxh MSR Address 00001A4Dh Type R W Reset Value 00000000_0000xxxxh MSR Address 00001A4Fh Typ...

Page 207: ...Address 00003001h Type R W Reset Value 69746E65_444D4163h MSR Address 00003002h Type R W Reset Value 00000400_000005A2h MSR Address 00003003h Type R W Reset Value 0088A93D_00000000h MSR Address 000030...

Page 208: ...n 80000000 EBX EAX 63 0 CPUID7 CPUID Max Extended Levels Same data as CPUID instruction 80000000 EDX ECX 63 0 CPUID8 Extended Type Family Model Stepping Same data as CPUID instruction 80000001 EBX EAX...

Page 209: ...Mgmnt GeodeLink SDCLKs TLB Integer Unit MMU Load Store FPU 64 KB L1 D cache 64 KB L1 I cache Bus Controller CPU Core Alpha Compositing ROP Unit BLT Engine Graphics Processor GP Timing Palette RAM Comp...

Page 210: ...e maximum configuration is four module banks with four component banks each pro viding a total of 16 open banks with the maximum memory size supported being 2 GB The GLMC handles multiple requests for...

Page 211: ...ving High Order Interleaving HOI uses the most significant address bits to select which bank the page is located in Figure 6 3 shows an example of how the Geode LX pro cessor s internal physical addre...

Page 212: ...in a system Table 6 1 shows a one DIMM bank conversion example while Table 6 2 shows a two DIMM bank example Tables 6 3 and 6 4 on page 214 show Non Auto LOI address conversion examples when either o...

Page 213: ...2 A3 A13 A3 A14 A3 A13 A3 A14 A3 A15 A3 CS0 CS1 A11 A12 A13 A12 A13 A14 CS2 CS3 BA0 BA1 A10 A11 A12 A11 A10 A12 A11 A13 A12 Table 6 2 LOI 2 DIMMs Same Size 2 DIMM Banks 1 KB Page Size 2 KB Page Size 4...

Page 214: ...A4 A14 A4 A15 A4 MA0 A11 A3 A12 A3 A13 A3 A12 A3 A13 A3 A14 A3 CS0 CS1 CS2 CS3 BA0 BA1 A10 A11 A12 A11 A10 A12 A11 A13 A12 Table 6 4 Non Auto LOI 1 or 2 DIMMs Different Sizes 2 DIMM Banks 1 KB Page S...

Page 215: ...e priori ties are sorted out as per criterion 1 and so on Requests in the C and O slots are run before the request at the GLIU0 interface if the DRAM is ready to receive them The GLIU0 interface reque...

Page 216: ...he buffers on the GLIU0 clock which is twice the frequency of the GLMC SDRAM clock The data strobes DQS are also shipped out with each data beat center aligned with the data to strobe the data into th...

Page 217: ...H Figure 6 9 DDR Writes mph1 m_sd_data drdyrx rqin_ready dain rqin_take wrx0 wrx1 wrx2 wrx3 drdywx wry0 dain_ready dain_take rqin WRREQY WRREQX wrx0 wrx1 wrx2 wrx3 wry0 w_databuf_out daout wrrespx wrr...

Page 218: ...e1 Save to RAM is only entered on sufficiently long idle periods 3 Set PMode1 in MSR 20002004h 2 to 1 to enable PMode1 On the next GLMC idle condition that is longer than the value in PM1_SENS the GLM...

Page 219: ...Page 222 Table 6 6 GLMC Specific MSR Summary MSR Address Type Register Name Reset Value Reference 20000010h RO Row Addresses Bank0 DIMM0 Bank1 DIMM0 MC_CF_BANK01 xxxxxxxx_xxxxxxxxh Page 223 20000011h...

Page 220: ...Value 00000000_000204xxh Table 6 6 GLMC Specific MSR Summary MSR Address Type Register Name Reset Value Reference GLD_MSR_CAP Register 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42...

Page 221: ...ites of 1 clears the error The GLMC only implements the type excep tion error on bit 16 which is set when the GLIU request s type field is either an I O type or snoop type This bit will be set on such...

Page 222: ...losing all banks with a precharge all command to the DIMMs 2 issuing a self refresh command 3 bringing CKE1 and CKE0 balls F4 and E4 respectively low and putting the address and control pins in TRI_ST...

Page 223: ...0 53 32 MC_CF_BANK1 Memory Configuration Back 1 Open row address 31 10 for Bank1 DIMM0 31 22 RSVD Reserved Reads back as 0 21 0 MC_CF_BANK0 Memory Configuration Back 0 Open row address 31 10 for Bank...

Page 224: ...mory Controller Configuration Bank 5 Open row address 31 10 for Bank5 DIMM0 31 22 RSVD Reserved Reads back as 0 21 0 MC_CF_BANK4 Memory Controller Configuration Bank 4 Open row address 31 10 for Bank4...

Page 225: ...mory Controller Configuration Bank 9 Open row address 31 10 for Bank1 DIMM1 31 22 RSVD Reserved Reads back as 0 21 0 MC_CF_BANK8 Memory Controller Configuration Bank 8 Open row address 31 10 for Bank0...

Page 226: ...mory Controller Configuration Bank C Open row address 31 10 for Bank5 DIMM1 31 22 RSVD Reserved Reads back as 0 21 0 MC_CF_BANKC Memory Controller Configuration Bank B Open row address 31 10 for Bank4...

Page 227: ...1 Size 0000 Reserved 0100 64 MB 1000 1 GB 0001 8 MB Default 0101 128 MB 1001 1111 Reserved 0010 16 MB 0110 256 MB 0011 32 MB 0111 512 MB 59 57 RSVD Reserved 56 D1_MB DIMM1 Module Banks Number of modul...

Page 228: ...QFC signal provides control for FET switches that are used to isolate module loads from the system memory busy at times when the given module is not being accessed Only pertains to x4 configurations 0...

Page 229: ..._BA bits 29 28 00 or the Extended Mode Register if MSR_BA bits 29 28 01 The Mode Register is programmed with CAS latency see MSR 2000019h 30 28 wrap type sequential and burst length of 4 for 64 bit da...

Page 230: ...be used during debug Default 0 bursts enabled 40 REORDER_DIS Reorder Disable Disables the reordering of requests This bit must be set to 1 39 34 RSVD Reserved 33 HOI_LOI High Low Order Interleave Sele...

Page 231: ...43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD WR_TO_RD RSVD RD_TMG_CTL RSVD REF2ACT PM1_UP_DLY RSVD WR2DAT MC_CF10...

Page 232: ...ister Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 CNT1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT...

Page 233: ...scriptions Bit Name Description 63 36 RSVD Reserved 35 STOP_CNT1 Stop Counter 1 If set stops counter 1 Default 0 34 RST_CNT1 Reset Counter 1 If set resets counter 1 Default 0 33 STOP_CNT0 Stop Counter...

Page 234: ...mand only gets issued conditionally before a load mode or refresh command only if the module banks are not all closed yet With this bit set the precharge all will be issued uncondition ally before the...

Page 235: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD PGOPEN1 PGOPEN0 MC_CFPG_OPEN Bit Descriptions Bit Name Description 63 16 RSVD Reserved Reads back as 0 15 8 PGOPEN1 Page Open DIMM 1 Page open indication of th...

Page 236: ...e1 power down mode If PMode1 is enabled PM1_SENS starts counting down from its loaded value whenever the GLMC becomes idle If it times out and the GLMC is still idle the GLMC goes into PMode1 If howev...

Page 237: ...to the Graphics Processor include Command buffer interface Hardware accelerated rotation BLTs Color depth conversion Palletized color Full 8x8 color pattern buffer Channel 3 third DMA channel Monochro...

Page 238: ...led rep movs writes Accelerated Text No No Pattern Size Mono 8x8 pixels 8x8 pixels Pattern Size Color 8x1 32 pixels 8x8 pixels 8x2 16 pixels 8x4 8 pixels Monochrome Pattern Yes Yes with inversion Dith...

Page 239: ...ry at the write address GP_CMD_WRITE then updating the write address to point to the next available space in the command buffer either the next contiguous DWORD address or the buffer starting address...

Page 240: ...A_0 Data GP_PAT_DATA_1 Data GP_CH3_MODE_STR Data GP_BASE_OFFSET Data GP_VECTOR_MODE Data Table 6 10 LUT Lookup Table Load Command Buffer Structure 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14...

Page 241: ...ATUS Channel 3 has the ability to begin prefetching data for a pending BLT before the active BLT has completed The PE bit in the GP_CH3_MODE_STR register GP Memory Off set 64h 19 can be set to allow p...

Page 242: ...from GP_DEST_OFFSET For all rotations it is required that both the source stride and the destination stride be aligned to a cache line bound ary i e bottom 5 bits of stride are all 0s Do not attempt t...

Page 243: ...that will be loaded into the LUT starting at that address The address automatically increments with every write Addresses 00h FFh are used for 8 bpp indexed pixels and addresses 00h 0Fh are used for 4...

Page 244: ...to the depth specified in the BPP FMT GP bits Memory Offset 38h 31 28 of the GP_RASTER_MODE register if the two depths do not match 6 3 2 7 Patterned Vectors When pattern mode is enabled during a vec...

Page 245: ...o carry desti nation data when it cannot be carried on either of the other two channels This should only be the case when the ROP calls for source destination and pattern when the opera tion is a vect...

Page 246: ...Pending bit in the GP_BLT_STATUS register GP Memory Offset 44h 2 The GP_PAT_COLOR_2 through GP_PAT_COLOR_5 GP Memory Offset 20h 2Ch registers are not pipelined If they are used in a new graphics oper...

Page 247: ...mode where only an 8x4 pattern fits the stride value could be doubled such that all of the even lines would be BLTed during the first pass and all of the odd lines during the second pass The pattern r...

Page 248: ...Byte 3 Byte 2 Byte 1 Byte 0 GP_PAT_DATA_1 02024002h GP_PAT_DATA_0 40024002h 02 02 40 02 40 02 40 02 GP_PAT_COLOR_1 0240E340h GP_PAT_COLOR_0 0240E340h 02 40 E3 403 02 40 E3 40 GP_PAT_COLOR_3 40E300E3h...

Page 249: ...depth specified by the GP_RASTER_MODE register 6 3 8 Source Data When called for by the raster operation or alpha blender software should set the source required bits in the GP_BLT_MODE register GP Me...

Page 250: ...e BLT is corrupt and most likely will not complete Since there is not enough host source data left the Graphics Processor hangs waiting for more source data The two LSBs of the source OFFSET are used...

Page 251: ...d GP_SRC_COLOR_BG GP Memory Offset 14h is loaded with FFh perform compare on all bits To make all pixels transparent that have more than 50 in their alpha chan nel for 32 bpp data load GP_SRC_COLOR_FG...

Page 252: ...ain Table 6 27 describes the various ways that the two images can be composited using the alpha blender For some of these cases a third alpha value in addition to the image stream data alphas is neede...

Page 253: ...n transparent otherwise display B 001 000 00 10 A xor B 1 B 1 A Display images only where they do not overlap 001 000 01 10 darken A R 0 Multiply RGB channels of image A by specified value Use enables...

Page 254: ...ing those bits which may be used in some future implementation of the GP Reserved register bits that do not have a register backing them always return a 0 regardless of what value software decides to...

Page 255: ...OFFSET 01004010h Page 270 50h R W Command Buff Command Top GP_CMD_TOP 01000000h Page 270 54h R W Command Buff Command Bottom GP_CMD_BOT 00FFFFE0h Page 271 58h R W Command Buff Command Read GP_CMD_READ...

Page 256: ...23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD CLKDOM DID RID GLD_MSR_CAP Bit Descriptions Bit Name Description 63 27 RSVD Reserved 26 24 CLKDOM Clock Domain Number of clock domain...

Page 257: ...ot set The error bits remain asserted until they are cleared An illegal address is defined as a memory mapped access to an address offset greater than 07Fh or an MSR access to an address greater than...

Page 258: ...for internal use by AMD and should not be written to GLD_MSR_ERROR Bit Descriptions Bit Name Description 63 18 RSVD Reserved Read returns 0 17 AE Address Error 1 indicates address violation Write 1 c...

Page 259: ...o fields the OFFSET and XLSBS The OFFSET is a pointer which when added to the source base address gives the memory location of the byte containing the first pixel of the BLT As in the destination offs...

Page 260: ...ression is enabled Refer to DC Memory Offset 034h 15 0 for frame buffer pitch Display Controller restrictions do not apply to source stride When copying from on screen frame buffer space e g window mo...

Page 261: ...Description 31 16 S_STRIDE Source Stride Width of the source bitmap in bytes 15 0 D_STRIDE Destination Stride Width of the destination scan line in bytes GP Memory Offset 0Ch Type R W Reset Value 000...

Page 262: ...se the frame buffer will be written with the color data resulting from the raster operation If no source is required for a given BLT the value of this register is used as the default source data into...

Page 263: ...er If the result of the OR produces all ones for an entire pixel and transparency is enabled then the write of that pixel is inhibited and the destination data is unchanged This register should only b...

Page 264: ...a write to these registers in 8 bpp monochrome pattern mode takes the least significant data byte and replicates it in the four bytes of the register In 16 bpp monochrome pattern mode the least signif...

Page 265: ...ting Using Alpha on page 252 for information on alpha blending and compositing This register is byte writable to allow modification of the ROP and other control bits without having to rewrite the BPP...

Page 266: ...the alpha operation to be performed if enabled 00 a A 01 1 a B 10 A 1 a B 11 a A 1 a B Channel A is added in this case only if the selected is also from channel A 19 17 AS Alpha Select Chooses which a...

Page 267: ...or source pattern and destination when performing raster operations See Section 6 3 10 Raster Operations ROP on page 251 Alpha Value aR Alpha value that can be used for some of the alpha compositing o...

Page 268: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD CP TH X Y SM RSVD DR SR GP_BLT_MODE Bit Descriptions Bit Name Description 31 12 RSVD Reserved Write to 0 11 CP Checkpoint...

Page 269: ...fset 44h 5 register indicates that the GP can accept another cache line 32 bytes of data This register is also aliased to the address range 100h 3FFh to allow the processor to move large blocks of dat...

Page 270: ...ffer which can be checked by reading the CE bit in the GP_BLT_STATUS register GP Memory Offset 44h 4 or by verifying that GP_CMD_READ GP Memory Offset 58h and GP_CMD_WRITE GP Memory Offset 5Ch have th...

Page 271: ...re and is used in combination with GP_CMD_WRITE GP Memory Offset 5Ch to determine how much space is available in the command buffer for new commands However this register can be written A write to thi...

Page 272: ...LSBs of OFFSET must still be initialized with the byte location of the first source pixel in the host source data stream Nibble Select is used when the source is 4 bpp to give an offset within the sp...

Page 273: ...determined by the X and Y bits When this bit is set the GP_DST_OFFSET GP Memory Offset 00h should point to the upper left corner of the destination and the X and Y bits in the GP_BLT_MODE GP Memory Of...

Page 274: ...ha All others Undefined 23 RO Rotate Bitmap 0 Disable rotation 1 Enable rotation direction determined by X and Y See Section 6 3 2 1 Rotating BLTs on page 242 22 BGR BGR Mode applies only when 16 bpp...

Page 275: ...et This register is also aliased to the address range 400h FFFh allowing the processor to load large blocks of data to the GP using the repeat MOVS instruction GP Memory Offset 68h Type R W Reset Valu...

Page 276: ...T at the location specified by the GP_LUT_INDEX register Either a read or write of this register will cause the GP_LUT_INDEX register to increment so the LUT can be loaded through successive writes to...

Page 277: ...INT_CNTRL register Writing a 1 to an interrupt detect bit clears the bit Writing a 0 to an interrupt detect bit has no effect Therefore all of the interrupts in the GP may be cleared by reading the GP...

Page 278: ...ter face block a VGA block and back end scaling filter The GUI is compatible with the Display Controller found in the GX processor The VGA block provides hardware compati bility with the VGA graphics...

Page 279: ...e 6 13 GUI Block Diagram Compressed Graphics Decompressor Cursor Display FIFO Compressor Video 32 32 64 64 64 Display 24 Display CRT_HSYNC CRT_VSYNC ENA_DISP DCLK PCLK VID_CLK VID_DATA 32 0 PIXEL 31 0...

Page 280: ...host memory data manip ulation functions such as color compare set reset etc This block provides complete support for all VGA text and graphics modes Figure 6 14 VGA Block Diagram CRTC Pixel Formatte...

Page 281: ...the minimum relation ship of DOTCLK to GLIU frequency should be at the various color depths Bandwidth requirements for the VGA engine are not listed in this table Most graphics modes require the same...

Page 282: ...0 400 1920x1440 8 16 or 24 32 60 234 000 266 8 16 or 24 32 70 278 400 400 8 16 or 24 32 72 288 000 400 8 16 or 24 32 75 297 000 400 8 16 or 24 32 85 341 349 400 Television Modes 720x483 SD NTSC up to...

Page 283: ...hat is running When enabled the icon overlay is displayed on each active scan line The icon is 64 pixels wide and supports three colors plus transparency as shown in Table 6 34 The display of cursor a...

Page 284: ...in size The DC contains logic to address the overlay of the cursor on top of a color key region Table 6 35 indicates what pixel value is output from the DC s rendering engine when the cursor is overl...

Page 285: ...compressed line buffer 64x64 bits Lines will not be written back to the compressed display buffer in the DRAM unless a success ful compression has resulted so there is no penalty for pathological fra...

Page 286: ...The width of the video output port is 32 bits This allows the display of high resolution video source material up to 1920 horizontal pixels mixed with high resolution graphics data Table 6 36 illustra...

Page 287: ...m The DC can be pro grammed to fetch multiple fields worth of VBI data from lin ear frame buffer space without resetting to the start of the buffer on each field This minimizes the interrupt overhead...

Page 288: ...layed foreground background colors blink underline etc There are two formats defined by BIOS for the attribute byte color and monochrome as shown in Table 6 40 Graphics Modes The graphics modes define...

Page 289: ...read and write modes are supported that provide various forms of acceleration for VGA graphics operations A high level diagram of the graphics controller is shown in Figure 6 16 Figure 6 16 Graphics...

Page 290: ...6 17 shows the data flow logic that supports these modes Figure 6 17 Write Mode Data Flow CPU Data 7 0 Rotator Data Rotate 2 0 Set Reset 3 0 3 2 1 0 3 2 1 0 B WriteMode2 B B B B Enable Set Reset 3 0 3...

Page 291: ...allows the CPU to do a single color compare across eight pixels Figure 6 18 shows the data flow for read modes Figure 6 19 on page 292 shows how the color compare logic in Figure 6 18 works Figure 6...

Page 292: ...234H Figure 6 19 Color Compare Operation 8x4 Input AND Compare Result 7 0 CC3 CC2 CC1 CC0 Memory Data 31 0 31 24 23 16 15 8 7 0 Color Compare 3 0 3 2 1 0 Color Don t Care 3 0 3 2 1 0 D 7 0 C XOR OR CC...

Page 293: ...ns The filter coefficients are 10 bits wide Scaling is controlled by adjusting the horizontal and vertical filter scale factors through configuration register 90 These numbers represent binary rationa...

Page 294: ...34H Figure 6 20 Graphics Filter Block Diagram Continued 2 Pixel Latch x x x x x x 2 Pixel Latch H Coefficient RAM X X X X X Addresses for H Coefficient RAM from H Phase Adder The entire structure is r...

Page 295: ...tream to the Dot clock domain When the flicker filter is enabled the final image width is dictated by this final line buffer which is 1024 pixels wide When the flicker filter is disabled the two line...

Page 296: ...and 5 The result is a color key pixel the alpha value is set accordingly If the center pixel matches the color key it is passed through directly If the center pixel does not match the color key then a...

Page 297: ...inal Output Width Final Output Height Default no VGA scal ing interlacing or flicker filter H_ACTIVE V_ACTIVE H_ACTIVE V_ACTIVE H_ACTIVE V_ACTIVE Scaling only FB_H_ACTIVE FB_V_ACTIVE H_ACTIVE V_ACTIVE...

Page 298: ...lse width of one line Table 6 43 lists timings for various interlaced modes for ref erence The user should verify these timings against cur rent specifications for their application Table 6 44 on page...

Page 299: ...fp 1 even_active even_fp 1 V_Sync_End odd_active odd_fp odd_vsync 1 even_active even_fp even_vsync 1 525 V_Active_End F1 F0 V_Total 106 105 V_Sync_Start F5 F5 V_Sync_End F6 F6 625 V_Active_End 11F 11F...

Page 300: ...80002002h R W GLIU0 Device SMI MSR GLD_MSR_SMI 00000000_00000000h Page 306 80002003h R W GLD Error MSR GLD_MSR_ERROR 00000000_00000000h Page 308 80002004h R W GLD Power Management MSR GLD_MSR_PM 00000...

Page 301: ...ertical Blank Timing DC_V_BLANK_TIMING xxxxxxxxh Page 331 058h R W DC CRT Vertical Sync Timing DC_V_SYNC_TIMING xxxxxxxxh Page 331 05Ch R W DC Frame Buffer Active Region Register DC_FB_ACTIVE xxxxxxxx...

Page 302: ...C_CLR_KEY 00000000h Page 347 0BCh R W DC Color Key Mask DC_CLR_KEY_MASK 00xxxxxxh Page 348 0C0h R W DC Color Key Horizontal Position DC_CLR_KEY_X 00000000h Page 348 0C4h R W DC Color Key Vertical Posi...

Page 303: ...h Page 357 3CAh 3BAh or 3DAh Note 1 VGA Feature Control xxh Page 357 3C4h VGA Sequencer Index 0xh Page 358 3C5h VGA Sequencer Data xxh Page 358 3B4h or 3D4h Note 1 CRTC Index 00h Page 362 3B5h or 3D5h...

Page 304: ...Value Reference 0030h R W ExtendedRegisterLock FFh Page 385 043h R W ExtendedModeControl 00h Page 385 044h R W ExtendedStartAddress 00h Page 385 047h R W WriteMemoryAperture 00h Page 386 048h R W Rea...

Page 305: ...ssors Specification Update document for value MSR Address 80002001h Type R W Reset Value 00000000_00000000h GLD_MSR_CONFIG Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 4...

Page 306: ...erved Set to 0 48 ISR1R_SMI Input Status Register 1 Read SMI Reading a 1 indicates that the VGA Input Status Register 1 has been read writing this bit to 1 clears it 47 MISCIOR_SMI Miscellaneous Outpu...

Page 307: ...indicates that the ASMI corresponding to DC Ver tical Blank has been triggered Writing a 1 to this bit clears it and deactivates the ASMI signal writing a 0 has no effect 31 29 RSVD Reserved Set to 0...

Page 308: ...VGA s CRTC registers has been written 4 CRTCIO_MSK CRTC Invalid Register I O SMI Mask When set to 1 disables generation of a syn chronous SMI when a non implemented VGA CRT Controller Register is read...

Page 309: ...tes that the exception flag was set because the DC received a GLIU0 transaction request 32 TYPE_ERR Unexpected Type Error Reading a 1 indicates that an asynchronous error has occurred because the DC r...

Page 310: ...IU0 clock to the VGA module 00 Clock is not gated 01 Enable active hardware clock gating Hardware automatically determines when it is idle and internally disables the GLIU0 clock whenever possible 10...

Page 311: ...RSVD SPARE_MSR Bit Descriptions Bit Name Description 63 7 RSVD Reserved 6 DISABLE_ VFIFO_WM Disable Video FIFO Watermarks When set the video watermarks in DC_ARB_CFG 19 12 have no effect 5 0 RSVD Rese...

Page 312: ...6 6 3 1 DC Unlock DC_UNLOCK This register is provided to lock the most critical memory mapped DC registers to prevent unwanted modification write operations Read operations are always allowed DC Memo...

Page 313: ..._V_ACTIVE_TIMING DC Memory Offset 050h DC_V_BLANK_TIMING DC Memory Offset 054h DC_V_SYNC_TIMING DC Memory Offset 058h DC_DFIFO_DIAG DC Memory Offset 078h DC_CFIFO_DIAG DC Memory Offset 07Ch DC_VID_DS_...

Page 314: ...rite address enabled to Compressed Line Buffer CLB in diagnostic mode 1 Read address enabled to CLB in diagnostic mode 28 DIAG RAM Diagnostic Mode Effective immediately 0 Normal operation 1 RAM diagno...

Page 315: ...video lines to the display filter 1 Use DC_VID_DS_DELTA DC Memory Offset 080h 31 18 as a Digital Differential Analyzer DDA delta value to skip certain video lines to support downscaling in the displa...

Page 316: ...A HSYNC VSYNC blank and pixel outputs are routed through the back end of the DC pixel and sync pipeline and then to the I O pads 6 DECE Decompression Enable 0 Disable display refresh decompression 1 E...

Page 317: ...6 7 1 on page 335 for more information 24 DCEN Display Center 0 Normal active portion of scan line is qualified with DISPEN ball AE4 1 Border and active portions of scan line are qualified with DISPEN...

Page 318: ...ammed timing set 1 Update working timing registers on next active edge of vertical sync 5 RSVD Reserved 4 VDEN Video Data Enable Set this bit to 1 to allow transfer of video data to the VP 3 GDEN Grap...

Page 319: ...a must be in the DFIFO before a line buffer load is permitted This level is set in 256 byte increments 15 9 LPEN_END_ COUNT Low Priority End Counter When bit 0 LPEN_VSYNC is set this field indicates t...

Page 320: ...FO typically does not contain a full scan line of data it is neces sary to fetch additional data from memory during this process 0 LPEN_VSYNC Low Priority Enable at VSYNC When this bit is set the DC i...

Page 321: ...dresses are all located within the same 1 MB aligned region Thus a separate register DC_GLIU0_MEM_OFFSET DC Memory Offset 084h is used to set a 1 MB aligned base address GART address translation is no...

Page 322: ...28 RSVD Reserved 27 0 OFFSET Compressed Display Buffer Start Offset This value represents the byte offset of the starting location of the compressed display buffer The lower five bits should always b...

Page 323: ...art of the following frame or interlaced field DC Memory Offset 020h Type R W Reset Value xxxxxxxxh DC_VID_Y_ST_OFFSET Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...

Page 324: ...s can result in corrupted video data until the next reset of this counter 27 0 OFFSET Video U Buffer Start Offset This value represents the starting location for the Video U Buffer The lower three bit...

Page 325: ...NE_SIZE Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD VID_LINE_SIZE RSVD CB_LINE_SIZE RSVD FB_LINE_SIZE DC_LINE_SIZE Bit Descriptions Bit Name...

Page 326: ...four QWORDs i e bits 17 16 must be 00 15 0 FB_PITCH Frame Buffer Pitch This value represents the number of QWORDs between consecu tive scan lines of frame buffer data in memory DC Memory Offset 038h...

Page 327: ...NA and INTL_EN bits would be set DC Memory Offset 94h 12 11 11 and the filter coefficients would be programmed This example also presumes that the FLICK_EN bit is set DC Memory Offset 0D4h 24 1 Becaus...

Page 328: ...pixel granularity it is not limited to character 8 pixel granularity 15 12 RSVD Reserved These bits should be programmed to zero 11 0 H_ACTIVE Horizontal Active This field represents the total number...

Page 329: ...s the pixel clock count at which the horizontal blanking signal becomes inactive minus 1 Unlike previous versions of the DC this field can be programmed to any pixel granularity it is not limited to c...

Page 330: ...the total number of lines for a given frame scan minus 1 Note that the value is necessarily greater than the V_ACTIVE field bits 10 0 because it includes border lines and blanked lines If the display...

Page 331: ...ould be identical to V_TOTAL 15 11 RSVD Reserved These bits should be programmed to zero 10 0 V_BLANK_ START Vertical Blank Start This field represents the line at which the vertical blanking signal b...

Page 332: ...when graphics scaling is enabled The lower three bits of this register are ignored and presumed to be 111 Includ ing these bits the value in this field represents the total number of pixels in a line...

Page 333: ...necessary to display the right most pixels of the cursor only as the cursor moves close to the left edge of the display 10 0 CURSOR_X Cursor X This field represents the X coordinate of the pixel at wh...

Page 334: ...DC Line Count This value is the current scan line of the DC Engine The DC Engine which fetches the frame buffer data performs compression and de compression and overlays cursor data typically runs se...

Page 335: ...ESS Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD PAL_ADDR DC_PAL_ADDRESS Bit Descriptions Bit Name Description 31 9 RSVD Reserved 8 0 PAL_ADD...

Page 336: ...ir of write operations causes the FIFO write pointer to increment automatically After all write opera tions are performed a pair of reads of don t care data should be performed to load 64 bits of data...

Page 337: ...fter each write the FIFO write pointer automatically increments After all write operations are performed the CFRW bit should be set high to enable read addresses to the FIFO and a pair of reads of don...

Page 338: ...nded to work for ratios from 1 down to 1 2 The equation above clips the value to the 14 bits of accuracy in the hardware The equation could be modified to allow for higher bits in the future by changi...

Page 339: ...0 0 DV_RAM_AD DV RAM Address This value is used to allow direct software access to the Dirty Valid DV RAM The address must be written in this location before reading or writing the DV RAM Access Regis...

Page 340: ...sponse to memory activity When this bit is cleared the DV RAM behaves normally 0 CLEAR_DV_RAM Clear DV RAM Writing a 1 to this bit causes the contents of the DV RAM to be cleared i e every entry is se...

Page 341: ...field The default value of this field 4000h represents 1 1 scaling This value must be pro grammed when the vertical filter is disabled The value in this field must not exceed 8000h which represents a...

Page 342: ...ery other line of the original unscaled frame buffer image The flicker filter and scaler filter should both be disabled if this bit is set 27 RSVD Reserved 26 16 LINE_COUNT Interrupt Line Count This v...

Page 343: ...t 098h and 09Ch When this bit is cleared the vertical filter coefficients are accessed instead 9 8 RSVD Reserved 7 0 FILT_ADDR Filter Coefficient Address This indicates which filter location is access...

Page 344: ...tion 31 20 RSVD Reserved Set to 0 This field is used only when reading or writing the Line Buffer Regis ter 19 10 TAP5 Tap 5 Coefficient This coefficient is used for the fifth tap rightmost in the hor...

Page 345: ...for VBI data DC Memory Offset 0A4h Type R W Reset Value xxxxxxxxh DC_VBI_EVEN_CTL Bit Descriptions Continued Bit Name Description DC_VBI_ODD_CTL Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18...

Page 346: ...of 126 or less 24 2 LN_EN_ODD Odd Line Enable Each of the bits in this field corresponds to a line 24 2 of VBI data Setting a bit in this field to 1 enables the corresponding line of VBI data in the...

Page 347: ...ne to the start of the next DC Memory Offset 0B8h Type R W Reset Value 00000000h DC_CLR_KEY Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD CLR_...

Page 348: ...paring the values This allows the value of some bits to be ignored when performing the match DC Memory Offset 0C0h Type R W Reset Value 00000000h DC_CLR_KEY_X Register Map 31 30 29 28 27 26 25 24 23 2...

Page 349: ...s IRQ If set to 1 this field indicates that while GenLock was enabled GenLock timeout was enabled and the DC reached the end of a frame and detected VIP_VIDEO_OK DC Memory Offset D4h 23 inactive As a...

Page 350: ...of the alpha value when the flicker filter is enabled FLICK_EN bit 24 1 If the flicker filter is enabled and this bit is cleared the alpha value of the center pixel is passed through the flicker filt...

Page 351: ...GenLock is enabled If GenLock timeout is also enabled GENLK_TO_EN bit 19 1 internal recognition of VSYNC occurs immediately upon timeout without allowing this skew time to elapse after the timeout is...

Page 352: ...uffer Start Offset This value represents the starting location for Video U Buffer for even fields when interlacing is enabled DC Memory Offset 094h 11 1 and YUV 4 2 0 mode is selected DC Memory Offset...

Page 353: ...7 RSVD Reserved These bits should be programmed to zero 26 16 V_TOTAL Vertical Total This field represents the total number of lines for a given frame scan minus 1 Note that the value is necessarily g...

Page 354: ...D Vertical Blank End This field represents the line at which the vertical blanking signal becomes inactive minus 1 If the display is interlaced no border is supported so this value should be identical...

Page 355: ...tte If set to 1 VGA palette write operations are NOT written to the palette RAMs Palette writes behave normally except that the data is discarded DC Memory Offset 104h Type RO Reset Value 00000000h VG...

Page 356: ...This bit is used to replace memory address bit A0 as the LSB when bit 1 of the Miscellaneous register Index 06h 1 in the VGA Graphics Controller is set to 1 4 RSVD Reserved 3 2 CLK_SEL Clock Select Se...

Page 357: ...emented Display Sense 3 0 RSVD Reserved Read Address 3BAh or 3DAh Write Address Type R W Reset Value 01h VGA Input Status Register 1 Bit Descriptions Bit Name Description 7 4 RSVD Reserved 3 VSYNC Ver...

Page 358: ...01h R W VGA Clocking Mode 02h Page 359 02h R W VGA Map Mask 00h Page 359 03h R W VGA Character Map Select xxh Page 360 04h R W VGA Memory Mode 02h Page 360 Index Address 3C4h Type R W Reset Value 0xh...

Page 359: ...is intended to allow the CPU full access to the memory bandwidth This bit must be 0 for the display image to be visible 4 RSVD Not Supported Shift4 3 DCLK_DIV2 Dot Clock Divide By 2 When set to 1 the...

Page 360: ...e Code Font Table Location in Map 2 Code Font Table Location in Map 2 0 8 KB Block 0 4 8 KB Block 1 1 8 KB Block 2 5 8 KB Block 3 2 8 KB Block 4 6 8 KB Block 5 3 8 KB Block 6 7 8 KB Block 7 Index 04h...

Page 361: ...CRTC Register Settings VGA Mode Index 00 01 02 03 04 05 06 07 0D 0E 0F 10 11 12 13 0 2D 2D 5F 5F 2D 2D 5F 5F 2D 5F 5F 5F 5F 5F 5F 1 27 27 4F 4F 27 27 4F 4F 27 4F 4F 4F 4F 4F 4F 2 28 28 50 50 28 28 50...

Page 362: ...rsor Start 00h Page 366 0Bh R W Cursor End 00h Page 367 0Ch R W Start Address High 00h Page 367 0Dh R W Start Address Low 00h Page 367 0Eh R W Cursor Location High 00h Page 367 0Fh R W Cursor Location...

Page 363: ...l This value specifies the number of character clocks per horizontal scan line minus 5 It determines the horizontal line rate period Index 01h Type R W Reset Value 00h Horizontal Display Enable End Re...

Page 364: ...ister Bits 4 0 This 6 bit value is a compare target for the character count where the horizontal blank signal ends Bit 5 of this value is in the Hori zontal Sync End register Index 05h 7 Note that not...

Page 365: ...c Start Bit 9 See V_SYNC_ST 7 0 bit description Index 10h 7 0 V_SYNC_ST8 is located at bit 2 6 V_DISP_EN_END9 Vertical Display Enable End Bit 9 See V_DISP_END 7 0 bit description Index 12h 7 0 V_DISP_...

Page 366: ...d to 0 the row scan counter increments on every scan line This bit is used to make 200 line text modes occupy 400 physical scan lines on the screen 6 LN_CMP9 Line Compare Register Bit 9 See LINE_COMP...

Page 367: ...Address Register Bits 15 8 Together with the register ST_ADDR_LOW Index 0Dh 7 0 this value specifies the frame buffer address used at the beginning of a screen refresh It represents the upper left cor...

Page 368: ...7 0 VERT_SYNC_ST Vertical Sync Start Register Bits 7 0 This value specifies the scan line number where the vertical sync signal will go active This is a 10 bit value Bits 9 and 8 are in the Overflow r...

Page 369: ...escriptions Bits Name Description 7 0 OFST Offset This field specifies the logical line width of the screen This value multiplied by two or four depending on the CRTC clocking mode is added to the sta...

Page 370: ...When set to 1 this bit enables the horizontal and vertical sync signals When 0 this bit holds both sync flip flops reset 6 BTMD Byte Mode If the DWORD mode bit DW Index 14h 6 is 0 then this bit config...

Page 371: ...ress counter bit 14 13 or 12 appears on MA14 See Table 6 55 on page 371 for more information 0 SL_A13 Select A13 This bit determines which CRTC signal appears on the MA13 address bit sent to the frame...

Page 372: ...s specified in the Attribute Mode Control register Index 10h Line Compare is a 10 bit value Bit 8 is located in the Overflow register Index 07h 4 and bit 9 is in the Maximum Scan Line register Index 0...

Page 373: ...alue This read only value indicates the value of Attribute Index regis ter bits 5 0 Index 3C0h Table 6 56 Graphics Controller Registers Summary Index Type Register Reset Value Reference R W VGA Graphi...

Page 374: ...90 for more information Data Address 3CFh Type R W Reset Value xxh VGA Graphics Controller Data Register Bit Descriptions Bit Name Description 7 4 RSVD Reserved 3 0 DATA Data Index 00h Type R W Reset...

Page 375: ...M_MP2 Color Compare Map 2 1 CO_CM_MP1 Color Compare Map 1 0 CO_CM_MP0 Color Compare Map 0 Index 03h Type R W Reset Value xxh VGA Data Rotate Bit Descriptions Bit Descriptions Bit Name Description 7 5...

Page 376: ...e serializer configuration 5 SH_R_MD Shift Register Mode When set to a 1 this bit configures the video serializers for BIOS modes 4 and 5 When this bit is 0 the serializers are taken in parallel i e c...

Page 377: ...is replicated for each map and combined with the data latches and written to memory The VGA Bit Mask Register Index 08h is used to protect individual bits in each map from being updated 11 Write Mode...

Page 378: ...ng in a color compare operation 0 CM_PR0 Compare Map 0 This bit enables bit 1 or excludes bit 0 map 0 from participating in a color compare operation Index 08h Type R W Reset Value xxh VGA Bit Mask Re...

Page 379: ...iptions Bit Name Description 7 6 RSVD Reserved 5 INT_PAL_AD Internal Palette Address This bit determines whether the EGA palette is addressed by the video pixel stream bit 1 or by the Attribute Contro...

Page 380: ...is used to cause a character to blink bit 7 1 or not bit 7 0 When this bit is 0 attribute bit 7 is used as a background intensity bit 2 EN_LGC Enable Line Graphics Codes When this bit is 0 the 9th Do...

Page 381: ...EGA palette 1 EN_CO_PN1 Enable Color Plane 1 This bit enables color plane 1 It is ANDed with it corresponding pixel bit and the resulting 4 bit value is used as the address into the EGA palette 0 EN_C...

Page 382: ...e original IBM video DAC behavior for write operations is 1 CPU initiates a palette write by writing INDEX to I O address 3C8h 2 CPU writes red green blue color values to temporary DAC registers at I...

Page 383: ...tions Bit Name Description 7 2 RSVD Reserved 1 0 DAC_ST DAC State This register returns the DAC state for save restore operations If the last palette address write was to 3C7h read mode both bits are...

Page 384: ...0 PAL_MSK Palette Mask These bits enable their respective color bits between the final VGA 8 bit pixel output and the DAC palette The bits are ANDed with the incoming VGA pixel value and the result u...

Page 385: ...cellaneous Output register RAM Enable bit is 0 all VGA memory space is disabled Or if the Memory Map bits of the Graphics Miscellaneous register are set the same as these bits then the VGA frame buffe...

Page 386: ...thin the 8 MB of graphics memory CRTC Index 048h Type R W Reset Value 00h ReadMemoryAperture Register Bit Descriptions Bit Name Description 7 0 RD_BASE ReadBase Offset added to the graphics memory bas...

Page 387: ...VGALatchSavRes This register is used to save restore the 32 bit VGA data latch When the CRTC index register is written an internal byte counter is cleared to 0 Four successive reads or writes to the C...

Page 388: ...3 on page 389 General Features Hardware video acceleration Graphics video overlay and blending Progressive video from the Display Controller module Dot Clocks up to 350 MHz Hardware Video Acceleration...

Page 389: ...d Gamma RAM Delay Video Output Port Output Format MUX Output Devices VIP TV Encoder CRT DAC 3x8 bit TFT Panel AMD Geode Companion Video Processor Panel Interface Dither Engine TFT Timing Generator Fla...

Page 390: ...zontal and vertical scaling hard ware and an optional YUV to RGB color space converter This motion video acceleration circuitry is integrated into the VP to improve video playback By off loading these...

Page 391: ...ry Offset 000h 3 2 00 Y0 Y1 Y2 Y3 01 Y3 Y2 Y1 Y0 10 Y1 Y0 Y3 Y2 11 Y1 Y2 Y3 Y0 Note The above formats describe Y data U and V data have the same format where U and V replace the Y in this sample RGB V...

Page 392: ...rted in 4 2 2 YUV video format only not 4 2 0 YUV or 5 6 5 RGB The downscaler supports up to 29 downscaler factors There are two types of factors Type A is 1 m 1 One pixel is retained and m pixels are...

Page 393: ...by the DDA algorithm The location of each intermediate point is one of eight phases between the original pixels see Figure 6 26 6 7 4 Color Space Converter After scaling and filtering have been perfo...

Page 394: ...data in RGB format and video data in RGB format YUV to RGB conversion are blended YUV blending eliminates video de interlacing and YUV to RGB conversion of video data For YUV blending the graphic dat...

Page 395: ...Palette Alpha Color Registers and Cursor Color Values Cursor_Color_Key VID_CLR_KEY Location RAM CUR_COLOR_MASK Compare Compare VID_CLR_MASK 1 0 0 1 0 1 YUV to RGB CSC HSV to RGB CSC RGB to HSV Satura...

Page 396: ...graphics value Pixel inside the video window Use selected cursor color for pixel Use graphics value for this pixel Pixel inside Alpha window Video pixel Blend graphic values and video values using th...

Page 397: ..._CK Note 1 Note 1 VG_CK is bit 20 in the Display Configuration register VP Memory Offset 0008h Windows Configuration Note 2 Note 2 GFX_INS_VIDEO is bit 8 in the Video De interlacing and Alpha Control...

Page 398: ...encoder The VOP must be BT 656 BT 601 compliant since its output may go directly or indirectly to a display 6 7 6 2 Supported Features VIP 2 0 level I and II with VIP 1 1 compatibility mode BT 656 mo...

Page 399: ...re time HBLANK is a function of horizontal pixel position while VBLANK is a function of the vertical line number and the horizontal pixel position Figures 6 30 to 6 34 show the for mation of these sig...

Page 400: ...263 525 Figure 6 33 HBLANK and VBLANK for Lines 1 18 264 281 Figure 6 34 HBLANK and VBLANK for Lines 19 282 Pixel Position Line Number HBLANK VBLANK 720 721 858 001 244 245 Pixel Position Line Number...

Page 401: ...U V 4 2 2 Sampled data Y1 Y1 U1 U1 V1 V1 Y2 Y2 Y3 Y3 U3 U3 V3 V3 etc Mode 1 4 2 2 Interspersed In this mode adjacent pairs of U V sample data are aver aged with the U V samples coming from the same ad...

Page 402: ...and correct single bit errors The bits are defined as follows P3 V H T P2 F H T P1 F V T P0 F V H Using the above formulas the bit values are listed in Table 6 63 VIP 1 1 Compatible Mode VIP 1 1 comp...

Page 403: ...d source REPEAT 1 repeat field in 3 2 pull down 0 not a repeat field tied to 0 EXT_FLAG 1 extra flag byte follows this EAV 0 no extra flag byte this flag is always 0 Figure 6 35 BT 656 8 16 Bit Line D...

Page 404: ...the different modes In BT 656 mode typically the TASK bit in the EAV SAV header is fixed at 1 In this case there is no indication of VBI data If the VBI bit in the VOP Configuration register is set to...

Page 405: ...Specification TFT panel support provided by use of one connector allows a pass through mode for the digital pixel input 9 12 18 and 24 bit 1 pixel per clock TFT support 9 9 or 12 12 bit and 24 bit 2 p...

Page 406: ...er clock is supported for all resolutions Other resolutions below 640x480 are also supported Table 6 66 shows the mapping of the data in the supported modes For TFT panel support the output from the d...

Page 407: ...over an 8x8 pixel area An 8x8 pixel area supports 64 different dithering patterns This means that the 8 bit input intensity for a given pixel pri mary color component can be reduced down to its two m...

Page 408: ...of the input intensity value for each color component The order in which 1s are added to the dithering pattern as the value of these two bits increases from 0 to 3 is the same as the order for the 6...

Page 409: ...00 111 101 110 000 001 010 011 100 111 101 110 5 6 7 3 4 6 5 4 7 3 1 2 1 2 5 6 7 3 4 6 5 4 7 3 1 2 1 2 5 6 6 5 4 7 3 1 2 1 2 5 6 6 5 4 7 3 7 3 4 7 3 4 X Count 3 0 Y Count 3 0 3 3 3 3 000 001 010 011 1...

Page 410: ...nfiguration for a fixed on screen image Addressing the Dithering Memories The least significant four bits of each color component intensity value are used to select a 4x4 dithering pattern In other wo...

Page 411: ...cess to debug signals The DBG signals are driven on the specified pins outside the VP module listed here for information only 7 VOP Normal function Table 6 68 Display RGB Modes Pin CRT 1 TFT ONLINE 2...

Page 412: ...D SMI MSR GLD_MSR_SMI 00000000_00000000h Page 417 48002003h R W GLD Error MSR GLD_MSR_ERROR 00000000_00000000h Page 417 48002004h R W GLD Power Management MSR GLD_MSR_PM 00000000_00000555h Page 418 48...

Page 413: ...000h Page 439 0D8h R W Alpha Window 1 Control A1T 00000000_00000000h Page 440 0E0h R W Alpha Window 2 X Position A2X 00000000_00000000h Page 441 0E8h R W Alpha Window 2 Y Position A2Y 00000000_0000000...

Page 414: ...rol and Address DCA 00000000_00000000h Page 457 450h R W Dither Memory Data DMD 00000000_00000000h Page 458 458h R W Panel CRC Signature CRC 00000000_00000000h Page 458 460h Reserved 468h RO 32 Bit Pa...

Page 415: ...MSR_CONFIG Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5...

Page 416: ...clock speed DIV reference clock 7 6 FMTBO Format Byte Order The lower 24 bits of the DRGB output bus byte order can be modi fied for any required interface These bits along with bit 14 are used to out...

Page 417: ...9 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD E 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD EM GLD_MSR_ERROR Bit Descriptions Bit Name Descri...

Page 418: ...ite no function 23 11 RSVD Reserved 10 PMD5 VOP 2x Dot Clock Power Mode 0 Disable clock gating Clocks are always ON 1 Enable active hardware clock gating 9 RSVD Reserved 8 PMD4 VP Video Dot Clock Powe...

Page 419: ...y dither mode 1 New dither mode 29 28 SM Sim Mode This field is used to put the VP in modes to aid verification 00 Normal operation 01 Graphics input bypasses VP and goes directly to FP 10 Reserved 11...

Page 420: ..._HSYNC DF_DRGB 23 0 MSR_PADSEL Bit Descriptions Bit Name Description 63 40 RSVD Reserved 39 VOPCINV Invert VOP Clock This is used to invert the VOP output clock This may be used to meet system timing...

Page 421: ...this bit increases line size from BIT_8_LINE_SIZE VID_LIN_SIZ bits 15 8 DWORDs by adding 512 DWORDs 0 Disable 1 Enable 25 SP Spare Bit is R W but has no function 24 INIT_RD_ LN_SIZE Increase Initial...

Page 422: ...Y0 10 Y1 Y0 Y3 Y2 11 Y1 Y2 Y3 Y0 If GV_SEL is set to 1 and EN_420 is set to 0 5 6 5 00 P1L P1M P2L P2M 01 P2M P2L P1M P1L 10 P1M P1L P2M P2L 11 P1M P2L P2M P1L Both RGB 5 6 5 and YUV 4 2 2 contain two...

Page 423: ...that are sent to the CRT This field should be programmed to 100 i e baseline sync is not moved as the baseline Via this register the sync can be moved forward later or backward earlier relative to th...

Page 424: ...1 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD VID_X_END RSVD VID_X_START VX Bit Descriptions Bit Name Description 63 28 R...

Page 425: ...is programmed relative to CRT Vertical sync input not the physical screen posi tion This value is calculated according to the following formula Value Desired screen position V_TOTAL V_SYNC_END 1 Note...

Page 426: ...icient usage 0 Use common 256 vert horz coefficient table 1 Use separate 128 vert horz coefficient tables When using separate tables the vertical coefficient should be placed in the lower half of the...

Page 427: ...ular shaped overlays of graphics onto video or video onto graphics within a scaled video window VP Memory Offset 030h Type R W Reset Value 00000000_00000000h VCK Bit Descriptions Continued Bit Name De...

Page 428: ...al data block VP Memory Offset 040h Type R W Reset Value 00000000_00xxxxxxh PDR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30...

Page 429: ...Bit Name Description 63 10 RSVD RO Reserved Read Only Reads back as 0 9 EN Enable Enable Saturation Scaling If this bit is cleared saturation conversion does not occur If it is set saturation convers...

Page 430: ...Spare Read write no function 11 APWRDN Analog Interface Power Down Enables power down of the analog section of the inter nal CRT DAC 0 Normal 1 Power down 10 DACPWRDN DAC Power Down Enables power dow...

Page 431: ...Load this value before each video frame Works with verti cal scaling in case a sub line offset is required prior to displaying video Pad 4 LSBs with 0 when loading 19 0 VID_Y_SCL Video Y Scale Factor...

Page 432: ...nded set to 10000h Will be greater than 1000h when down scaling Will be less than 10000h when upscaling VP Memory Offset 078h Type R W Reset Value 00000000_00000000h VDC Register Map 63 62 61 60 59 58...

Page 433: ...at the next falling edge of VSYNC 1 Enable If SIGNEN bit 0 is set to 1 the signature register captures data continuously across multiple frames 0 SIGEN Signature Enable 0 Disable The SIGVAL bits 31 8...

Page 434: ...s This field is used for test purposes only See VP Memory Offset 088h for more information VP Memory Offset 098h Type R W Reset Value 00000000_00000400h VDE Register Map 63 62 61 60 59 58 57 56 55 54...

Page 435: ...input bus 31 24 11 DRGB 31 24 contain contents of graphics input bus 31 24 when NOT inside any alpha window inside any alpha window DRGB 31 24 contains actual video alpha value 13 GV_SEL Graphics Vide...

Page 436: ...VD RO Reserved Read Only Reads back as 0 4 SP Spare Read write no function 3 RSVD RO Reserved Read Only Reads back as 0 2 0 SP Spares Read write no function VP Memory Offset 0A0h Type R W Reset Value...

Page 437: ...be forced to match Example A mask of FFFFFFh causes all 24 bits to be compared single color match A mask of 000000h causes none of the 24 bits to be compared all colors match VP Memory Offset 0B0h Ty...

Page 438: ...0C0h Type R W Reset Value 00000000_00000000h A1X Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 1...

Page 439: ...is calculated according to the following formula Value Desired screen position V_TOTAL V_SYNC_END 2 Note 1 15 11 RSVD RO Reserved Read Only Reads back as 0 10 0 ALPHA1_Y_ START Alpha Window 1 Y Start...

Page 440: ...he alpha window graphics are displayed See Figure 6 31 on page 438 1 Enable If this bit is enabled and the alpha window is enabled then where there is a color key match within the alpha window the col...

Page 441: ...aches either the maxi mum or the minimum alpha value 255 or 0 it keeps that value i e it is not incremented decremented until it is reloaded via LOAD_ALPHA bit 17 7 0 ALPHA1_MUL Alpha Window 1 Value S...

Page 442: ...is calculated according to the following formula Value desired screen position V_TOTAL V_SYNC_END 2 Note 1 15 11 RSVD RO Reserved Read Only Reads back as 0 10 0 ALPHA2_Y_ START Alpha Window 2 Y Start...

Page 443: ...ies the color to be displayed inside the alpha window when there is a color key match in the alpha window This color is only displayed if the alpha window is enabled and ALPHA2_COLOR_REG_EN bit 24 is...

Page 444: ...ntinued Bit Name Description A3X Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14...

Page 445: ...alue is calculated according to the following formula Value Desired screen position V_TOTAL V_SYNC_END 2 Note 1 15 11 RSVD RO Reserved Read Only Reads back as 0 10 0 ALPHA3_Y_ START Alpha Window 3 Y S...

Page 446: ...ies the color to be displayed inside the alpha window when there is a color key match in the alpha window This color is only displayed if the alpha window is enabled and the ALPHA3_COLOR_REG_EN bit 24...

Page 447: ...til it is reloaded via LOAD_ALPHA bit 17 7 0 ALPHA3_MUL Alpha Window 3 Value Specifies the alpha value to be used for this window VP Memory Offset 120h Type R W Reset Value 00000000_001B0017h A3T Bit...

Page 448: ...iption 63 24 RSVD Reserved Reads back as 0 23 16 AW3 Alpha Value for Window 3 15 8 AW2 Alpha Value for Window 2 7 0 AW1 Alpha Value for Window 1 VP Memory Offset 130h Type R W Reset Value 00000000_000...

Page 449: ...ording to the following formula Value Desired screen position V_TOTAL V_SYNC_END 1 Note 1 Note 1 V_TOTAL and V_SYNC_END are the values written in the Display Controller module registers VP Memory Offs...

Page 450: ...ND 1 Note 1 Note 1 V_TOTAL and V_SYNC_END are values programmed in the Display Controller module registers The value of V_TOTAL V_SYNC_END is sometimes referred to as vertical back porch VP Memory Off...

Page 451: ...r tap 0 of filter VP Memory Offset 400h Type R W Reset Value 00000000_00000000h PT1 Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31...

Page 452: ...lay the input HSYNC before it is output onto the LP HSYNC Default 1 Delay the input HSYNC before it is output onto the LP HSYNC 26 8 RSVD Reserved R W no function 7 5 HSYNC_DELAY Horizontal Sync Delay...

Page 453: ...not used 29 LPOL Display Timing Strobe Polarity Select Selects the polarity of the LDE MOD pin This can be used for panels that require an active low timing LDE interface signal 0 LDE MOD signal is a...

Page 454: ...38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SP PWR_SEQ_SEL PNL_PWR_SIM D P PUB2 PUB1 PUB0 PD2 PD1 PD0 HDEL VDEL SINV SP PANEL_PWR_UP...

Page 455: ...abled 0 32 ms 1 128 ms 20 PD2 Panel Power Down Phase Bit 2 Selects the amount of time from when panel DIS PEN is disabled to PD1 0 32 ms 1 128 ms 19 PD1 Panel Power Down Phase Bit 1 Selects the amount...

Page 456: ...ve image of the original image It acts as though the incoming data stream were logically inverted 1 becomes 0 and 0 becomes 1 0 Normal display mode 1 Negative image display mode 9 7 RSVD RO Reserved R...

Page 457: ...29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD A U ADDR DCA Bit Descriptions Bit Name Description 63 8 RSVD RO Reserved Read Only Reads back as 0 7 A Dither RAM...

Page 458: ...24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD FRCT SIGVAL SIGFR SIGEN CRC Bit Descriptions Bit Name Description 63 9 RSVD RO Reserved Read Only Reads back as 0 8 3 FRCT RO Fra...

Page 459: ...8 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPARE VBI_SWAP RSVD RGB_MODE VALID_SIG INV_DE_POL INV_VS_PO...

Page 460: ...he TASK bit in the EAV SAV is defined such that 0 is VBI data and 1 is active video data Therefore this VBI bit has no effect in VIP 1 1 mode In VIP 2 0 mode the TASK bit determines the value of the T...

Page 461: ...ons also used in BT 656 0 Do not use extended codes 1 Use extended codes Note Selecting BT 656 mode in bits 1 0 automatically uses the extended codes 2 VIP_LEVEL VIP 2 0 Level Selection 0 VIP 2 0 Leve...

Page 462: ...en field indication vip_int output for interrupt generation on frame field line boundaries 6 9 1 1 Performance Metrics System goals 150 MHz video interface 400 MHz GLIU interface Adequate GLIU bandwid...

Page 463: ...Input Control QWORD 64 bits take req reg write reg read Mapped GLIU Interface Clock Control Input Output Control Dual Port input ctl output ctl 16 bits Capture RAM VIP INT SYNC_TO_PIN SYNC_TO_VG 256x6...

Page 464: ...times to system memory Programmable thresh old level flags are available to monitor data levels This should be helpful in debugging Memory BIST is imple mented and can be invoked from the JTAG logic f...

Page 465: ...8 bit message data and 8 bit streaming data allowing the AMD Geode CS5536 companion device connected to the VIP to load data directly into the AMD Geode LX proces sor s system memory The Message Passi...

Page 466: ...ORD is shown in Table 6 73 A sample SAV EAV line is shown in Figure 6 40 on page 467 A full frame is shown in Figure 6 41 on page 468 The status WORD provides the raster reference information VIP 1 1...

Page 467: ...te The VIP ignores fields lines with the repeat flag set This reducers the amount of data being transferred to system memory reducing overall bandwidth requirements Additional flag bytes are also supp...

Page 468: ...for VIP 1 1 mode there must be a minimum of one SAV EAV scan line during vertical blanking in order for the VBlank flag to transition from 0 1 0 An End of Frame event is detected the same in VIP 1 1...

Page 469: ...her explanation There is no restriction on the code in the data section of the packet codes 00 and FF are allowed The SAV EAV packet preamble detection circuitry is disabled during the reception of th...

Page 470: ...n external device to pass raw data to the processor system memory see Figure 6 44 When in Data Streaming mode the VID9 data pin is redefined as a DATA_VALID control input VID8 is the START_MSG indicat...

Page 471: ...fault value requires that the HSYNC and VSYNC leading edges occur simultaneously for odd field detection see Figure 6 46 on page 472 The horizontal and vertical input timings of the input video frame...

Page 472: ...arity 0 ACTIVE HIGH HSYNC VSYNC HSYNC Polarity 1 VSYNC Polarity 1 VSYNC for odd field for even field even field odd field line 1 HSYNC VSYNC odd_field_detect_start field_detect_duration VSYNC for odd...

Page 473: ...erlacing Figure 6 49 on page 474 illustrates the positioning of the YCbCr samples for the 4 2 2 and 4 2 0 formats when 1 Receiving a progressive scan frame 2 Receiving interlaced odd and even fields f...

Page 474: ...UV 4 2 2 YUV 4 2 0 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 1 2 3 4 5 6 1 2 4 3 1 1 2 3 2 3 4 YUV 4 2 2 YUV 4 2 0 1 2 3 4 5 6 1 2 3 4 5 6 5 6 7 Progressive scan Discard even line UV values Interlaced Weave Disca...

Page 475: ...eo 1 1 0 VIP_TASK_A_VID_EVEN_BASE VIP_TASK_A_U_OFFSET VIP_TASK_A_V_OFFSET Task A Odd Field VBI 1 0 1 VIP_TASK_A_VBI_ODD_BASE N A Task A Even Field VBI 1 1 1 VIP_TASK_A_VBI_EVEN_BASE N A Task B Odd Fie...

Page 476: ...nt Ancillary Packet Count bit in the VIP Status register VIP Memory Offset 08h 18 Ancillary data packets include a checksum After packet reception the internally generated checksum is compared to the...

Page 477: ...ne 2 start line 3 start line is 00 filled if not QWORD aligned Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y 00 00 00 00 Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y 00 00 00 00 Cb Y Cr Y vid_base vid_...

Page 478: ...alues vid_base vid_base vid_base Similar buffers can exist for Task A even video Note Line lengths which are not divisible by 8 will result in an odd number of U and V data for each line When this occ...

Page 479: ...ata data data data data data data data data data data data data data 00 CS data data packet 3 start packet is 00 filled to QWORD aligned address anc_message_base 00 CS data data packet is 00 filled if...

Page 480: ...ther an odd or even field was received Software can manage these field frame buffers so that the Display Controller always accesses fully assem bled frame data 6 9 12 VIP Interrupts Software applicati...

Page 481: ...video mode this indicates that the number of outstanding ancillary packets has reached the threshold count programmed in VIP Memory Offset 60h End of Vertical Blanking Indicates that a falling edge of...

Page 482: ...onfiguration Control Registers Summary VIP Memory Offset Type Register Name Reset Value Reference 00h R W VIP Control Register 1 VIP_CTL_REG1 42000001h Page 488 04h R W VIP Control Register 2 VIP_CTL_...

Page 483: ...ng Data Streaming Buffer 2 Base Address VIP_ANC_MSG_2_BASE 00000000h Page 505 60h R W VIP Ancillary Data Message Passing Data Streaming Buffer Size VIP_ANC_MSG_SIZE 00000000h Page 505 64h Reserved 68h...

Page 484: ...D Identifies device 03C4h 7 0 REV_ID Revision ID Identifies device revision See AMD Geode LX Processors Specification Update document for value MSR Address 54002001h Type R W Reset Value 000000000_ 00...

Page 485: ...r Bit 24 VIP clock input error Bit 23 Ancillary packet checksum error Bit 22 Message buffer full or ancillary threshold packet count reached Bit 21 End of vertical blanking Bit 20 Start of vertical bl...

Page 486: ...6 5 4 3 2 1 0 RSVD E1 E0 RSVD EM1 EM0 GLD_MSR_ERROR Bit Descriptions Bit Name Description 63 18 RSVD Reserved 17 E1 Error Status 1 Writing a 1 to this bit clears the status 0 VIP error not pending 1 V...

Page 487: ...lock Power Mode 0 Disable clock gating VIP clock is always ON 1 Enable active hardware clock gating The VIP input clock to the video input block is enabled when this bit is 0 When this bit is 1 the VI...

Page 488: ...for flushing the 64 deep planar mode or 192 deep linear mode FIFO s This value determines how full the ancillary FIFO is before VIP starts writing QWORDs to system memory If the FIFO has greater than...

Page 489: ...a and save in system memory 16 DD Disable Decimation Disables decimation of even lines of Cr Cb data for 4 2 2 4 2 0 translation 0 Normal operation Even lines of Cr Cb data do NOT get saved in Cr Cb b...

Page 490: ...A_ERR_EN R_EN SWC ANC10 ANCPEN LPB FF_R W PAGE_CNT ANC_FF_THRESH RSVD VID_FF_THRESH SYNC_TO_PIN FIELD_TO_DC SYNC_TO_DC VIP_CTL_REG2 Bit Descriptions Bit Name Description 31 FI Field Invert When set t...

Page 491: ...e secondary priority is used during a write request If the FIFO WORD count exceeds this value the secondary priority ID is used An INT or SMI can also be generated if this threshold is exceeded Thresh...

Page 492: ...1 to this bit causes the ancillary packet count to be decremented by 1 17 SO WO Sync Out Write Only Writing a 1 to this bit causes a 0 1 0 transition on the VIP_VSYNC pin 32 GLIU clocks 16 BRNU RO Ba...

Page 493: ...y 0 VIP FIFO is NOT empty 1 VIP FIFO is empty 7 5 RSVD Reserved 4 F RO Field Indication Read Only Indicates current status of field being received 0 Odd field is being received 1 Even field is being r...

Page 494: ...18 Start of odd field Bit 17 Current line VIP Line Target see Current Target Line register Bit 16 Not used 0 15 0 INT_MASK VIP Interrupt Masks 0 Enable unmask the INT 1 Disabled mask the INT Bit 14 Wh...

Page 495: ...IP_MAX_ADDR Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAX_ADDR RSVD VIP_MAX_ADDR Bit Descriptions Bit Name Description 31 3 MAX_ADDR Max Addres...

Page 496: ...r is not updated at this point When the first data of the next field is captured the pending values of all base registers are written to the appropriate base registers and the Base Register Not Update...

Page 497: ...ated at this point When the first data of the next field is captured the pending values of all base registers are written to the appropriate base registers and the Base Register Not Updated bit is cle...

Page 498: ...start of the line address to get the address of the next line where captured video data will be stored This value must be an integral number of QWORDs This value needs to be 32 byte aligned Bits 4 0 a...

Page 499: ...where high GLIU latencies cause continuous FIFO overflows when a line overrun error occurs or if the line offset gets corrupted which could result in an image shift This bit remains a 1 during the FIF...

Page 500: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TASK_B_VID_EVEN_BASE_HORIZ_END 601 type modes VIP_TASK_B_VID_EVEN_BASE_HORIZ_END Bit Descriptions Bit Name Descriptio...

Page 501: ...base registers and the Base Register Not Updated bit is cleared 11 0 HORIZ_START Horizontal Start This register is redefined in BT 601 mode In BT 601 type input modes timing is derived from the extern...

Page 502: ...for odd fields is stored Changes to this register take effect at the beginning of the next field This value must be 32 byte aligned Bits 4 0 are required to be 00000 Note This register is double buff...

Page 503: ...ating non interlaced input The VERT_START VIP Memory Offset 6Ch value is used for non interlaced modes See Figure 6 48 BT 601 Mode Vertical Timing on page 473 for additional detail VIP Memory Offset 5...

Page 504: ...s register must be 32 byte aligned Bits 4 0 are required to be 00000 Note This register in NOT double buffered and should be initialized before start of video capture VIP Memory Offset 58h Type R W Re...

Page 505: ...t be 32 byte aligned Bits 4 0 are required to be 00000 Note This register is NOT double buffered VIP Memory Offset 60h Type R W Reset Value 00000000h VIP_ANC_MSG_SIZE Register Map 31 30 29 28 27 26 25...

Page 506: ...ype R W Reset Value 00000000h VIP_VERT_START_STOP Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD VERT_END RSVD VERT_START VIP_VERT_START_STOP B...

Page 507: ...ddress for which a FIFO read or write occurs The data is writ ten read via the FIFO Data register VIP Memory Offset 74h Note that the 256x64 bit FIFO is mapped as a 512x32 bit memory VIP Memory Offset...

Page 508: ...in an input field interlaced video or frame non interlaced video If the number of video clocks between rising edges of VBLANK is less then this number or greater then VERTICAL_COUNT VERTICAL_WINDOW a...

Page 509: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TASK_A_V_EVEN_OFFSET Program to 00000 VIP_TASK_A_V_EVEN_OFFSET Bit Descriptions Bit Name Description 31 0 TASK_A_V_ EVEN_OFFSET Task A V Even Offset This register...

Page 510: ...Programmable Hidden AES key Can use interrupts SMIs or be polled for completion status Memory mapped register interface True Random Number Generator TRNG Read via MSR Note For security purposes the E...

Page 511: ...contexts allows the software to queue a sec ond encryption decryption request while the first operation is completing The Security Block only contains a single AES hardware block so the second reques...

Page 512: ...t programmed by software and then the EEPROM Command register SB Memory Offset 804h is written to initiate a write from the EEPROM Data register SB Mem ory Offset 808h to the array or a read from the...

Page 513: ...58002004h R W GLD Power Management MSR GLD_MSR_PM 00000000_00000015h Page 518 58002005h R W GLD Diagnostic MSR GLD_MSR_DIAG 00000000_00000000h Page 518 Table 6 79 Security Block Specific MSRs MSR Addr...

Page 514: ...0h Page 529 054h RO SB Random Number Status SB_RANDOM_NUM_STATUS 00000001h Page 529 800h R W SB EEPROM Command SB_EEPROM_COMM 00000000h Page 530 804h R W SB EEPROM Address SB_EEPROM_ADDR 000000FFh Pag...

Page 515: ...ons Bit Name Description 63 24 RSVD Reserved 23 8 DEV_ID Device ID Identifies device 1304h 7 0 REV_ID Revision ID Identifies device revision See AMD Geode LX Processors Specification Update document f...

Page 516: ...ved 34 32 SMI_STATUS SMI Status There are three SMI status sources For each source the individual bit has the following meaning 0 SMI not pending 1 SMI pending Writing a 1 to the bit clears the status...

Page 517: ...se with either the SSMI or Exception flag set This can occur on any of the read responses or on the last write of an encrypt or decrypt operation that also requires a response If the error occurs on a...

Page 518: ...RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD PMD2 RSVD PMD1 RSVD PMD0 GLD_MSR_PM Bit Descriptions Bit Name Description 63 5 RSVD Reserved 4 PMD2 Powe...

Page 519: ...m on read 4 TW Time Write This bit controls the EEPROM write timing within the EEPROM interface module Normally the EEPROM interface signals completion immediately after it finishes shifting out the l...

Page 520: ...W Reset Value 00000000h GLD_MSR_CTRL Bit Descriptions Continued Bit Name Description SB_CTL_A Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD RS...

Page 521: ...encrypts decrypts using the Cipher Block Chaining Mode for the B pointer When reset the AES engine encrypts decrypts using the Electronic Codebook ECB Mode No ini tialization vector is used when in EC...

Page 522: ...EEPROM operation complete INT 1 When enabled 0 allows AES context B complete INT 0 When enabled 0 allows AES context A complete INT SB Memory Offset 010h Type R W Reset Value 00000000h SB_SOURCE_A Re...

Page 523: ...A is asserted SB Memory Offset 000h 0 1 This register can be modified during an operation using the B pointer set while STB is asserted SB Memory Offset 004h 0 1 3 0 RSVD Reserved Set to 0 SB Memory O...

Page 524: ...1 This regis ter can be modified during an operation using the B pointer set while STB is asserted SB Memory Offset 004h 0 1 3 0 RSVD Reserved Set to 0 SB Memory Offset 024h Type R W Reset Value 00000...

Page 525: ...th to be an inte ger number of 16 byte blocks This register should not be changed during an AES encryption or decryption operation using the A pointer set i e while STA is asserted SB Memory Offset 00...

Page 526: ...ister should not be changed during an AES encryption or decryption operation To prevent one process from reading the key written by another process this register is not read able SB Memory Offset 038h...

Page 527: ...encryption or decryption operation To prevent one process from reading the key written by another process this register is not read able SB Memory Offset 040h Type R W Reset Value 00000000h SB_CBC_IV...

Page 528: ...2 Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CBC_IV_2 95 64 SB_CBC_IV_2 Bit Descriptions Bit Name Description 31 0 CBC_IV_2 95 64 CBC Initializa...

Page 529: ...m number Check the TRNG_VALID bit SB Memory Offset 054h 0 before reading this register If the status bit TRNG_VALID is 1 the value in this register is ready for use A 0 in the status bit indicates tha...

Page 530: ...te that the automatic load of the hidden key into the AES key register has com pleted and the key is now ready for use No AES operations using the hidden key regis ter should be initiated before this...

Page 531: ...pansion of the EEPROM size and must be written to 0 7 0 EE_ADDR EEPROM Address This is the 8 bit address for accessing one of the 256 bytes within the EEPROM array SB Memory Offset 808h Type R W Reset...

Page 532: ...st program the Access Con trol byte 1 address 1 of the EEPROM and the part must be reset 10 8 DBL Debug Lock This register holds the 3 bit value of the access control bits used to dis able certain deb...

Page 533: ...d out data LSB first The Instruction and all Data registers are shift registers so if more bits are shifted in than the register can hold only the last bits shifted in the MSBs are used The TAP contro...

Page 534: ...by the TAP 23 18 USER 5 0 User bits used to identify an internal scan chain or if bit 24 is high to access a special internal DR as shown in Table 6 81 17 16 bistEnable 4 3 Bits 4 and 3 of the BIST e...

Page 535: ...reset using the input signal RESET or by a soft reset by writing to an internal MSR in the GLCP RESET is used for power on reset During power on reset all internal blocks are reset until the release o...

Page 536: ...all the GLIU slave functionality The GIO_GLIU slave implements a large MSR space consisting of the required standard GLIU device MSRs and the MSR controls for the I O com panion modes and the Legacy s...

Page 537: ...GIO_NMI GIO_SUSP GIO_INIT GIO_INPUT_DIS GIO_OUTPUT_DIS GIO_INTR GLCP_SUSPA RQ13 SUSPA GLIU Slave I F IGNNE FERR IRQ13_GL SMI_GL LGCY_GL GL Clock PCI_RAW_CLK CLK Control SUSP CIS Table 6 83 GIO_PCI Ou...

Page 538: ...response to a specific CPU initiated instruction I O the SMI signal is transmitted to the processor before the com pletion of the PCI cycle Therefore the companion device must not complete read or wr...

Page 539: ...0000_00000015h Page 544 4C002005h R W GLD Diagnostic MSR GLD_MSR_DIAG 00000000_00000000h Page 544 Table 6 86 GLCP Specific MSRs Summary MSR Address Type Register Name Reset Value Reference GLCP Contro...

Page 540: ...000000_00000000h Page 561 4C00001Dh R W I O Offset 14h GLCP Scale Factor GLCP_TH_SF 00000000_00000000h Page 561 4C00001Eh R W I O Offset 18h GLCP Processor Throttle Off Delay GLCP_TH_OD 00000000_00000...

Page 541: ...2 1 0 RSVD DEV_ID REV_ID GLD_MSR_CAP Bit Descriptions Bit Name Description 63 24 RSVD Reserved Reads as 0 23 8 DEV_ID Device ID Identifies device 0024h 7 0 REV_ID Revision ID Identifies device revisi...

Page 542: ...anagement GLCP_LVL2 SSMI generated when GLCP_LVL2 MSR 4C000019h I O register was read Write 1 to clear 0 has no effect 18 SMI_PMCNT SMI Power Management GLCP_CNT Mask SSMI generated when GLCP_CNT MSR...

Page 543: ...terface detected a read or write of more than 1 data packet size 16 bytes or 32 bytes If a response packet is expected the excep tion bit will be set in all cases the asynchronous error signal will be...

Page 544: ...43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD PM_PCI PM_DBG PM_GLIU GLD_MSR_PM Bit Descriptions Bit Name Descripti...

Page 545: ...function of GLCP_CLK4ACK MSR 4C000013h If the CLK_DLY_EN bit is not set but this register is non zero then this register serves as a timeout for the CLK4ACK behavior MSR Address 4C000009h Type R W Res...

Page 546: ...ic Clock Off When set disables clock to timer logic of secondary GLIU 14 DCGLIU_1 DC GLIU clock 1 Off When set disables DC GLIU Clock 1 vga 13 DCGLIU_0 DC GLIU clock 0 Off When set disables DC GLIU Cl...

Page 547: ...e Enables turning off the Dot clock PLL during sleep when high 16 SYSPLL_EN SYSPLL Enable Enables turning off the system PLLs during sleep when high 15 13 RSVD Reserved 12 OUT_VP VP Outputs When set e...

Page 548: ...was last read Writing this bit has no effect 5 STOPCLK_ NONE Stop Clock Status When read this bit is high if a GLCP stop clock action has occurred since this register was last read Writing this bit h...

Page 549: ...C00000Fh Type R W Reset Value 00000000_00000000h GLCP_DELAY_CONTROLS Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 EN B_DQ B_CMD B_MA SDC...

Page 550: ...ci_ad IRQ13 SUSPA INTA odd bits 29 28 D_PCI_E Output delay for pci_ad CBE PAR STOP FRAME IRDY TRDY DEVSEL REQ GNT even bits 27 26 D_DOTCLK Output delay for DOTCLK 25 24 D_DRBG_O Output delay for DRGB...

Page 551: ...set disables AES GLIU interface clock 29 AESEE AES EEPROM Clock Off When set disables AES EEPROM clock 28 GLCPDBG GLCP Debug Clock Off When set disables GLCP DBG logic clock 27 GLCPGLIU GLCP GLIU Clo...

Page 552: ...CPU to Bus Controller Clock Off When set disables CPU clock to bus controller block 3 MSS CPU to MSS Clock Off When set disables CPU clock to MSS block 2 IPIPE CPU to IPIPE Clock Off When set disable...

Page 553: ...1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AES AESGLIU AESEE GLCPDBG GLCPGLIU GLCPPCI VPVOP VPDOT_2 VPDOT_1 VPDOT_0 VPGLIU_1 VPGLIU_0 PCIPCIF PCIPCI PCIGLIU GLIU1_1 GLIU1_0 DCGLIU_1 DCGLIU...

Page 554: ...7 6 5 4 3 2 1 0 SWFLAGS GLIULOCK CORELOCK HOLD_COUNT RSVD GLIUPD COREPD GLIUBYPASS COREBYPASS LPFEN VA_SEMI_SYNC_MODE PCI_SEMI_SYNC_MODE BOOTSTRAPS CHIP_RESET GLCP_SYS_RSTPLL Bit Descriptions Bit Name...

Page 555: ...ormal operation 9 VA_SEMI_ SYNC_MODE CPU Sync Mode This bit controls whether the CPU uses a FIFO for interfacing with the GLIU If the bit is high the CPU will not use the FIFO It behaves as if the CPU...

Page 556: ...01806h 0000100 266 7 266 7 0000038E_03001808h 0000101 333 9 200 5 00000292_0300180Ah 0000110 333 9 266 7 00000392_0300180Ch 0000111 333 9 333 9 00000492_0300180Eh 0001000 366 10 200 5 00000294_0300181...

Page 557: ...ith would be However not all MDIV NDIV and PDIV settings lock and not all that lock have good long term jitter characteristics The PLL resets to 25 0565 MHz for VGA monitors assuming a 14 31818 MHz in...

Page 558: ...equency determined by the MDIV NDIV PDIV settings This fea ture enables 8 bit VOP of SD data at 27 MHz VOP clock pixel rate only 13 5 MHz 23 16 RSVD Reserved Write as read 15 BYPASS Dot PLL Bypass Thi...

Page 559: ...2 1 0 RSVD CLKSEL GLCP_DBGCLKCTL Bit Descriptions Bit Name Description 63 3 RSVD Reserved Write as read 2 0 CLKSEL Clock Select Selects the clock to drive into the debug logic 000 None 001 CPU Core c...

Page 560: ...any other preparations P_LVL2_IN MSR 4C00001Ch 12 can abort the suspend operation MSR reads to this register return 0 but perform no further action MSR Address 4C000018h Type R W I O Offset 00h Reset...

Page 561: ...icates how long to wait before beginning the processor throttling pro cess as defined by MSR 4C000018h The delay setting is multiplied by 16 to get the number of PCI clock cycles to wait thus setting...

Page 562: ...ress 4C00001Eh Type R W I O Offset 18h Reset Value 00000000_00000000h GLCP_TH_OD Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30...

Page 563: ...6 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD SB SG SR INREFEN OL AB AG AR GLCP_DAC Bit Descriptions Bit Name Description 64 14 RSVD Reserved 13 SB RO Status Blue Read onl...

Page 564: ...29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD MSR_A20M MSR_A20M Bit Descriptions Bit Name Description 63 1 RSVD Reserved 0 MSR_A20M A20M Value of A20M driven to...

Page 565: ..._INT2 GLIU1_INT1 GLIU1_INT0 RSVD RSVD GLIU0_INT5 GLIU0_INT4 GLIU0_INT3 GLIU0_INT2 GLIU0_INT1 GLIU0_INT0 MSR_INTAX Bit Descriptions Bit Name Description 63 15 RSVD Reserved 14 GLIU1_INT6 Value of INTR...

Page 566: ...32 bit 66 MHz PCI bus operation Target support for fast back to back transactions Arbiter support for three external PCI bus masters Write gathering and write posting for in bound write requests Virt...

Page 567: ...us a pending out bound read request need not be deferred while posted in bound write data is flushed The out bound read request may be performed on the PCI bus at the same time that the in bound write...

Page 568: ...PCI device 1 PCI device 15 PCI device 25 PCI device 30 2 4 3 6 5 1 2 7 3 AMD Geode LX Processor 2 4 1 3 6 x 2 4 2 5 1 x 2 4 3 2 7 3 GLPCI_EXT MSR 5000201Eh configuration GLIU port1 PCI device 15 GLIU...

Page 569: ...cycles The standard mechanism for generating PCI configuration cycles as described in the PCI 2 2 specification is used To access the internal PCI configuration registers of the AMD Geode LX processor...

Page 570: ...master to retain control of the PCI bus across multiple bus tenures and the grant hold keeps the grant asserted with an idle bus for a configurable number of clock cycles giving the bus master a chan...

Page 571: ...When performing an in bound write from the PCI bus two errors may occur a detected parity error and a GLIU exception A GLIU exception cannot be relayed back to the originating PCI bus master because i...

Page 572: ...0000015h Page 577 50002005h R W GLD Diagnostic MSR GLD_MSR_DIAG 00000000_00000000h Page 577 Table 6 92 GLPCI Specific Registers Summary MSR Address Type Register Name Reset Value Reference 50002010h R...

Page 573: ...00000_00000000h Page 593 5000201Eh R W GLPCI External MSR Access Configuration GLPCI EXT_MSR 00000000_00000000h Page 594 5000201Fh R W GLPCI Spare 00000000_00000000h Page 595 50002020h R W GLPCI Gener...

Page 574: ...Description 63 24 RSVD Reserved Reserved for future use 23 8 DEV_ID Device ID Identifies device 1054h 7 0 REV_ID Revision ID Identifies device revision See AMD Geode LX Processors Specification Update...

Page 575: ...cleared 18 BME Broken Master Event Read Write 1 to Clear This bit is asserted due to detection of a broken PCI bus master Write 1 to clear BMS MSR 50002010h 26 must be set to enable this event The ev...

Page 576: ...RSVD RO Reserved Read Only Reserved for future use 18 BME Broken Master Event Read Write 1 to Clear This bit is asserted due to detection of a broken PCI bus master Write 1 to clear BME MSR 50002010h...

Page 577: ...0 RSVD PM2 RSVD PM1 RSVD PM0 GLD_MSR_PM Bit Descriptions Bit Name Description 63 5 RSVD RO Reserved Read Only Reserved for future use 4 PM2 Power Mode 2 Power mode for PCI fast clock domain 0 Disable...

Page 578: ...e next cache line of read data The status of the companion device s GNT pin GNT2 is sam pled to determine when the companion device is generating an in bound request 51 49 RTL Retry Transaction Limit...

Page 579: ...icant bits of the PCI latency timer field are fixed as zeros These bits are not used as part of the PCI latency timer comparison 31 PE PCI Error Allow detection of either a parity error or a system er...

Page 580: ...for discarding stale data from in bound read data FIFO 00 Discard at end of in bound read PCI transaction 01 Discard upon timeout 10 Discard at start of out bound write or upon timeout 11 Discard at...

Page 581: ...ferent in bound PCI write transac tions into a single GLIU host write transaction When cleared to 0 PCI write data received from the host bridge target is not held in the posted write buffer a GLIU tr...

Page 582: ...t be idle after a requestor 2 transaction before arbitration continues This is only valid if there is a non zero value for the Request Repeat 2 field R2 bits 59 56 This may be overidden by either COV...

Page 583: ...this bit is cleared the arbiter ignores R0 and H0 bits 51 48 and 35 32 7 BM1 RO Broken Master 1 Read Only Indicates when a broken master is attached to REQ1 This bit is set when the arbiter detects th...

Page 584: ...4 43 42 41 40 39 38 37 36 35 34 33 32 RSVD SUB RSVD SEC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEV GLPCI_PBUS Bit Descriptions Bit Name Description 63 56...

Page 585: ...m PCI 13 D4 D4 Enable Enables memory access to D4000 through D7FFF from PCI 12 D0 D0 Enable Enables memory access to D0000 through D3FFF from PCI 11 CC CC Enable Enables memory access to CC000 through...

Page 586: ...d for future use 5 PF Prefetchable Reads to this region have no side effects 4 WC Write Combine Writes to this region may be combined 3 RSVD RO Reserved Read Only Reserved for future use 2 WP Write Pr...

Page 587: ...CI_E0 Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 FC F8 F4 F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6...

Page 588: ...served Read Only Reserved for future use 31 12 BASE Base of Region 4 KB granularity inclusive 11 9 RSVD RO Reserved Read Only Reserved for future use 8 EN Region Enable Set to 1 to enable access to th...

Page 589: ...eserved Read Only Reserved for future use 31 12 BASE Base of Region 4 KB granularity inclusive 11 9 RSVD RO Reserved Read Only Reserved for future use 8 EN Region Enable Set to 1 to enable access to t...

Page 590: ...eserved Read Only Reserved for future use 31 12 BASE Base of Region 4 KB granularity inclusive 11 9 RSVD RO Reserved Read Only Reserved for future use 8 EN Region Enable Set to 1 to enable access to t...

Page 591: ...eserved Read Only Reserved for future use 31 12 BASE Base of Region 4 KB granularity inclusive 11 9 RSVD RO Reserved Read Only Reserved for future use 8 EN Region Enable Set to 1 to enable access to t...

Page 592: ...eserved Read Only Reserved for future use 31 12 BASE Base of Region 4 KB granularity inclusive 11 9 RSVD RO Reserved Read Only Reserved for future use 8 EN Region Enable Set to 1 to enable access to t...

Page 593: ...eserved Read Only Reserved for future use 31 12 BASE Base of Region 4 KB granularity inclusive 11 9 RSVD RO Reserved Read Only Reserved for future use 8 EN Region Enable Set to 1 to enable access to t...

Page 594: ...45 FUNC 6 Function Number 6 PCI function number to use for MSR accesses addressed to Port 6 44 40 DEVICE 6 Device Number 6 PCI device number to use for MSR accesses addressed to Port 6 39 37 FUNC 5 Fu...

Page 595: ...ount Controls the maximum number of PIO I O writes that may be posted in the GLPCI When cleared one I O write may be posted When set two I O writes may be posted 2 MME Mask External MSR Exceptions Set...

Page 596: ...served Read Only Reserved for future use 47 32 SAMPDIV Sample Divider Controls the frequency of sampling input data fed into each filter With a value of zero each input is sampled on every PCI clock e...

Page 597: ...system designer should be kept at either ground or VIO To prevent possible spurious opera tion For active high inputs to ground through a 20 k 10 pull down resistor and active low inputs to VIO throug...

Page 598: ...900 1 5W 1 36 1 40 1 44 V Filtered version of this supply also supplies PLL power Note 2 Note 2 This parameter is calculated as nominal 3 Core Supply Voltage LX 800 0 9W 1 21 1 25 1 29 V Core Supply V...

Page 599: ...ult For each voltage power is measured at one second inter vals The measurements are then averaged together to produce the final number The CRT resolution is 1024x768x32 bpp at 85 Hz refresh and the T...

Page 600: ...ining Memory Interface I O Power Consumption document publication ID 40554 for the detailed analysis This number is used for the results in DC Current tables Tables 7 3 7 4 and 7 5 Figure 7 1 VMEMLX P...

Page 601: ...LE TFT Display 37 ICOREIDLE 885 IMEMIDLE Terminated 150 Note 2 Note 3 IMEMIDLE Unterminated 80 Note 3 ICC3SLP CRT Display Power State Sleep S1 4 mA ICC3SLP TFT Display 4 ICORESLP 225 IMEMSLP Terminate...

Page 602: ...C3IDLE TFT Display 37 ICOREIDLE 555 IMEMIDLE Terminated 145 Note 2 Note 3 IMEMIDLE Unterminated 75 Note 3 ICC3SLP CRT Display Power State Sleep S1 4 mA ICC3SLP TFT Display 4 ICORESLP 195 IMEMSLP Termi...

Page 603: ...E TFT Display 37 ICOREIDLE 510 IMEMIDLE Terminated 140 Note 2 Note 3 IMEMIDLE Unterminated 70 Note 3 ICC3SLP CRT Display Power State Sleep S1 4 mA ICC3SLP TFT Display 4 ICORESLP 185 IMEMSLP Terminated...

Page 604: ...stics Symbol Parameter Min Max Units Comments VIL Low Level Input Voltage Note 1 PCI 0 5 0 3 VIO V 24 Q3 0 5 0 8 V 24 Q5 0 5 0 8 V 24 Q7 0 5 0 8 V 5V 0 5 0 8 V DDR 0 3 MVREF 0 2 V DDRCLK N A N A VIH H...

Page 605: ...downs are only enabled during reset or power sequencing system behaviors Note 2 24 Q5 50 150 A 24 Q7 50 150 A 5V 50 150 A DDR N A DDRCLK N A IOH Output High Current Note 1 VO VOH Min PCI 500 A 24 Q3...

Page 606: ...IOL min 8 mA with quarter drive set for pad DDRCLK 10 0 mA CIO Input and Output Capacitance Note 1 PCI 8 0 pF 24 Q3 5 0 pF 24 Q5 5 0 pF 24 Q7 5 0 pF 5V 5 0 pF DDR 8 0 pF DDRCLK 15 0 pF Note 1 Refer t...

Page 607: ...cified VCORE 1 14V to 1 26V 1 2V Nominal VIO 3 14V to 3 46V 3 3V Nominal VMEM 2 5V SSTL MVREF DDR 1 25V TC 0o C to 85o C RL 50 CL 50 pF While most minimum maximum and typical AC character istics are o...

Page 608: ...F 0 ns tVAL1 IRQ13 Valid Delay time from SYSREF 2 0 6 0 ns tVAL2 SUSPA Valid Delay time from SYSREF 2 0 6 0 ns tON VIO and VMEM power on after VCORE 0 100 ms Note 2 tMVON MVREF power on after VMEM 0 1...

Page 609: ...U2 REQ 2 0 Input Setup time to SYSREF 4 5 ns tH Input Hold time from SYSREF for all PCI inputs STOP DEVSEL FRAME GNT 2 0 IRDY PAR TRDY REQ 2 0 STOP 0 ns Note 1 tVAL1 Bused signals Valid Delay time fro...

Page 610: ...n Max Unit Comments tCK VIPCLK period 12 5 ns 80 MHz tCH VIPCLK High time 3 0 ns 45 tCK tCL VIPCLK Low time 3 0 ns 45 tCK tVAL VIP_SYNC Output Valid Delay time from VIPCLK 1 0 4 0 ns tSU1 VID 7 0 Inpu...

Page 611: ...K long term output jitter 15 tCK Note 1 tVAL1 DRGB 31 0 Output Valid Delay time from rising edge of DOTCLK 0 5 3 0 ns tVAL2 DISPEN LDEMOD Output Valid Delay time from rising edge of DOTCLK 0 5 3 0 ns...

Page 612: ...trigger Note 2 HSYNC and VSYNC for CRT timing are generated from the same on chip clock that is used to generate the RED GREEN and BLUE signals Table 7 13 CRT Display Recommended Operating Conditions...

Page 613: ...C matching 1 4 Analog Power Supply Rejection 45 dB 1 KHz tRISE Output Rise Time 0 5 1 25 ns Note 3 and Note 4 tFALL Output Fall Time 0 5 1 25 ns Note 3 and Note 4 Note 1 All tests unless otherwise spe...

Page 614: ...DQS 0 25 tCK 0 5 ns Note 3 Note 5 tDQSQh DQ 63 0 Input hold time from DQS 0 25 tCK 0 5 ns Note 3 Note 5 tVAL1 DQ 63 0 DQM 7 0 Output Data Valid Delay time from DQS rising OR falling edge 0 25 tCK 0 4...

Page 615: ...8 DDR Write Timing Measurement Points SDCLK 5 1 P Non DQ Outputs VREF Valid Output n 1 Valid Output n VREF tVAL2Min tVAL2Max VIHD VILD VREF DQS Outputs DQS VIHD VILD VREF DQ Outputs DQ n 1 DQ n VREF D...

Page 616: ...ations 33234H Figure 7 9 DDR Read Timing Measurement Points DQ Inputs VREF DQt VREF DQt 1 SDCLK0 DQS Late Input VREF other DQS Input VREF DQt 1 DQt 2 DQS n Input VREF tSKEW2 tDQSCKMax DQS Early Input...

Page 617: ...0 ns TDI Hold time from TCLK rising edge Functional 2 TGLBus ns Hold for 2 GLBus clocks TDO Output Valid Delay time from TCLK falling edge when running boundary scan test 3 0 70 0 ns TDO Output Valid...

Page 618: ...618 AMD Geode LX Processors Data Book Electrical Specifications 33234H...

Page 619: ...a cycle must be added to the count 6 All clock counts assume an 8 byte span of 32 bit memory IO operands 7 If instructions access a 32 bit operand not within an 8 byte block add one clock for read or...

Page 620: ...ion operation mod Address Mode Specifier Used with the r m field to select addressing mode reg General Register Specifier Uses reg sreg3 or sreg2 encoding depending on opcode field r m Address Mode Sp...

Page 621: ...4 8 1 2 2 d Field Operand Direction When used the 1 bit d field determines which operand is taken as the source operand and which operand is taken as the destination See Table 8 5 8 1 2 3 s Field Imme...

Page 622: ...m field encodings are dependent on the w field and are shown in Table 8 9 Table 8 7 eee Field Encoding eee Field Register Type Base Register 000 Control Register CR0 010 Control Register CR2 011 Contr...

Page 623: ...6 10 101 DS DI d16 SS EBP d32 10 110 SS BP d16 DS ESI d32 10 111 DS BX d16 DS EDI d32 11 xxx See Table 8 9 See Table 8 9 Note 1 d8 refers to 8 bit displacement d16 refers to 16 bit displacement and d3...

Page 624: ...g3 Field FS and GS Segment Register Selection The sreg3 field Table 8 12 is 3 bit field that is similar to the sreg2 field but allows use of the FS and GS segment registers Table 8 10 reg Field reg 16...

Page 625: ...e scale factor multiplies the index value to provide one of the components used to calculate the offset address 8 1 5 2 Index Field Index Selection The index field Table 8 14 specifies the index regis...

Page 626: ...ess Mode with mod r m and s i b Bytes Present 00 000 DS EAX scaled index 00 001 DS ECX scaled index 00 010 DS EDX scaled index 00 011 DS EBX scaled index 00 100 SS ESP scaled index 00 101 DS d32 scale...

Page 627: ...of the processor as shown in Table 8 16 8 2 1 2 CPUID Instruction with EAX 00000001h Standard function 00000001h EAX 00000001h of the CPUID instruction returns the processor type family model step pi...

Page 628: ...ported EDX 23 1 MMX MMX Instruction Set and Architecture EDX 22 20 000 Reserved EDX 19 1 CLFSH CLFLUSH feature is supported EDX 18 0 PN 96 Bit Serial Number Feature Not supported EDX 17 0 PSE36 36 Bit...

Page 629: ...d the supported extended feature flags in the EDX register The EBX and ECX reg isters are reserved Table 8 20 provides a register map In the EDX register each flag refers to a specific extended featur...

Page 630: ...t supported EDX 19 0 MP Multiprocessing capability Not supported EDX 18 0 Reserved EDX 17 0 PSE36 36 Bit Page Size Extensions Not supported EDX 16 0 PAT Page Attribute Table Not supported EDX 15 1 CMO...

Page 631: ...ian format If the name is shorter than 48 characters long the remaining bytes are filled with ASCII NUL characters 00h Table 8 22 CPUID Instruction with EAX 80000002h 80000003h or 80000004h Register R...

Page 632: ...ent EAX 00000000h 4 MB L1 TLB Information Indicates no 4 MB L1 TLB EBX FF10FF10h 4 KB L1 TLB Information Decodes to eight fully associative code TLB and eight fully associative data TLB entries ECX 40...

Page 633: ...ames have been abbreviated and various con ventions used to indicate what effect the instruction has on the particular flag Table 8 25 Processor Core Instruction Set Table Legend Symbol or Abbreviatio...

Page 634: ...olean AND 0 x x u x 0 b h Register to Register 2 00dw 11 reg r m 1 1 Register to Memory 2 000w mod reg r m 1 1 Memory to Register 2 001w mod reg r m 1 1 Immediate to Register Memory 8 00sw mod 100 r m...

Page 635: ...OVC CMOVNAE Move if Below Carry Not Above or Equal 1 1 r Register Register Memory 0F 42 mod reg r m CMOVE CMOVZ Move if Equal Zero 1 1 r Register Register Memory 0F 44 mod reg r m CMOVNE CMOVNZ Move i...

Page 636: ...CWDE Convert Word to Doubleword Extended 98 3 3 DAA Decimal Adjust AL after Addition 27 2 2 x x x x x DAS Decimal Adjust AL after Subtraction 2F 2 2 x x x x x DEC Decrement by 1 x x x x x b h Register...

Page 637: ...rupt Return CF 6 13 13 239 x x x x x x x x x g h j k r JB JNAE JC Jump on Below Not Above or Equal Carry r 8 bit Displacement 72 1 1 Full Displacement 0F 82 1 1 JBE JNA Jump on Below or Equal Not Abov...

Page 638: ...ement 0F 8A 1 1 JS Jump on Sign r 8 bit Displacement 78 1 1 Full Displacement 0F 88 1 1 LAHF Load AH with Flags 9F 2 2 LAR Load Access Rights 0F 02 mod reg r m x a g h j p From Register Memory 9 LDS L...

Page 639: ...F 20 11 eee reg 2 5 2 5 MOV Move To From Debug Registers l Register to DR 0F 23 11 eee reg 10 18 10 18 DR to Register 0F 21 11 eee reg 8 18 8 18 MOV Move To From Test Registers u l u Register to TR 0F...

Page 640: ...1 1 SS 16 1 1 DS 1E 1 1 ES 06 1 1 FS 0F A0 1 1 GS 0F A8 1 1 Immediate 6 10s0 1 1 PUSHA Push All General Registers 60 8 8 b h PUSHF Push FLAGS Register 9C 2 2 b h RCL Rotate Through Carry Left Register...

Page 641: ...te to SP C2 3 3 Intersegment CB 6 10 48 Intersegment Adding Immediate to SP CA 7 10 48 Protected Mode Different Privilege Level Intersegment Intersegment Adding Immediate to SP 35 35 ROL Rotate Left R...

Page 642: ...ETL SETNGE Set Byte on Less Not Greater or Equal h To Register Memory 0F 9C mod 000 r m 1 1 SETLE SETNG Set Byte on Less or Equal Not Greater h To Register Memory 0F 9E mod 000 r m 1 1 SETNB SETAE SET...

Page 643: ...SMINT Software SMM Entry 0F 38 56 58 56 58 0 0 0 0 0 0 0 0 0 s u s u STC Set Carry Flag F9 1 1 1 STD Set Direction Flag FD 2 2 1 STI Set Interrupt Flag FB 1 1 1 m SUB Integer Subtract x x x x x x b h...

Page 644: ...3 000w mod reg r m 1 1 Memory to Register 3 001w mod reg r m 1 1 Immediate to Register Memory 8 00sw mod 110 r m 1 1 Immediate to Accumulator short form 3 010w 1 1 Note 1 The instructions RDTSC RDPMC...

Page 645: ...e by this instruction automatically assert LOCK to maintain descriptor integrity in multiprocessor systems k JMP CALL INT RET and IRET instructions referring to another code segment cause an exception...

Page 646: ...R DMINT DMM_HEADER CURRENT_IP IP OF DMINT instruction DMM_HEADER CS_LIMIT CS LIMIT DMM_HEADER CS_BASE CS BASE DMM_HEADER CS_SELECTOR CS SELECTOR DMM_HEADER CS_FLAGS CS FLAGS DMM_HEADER SS_SELECTOR SS...

Page 647: ...DMINT 8 3 4 2 ICEBP Call Debug Exception Handler Operation Same as an INT 1 instruction Description The ICEBP instruction generates a call to the Debug exception handler It s advantage over the INT 1...

Page 648: ...ters Writing to a test register has no side effects Reading from a test register has no side effects The reg field within the ModR M byte specifies which of the test registers is involved Reg values o...

Page 649: ...0 DR6 4 DR7 8 XDR6 C XDR7 10 SS FLAGS SS SELECTOR 14 G B 0 Av 0 1 DPL 1 0 E W A INDEX TI RPL CS FLAGS CS SELECTOR 18 G D 0 Av 0 1 DPL 1 1 Cf R A INDEX TI RPL CS BASE 1C 0 CS LIMIT 20 CURRENT_IP 24 NE...

Page 650: ...in SMM and if the processor is not in DMM Notes The reg field within the mod r m byte specifies which segment s register and descriptor should be restored Reg fields of 0 1 2 3 4 and 5 specify the ES...

Page 651: ...nd if the processor is not in DMM Notes The reg field within the mod r m byte must be zero for the RSLDT instruction to be recognized The RSLDT instruction does not check its memory operand for validi...

Page 652: ...m SMI 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DR7 4 EFlags 8 CR0 C CURRENT_IP 10 NEXT_IP 14 CS_FLAGS Code Segment Selector 18 G D 0 Av 0 1 DPL 1 1 Cf R A...

Page 653: ...in memory Flags Affected None Exceptions UD If current privilege level is not 0 or the SMM_INST_EN 0 and if the processor is not in SMM and if the processor is not in DMM Notes The reg field within t...

Page 654: ...GS SMM_HEADER CS_LIMIT CS LIMIT SMM_HEADER CS_BASE CS BASE SMM_HEADER CS_SELECTOR CS SELECTOR SMM_HEADER CS_FLAGS CS FLAGS SMM_HEADER NEXT_IP IP OF INSTRUCTIOn after SMINT SMM_HEADER CURRENT_IP IP of...

Page 655: ...in DMM Notes The SMINT instruction will clear the V X M H P I I O ADDRESS I O SIZE and I O DATA fields of the SMM header The CURRENT_IP field of the SMM header will point to the SMINT instruction The...

Page 656: ...Save Local Descriptor Table Register and Descriptor Operation Description Write the Local Descriptor Table register and descriptor to memory Below is the format of the descriptor contents in mem ory F...

Page 657: ...rmat of the descriptor contents in memory Flags Affected None Exceptions UD If current privilege level is not 0 or the SMM_INST_EN 0 and if the processor is not in SMM and if the processor is not in D...

Page 658: ...in the instruction sets are listed in Table 8 27 Note The following opcodes are reserved D9D7 D9E2 D9E7 DDFC DED8 DEDA DEDC DEDD DEDE and DFFC If a reserved opcode is executed unpredictable results ma...

Page 659: ...p of stack register pointed to by SSS in the status register ST 1 Note 1 FPU register next to TOS ST n Note 1 A specific FPU register relative to TOS M WI 16 bit integer operand from memory M SI 32 bi...

Page 660: ...ation MMX Register 2 to MMX Register 1 0F63 11 mm1 mm2 MMX reg 1 qword packwb signed sat MMX reg 2 MMX reg 1 2 Memory to MMX Register 0F63 mod mm r m MMX reg qword packwb signed sat memory MMX reg 2 P...

Page 661: ...with Memory 0FE3 mod mm r m MMX reg 1 word round up MMX reg word Memory64 word 01h 2 2 PCMPEQB Packed Byte Compare for Equality MMX Register 2 with MMX Register 1 0F74 11 mm1 mm2 MMX reg 1 byte FFh i...

Page 662: ...tmp2 windex 0 imm8 2 PMADDWD Packed Multiply and Add MMX Register 2 to MMX Register 1 0FF5 11 mm1 mm2 MMX reg 1 low dword MMX reg 1 low dword MMX reg 2 low sign word MMX reg 1 low dword MMX reg2 high...

Page 663: ...d high word MMXreg 1 word MMX reg 2 word 2 MMX Register with Memory64 0FE4 mod mm r m MMX reg word high word MMX reg word Memory64 word 2 PMULHW Packed Multiply High MMX Register 2 to MMX Register 1 0...

Page 664: ...MMX reg dword shift right by memory dword shifting in sign bits 2 MMX Register by immediate 0F72 11 100 mm MMX reg dword MMX reg dword shift right by im byte shifting in sign bits 2 PSRAW Packed Shif...

Page 665: ...egister 2 to MMX Register 1 0FF9 11 mm1 mm2 MMX reg 1 word MMX reg 1 word MMX reg 2 word 2 Memory to MMX Register 0FF9 mod mm r m MMX reg word MMX reg word memory64 word 2 PUNPCKHBW Unpack High Packed...

Page 666: ...pipeline PXOR Bitwise XOR MMX Register 2 to MMX Register 1 0FEF 11 mm1 mm2 MMX reg 1 qword MMX reg 1 qword logic exclusive OR MMX reg 2 qword 2 Memory to MMX Register 0FEF 11 mm reg MMX reg qword memo...

Page 667: ...FCMOVNBE Floating Point Conditional Move if Not Below or Equal DB 1101 0 n If CF 0 and ZF 0 ST 0 ST n 1 3 FCMOVNU Floating Point Conditional Move if Not Unordered DB 1101 1 n If PF 0 ST 0 ST n 1 3 FCO...

Page 668: ...M XR onto stack 1 3 64 bit Real DD mod 000 r m Push M DR onto stack 1 3 32 bit Real D9 mod 000 r m Push M SR onto stack 1 3 FBLD Load Packed BCD Data to FPU Register DF mod 100 r m Push M BCD onto sta...

Page 669: ...DB mod 010 r m M SI TOS 4 16 bit Integer DF mod 010 r m M WI TOS 3 FISTP Store Integer FPU Register Pop 64 bit Integer DF mod 111 r m M LI TOS then pop TOS 6 32 bit Integer DB mod 011 r m M SI TOS th...

Page 670: ...DEDC DEDD DEDE and DFFC If a reserved opcode is executed unpre dictable results may occur exceptions are not generated FISUB Floating Point Integer Subtract 32 bit Integer DA mod 100 r m TOS TOS M SI...

Page 671: ...MMX reg 1 low dword MMX reg 1 low dword MMX reg 1 high dword MMX reg 1 high dword Memory64 low dword Memory64 high dword PFADD Packed Floating Point Addition 2 MMX Register1 with MMX Register2 0F0F 1...

Page 672: ...d Positive Negative Accumulate 2 MMX Register1 with MMX Register2 0F0F 11 mm1 mm2 8E MMX reg 1 low dword MMX reg 1 low dword MMX reg 1 high dword MMX reg 1 high dword MMX reg 2 low dword MMX reg 2 hig...

Page 673: ...11 mm1 mm2 9A MMX reg 1 dword MMX reg1 dword MMX reg 2 dword MMX Register with MMX Memory64 0F0F mod mm r m 9A MMX reg dword MMX reg dword Memory64 dword PFSUBR Packed Floating Point Reverse Subtracti...

Page 674: ...t 1 of the ID_CONFIG MSR MSR 00001250h 8 4 1 2 PFRSQRTV Floating Point Reciprocal Square Root Approximation Operation Description PFRSQRTV performs the same operation as the PFRSQRT instruction except...

Page 675: ...ckage Specifications 33234H 9 0Package Specifications 9 1 Physical Dimensions The figures in this section provide the mechanical package outline for the BGU481 481 terminal Ball Grid Array Cavity Up F...

Page 676: ...676 AMD Geode LX Processors Data Book Package Specifications 33234H Figure 9 2 BGU481 Bottom View Dimensions...

Page 677: ...dering number shown above for viewing clarity only C Display Type V CRT TFT and VOP Performance Indicator Package Type EE BGU TE PBGA C 0 C to 85 C Commercial D 0 C to 85 C Commercial Lead Pb Free H 0...

Page 678: ...ing Voltage System Bus Speed EEPROM Indicator Display Type Case Temperature Solder Type Note ALX G 900 EE Y J 2 V H ALX D 800 EE X J 2 V C D F C C D ALX C 700 EE T H 2 V C D C C D ALX C 600 EE T K 2 V...

Page 679: ...y 2008 Minor edits corrections See Table A 3 for details H February 2009 Added LX 600 0 7W parameters Table A 3 Edits to Current Revision Section Revision Section 1 0 Overview Section 1 1 General Desc...

Page 680: ...One AMD Place P O Box 3453 Sunnyvale CA 94088 3453 USA Tel 408 749 4000 or 800 538 8450 TWX 910 339 9280 TELEX 34 6306 www amd com...

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