AMD Elan SC520, User Manual, Page: 58 / 444

System Initialization
3-2 Élan™SC520 Microcontroller User’s Manual
Some use a commercial real-time operating system (RTOS), a custom RTOS, or a simple
‘main loop’ or non-preemptive executive. In general, the executive or RTOS generally
interfaces to the hardware using a hardware dependent layer called a
board support
package (BSP)
1
.
In general, the system initialization flow for a native embedded system follows this
sequence:
1 < Reset event >
2 Near Jump to reset handler from the reset vector
3 Switch to simple protected mode
4 Determine the cause of the reset
5 Initialize the DRAM controller and DRAM. Size the DRAM
6 Setup a Stack and begin execution from “C” code
7 if (NOT Execute-In-Place) then
8 Copy the Operating System to DRAM
9 Jump to the operating system’s entry point
10 Set up the Global Descriptor Table (GDT), Local Descriptor Table (LDT),
Interrupt Descriptor Table (IDT), fault handlers, page tables, and a
Task State Segment (TSS) for the operating system, application or
executive.
11 Set the processor speed
12 Configure the GP bus timings
13 Configure the pin multiplexing
14 Configure the GP bus chip selects
15 Configure the Programmable Address Region (PAR) registers
16 Configure the interrupt mappings
17 Configure the programmable I/O (PIO) pins
18 Configure the PCI bus controller and arbitration mode
19 Initialize a periodic timer interrupt (if necessary)
20 Now, the BSP can initialize devices external to the ÉlanSC520
microcontroller and otherwise continue to start the operating system,
I/O drivers and application.
In the above example, the switch to simple protected mode (line 3) sets the processor CS
register and the CS descriptor cache. This disables the redirection of the reset region to
the reset segment (see “Reset Vector and Reset Segment” on page 3-5 for more
information).
In line 3 above, the term simple protected mode means that the protected mode environment
(GDT, LDT, IDT, and TSS) is the simplest kind possible. For example, both the LDT and
IDT can be empty and the TSS and GDT can contain minimal information. Or, alternatively,
the IDT can be empty. This means that exceptions cannot be handled, but this should not
be a problem for the short period that the initialization code runs. More importantly, the TSS
and GDT for simple protected mode can be contained in read-only memory (usually Flash)
and do not have to be created at runtime. Once the DRAM is operational, then more
extensive GDT, LDT, and IDT tables and one or more appropriate TSS can be setup in
DRAM.
1. There is no standard term for this component. Other terms for BSP are OEM Adaptation
Layer (OAL), Hardware Adaptation Layer (HAL), or Porting Layer. A BSP is like a BIOS, but is
almost always unique to a specific executive or RTOS. This is especially true for comercially
available RTOS products. A BSP for one vendor’s RTOS generally does not work with products
from another vendor. Also, where a BIOS is most often a 16-bit real-mode entity, a BSP is
usually a 32-bit protected mode entity. Lastly, operating systems and applications always
communicate with a BIOS using software interrupts (or other run-time mechanisms), but a BSP
is often linked directly to an executive or application to form a single executable and is called
directly using the CALL instruction.