AMD Elan SC520, User Manual, Page: 385 / 444

System Test and Debugging
Élan™SC520 Microcontroller User’s Manual 24-11
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The ÉlanSC520 microcontroller’s address decode logic allows notification of violations
of write-protected memory regions, which is useful when debugging a software task that
is illegally attempting to modify a portion of memory modified as write-protected. See
Chapter 4, “System Address Mapping”, for further details on enabling this feature.
■
The ÉlanSC520 microcontroller’s address decode logic also allows notification of
violations of memory regions marked as non-executable address space. This is useful
when debugging a software task that is attempting to execute code from a portion of
memory designated for data only. See Chapter 4, “System Address Mapping”, for further
details on enabling this feature.
■ If the ICE_ON_RST bit is set in the Reset Configuration (RESCFG) register (MMCR
offset D72h), the Am5
x
86 CPU enters AMDebug mode whenever it is reset (immediately
after the reset sequence). The debugging tool can read the Reset Status (RESSTA)
register (MMCR offset D74h) to identify the source of the reset.
■ The programmable interrupt controller (PIC) supports many features, such as the ability
to mask specific interrupts and to force software interrupts, which can also be useful
during the system debugging phase. See Chapter 15, “Programmable Interrupt
Controller”, for details on configuring interrupts in a system.
■ To assist in the development of software to handle ECC single-bit and multi-bit errors,
the ECC Check Code Test (ECCCKTEST) register (MMCR offset 23h) is provided. This
register can be used to override the automatically-generated ECC check code with a
user-provided check code for the following SDRAM write access.
24.4.4 Software Considerations
The cache should always be flushed after the cacheability attribute for an address range
is changed from cacheable to noncacheable for any memory region (by programming a
PAR register), or when the cache write policy is changed from write-back to write-through.
Software must include proper interrupt service routines and exception handlers when
enabling write-protection violation interrupts and non-executable region attributes in the
Address Decode Control (ADDDECCTL) register (MMCR offset 80h). Note that in the case
of the write-protect violation, the address of the violation is latched in a 32-bit register and
retained until the register is cleared by software; any additional violations that occur before
the register is read will not be seen.
A write-protection violation occurs when the Am5
x
86 CPU, any PCI bus master, or the GP-
DMA controller attempt to write to any memory region that has been marked as write-
protected by a PAR register attribute. When this occurs, the cycle is always forwarded to
SDRAM as a write-protected cycle (the SDQM3–SDQM0 pins are forced inactive), and the
original data is discarded.
24.4.5 Latency
Some features described in this chapter to aid the debugging process may affect system
performance, and these effects should therefore be considered when enabling or disabling.
A brief list of the features and their direct affects on latency are listed.
■ Write buffer and system test modes do not affect performance, unless the SDRAM timing
has been programmed at slower speeds to accommodate external capturing of data.
■ Nonconcurrent arbitration affects PCI bus latency, the Am5
x
86 CPU’s latency, and the
GP-DMA controller’s latency, since ownership of both buses must be negotiated before
any transaction is allowed to begin. The effect in a system with no PCI bus masters or
GP-DMA initiators is much less, because bus acquisition is immediate.