AMD Elan SC520, User Manual, Page: 356 / 444

UART Serial Ports
21-10 Élan™SC520 Microcontroller User’s Manual
When in 16550-compatible mode, the receiver and transmitter FIFO buffers can be cleared
by the RF_CLR and TF_CLR bits in the UART x FIFO Control (UARTxFCR) register,
respectively. The receiver FIFO trigger level can be programmed by RFRT field of the UART
x FIFO Control (UARTxFCR) register.
21.5.5 DMA Interface
To support higher serial data transfer rates, both UARTs support DMA. For more detailed
information on the operation of the GP-DMA controller, see Chapter 14, “GP Bus DMA
Controller”.
The ÉlanSC520 microcontroller’s DMA interface provides up to four 8-bit DMA channels
to support the two integrated UARTs. Each UART can use up to two DMA channels: one
for receive and one for transmit. DMA transfers are supported for both 16450- and 16550-
compatible modes.
The DMA controller can perform read and write operations in single cycle, demand, or block
transfer mode. However, block transfer mode is not supported for UART transfers.
21.5.5.1 Transmit DMA
The internal tx_dma_req signal from the UART is asserted whenever there is room for
another transmit character in the UART.
■ For 16450-compatible UART mode, this means that either the internal transmitter shift
register or the UART x Transmit Holding (UARTxTHR) register can accept a character.
■ For 16550-compatible mode, this means that the transmit FIFO is not full.
21.5.5.2 Receive DMA
The internal rx_dma_req signal from the UART is asserted:
■ For 16550-compatible mode, whenever the receive trigger level was reached or a time-
out has occurred. The rx_dma_req signal is made inactive when the receive FIFO is
completely empty.
■
For 16450-compatible UART mode, whenever the UART x Receive Buffer (UARTxRBR)
register contains a valid character.
For either mode, the internal rx_dma_req signal is deasserted whenever a character is
received with an error condition. This allows software to inspect the error condition before
the error status is cleared by a subsequent DMA transfer. Once software has cleared the
error status by a read of the UART x Line Status (UARTxLSR) register, the rx_dma_req is
asserted when another character is present in the UART.
21.5.6 Clocking Considerations
The clock input to the UARTs to support standard PC/AT baud selections is 1.8432 MHz.
A clock of 18.432 MHz is also provided to the UARTs for fast serial communication. This
frequency is determined by the CLK_SRC bit in the UART x General Control (UARTxCTL)
register.
21.5.7 Interrupts
Each of the two UARTs on the ÉlanSC520 microcontroller provides its own interrupt to the
programmable interrupt controller. Each ÉlanSC520 microcontroller serial port has an
internal interrupt signal that can be mapped to uart1_irq or uart2_irq. For detailed
information, see Chapter 15, “Programmable Interrupt Controller”.