AMD Elan SC520, User Manual, Page: 312 / 444

Programmable Interval Timer
16-4 Élan™SC520 Microcontroller User’s Manual
16.5.3 PIT Channel 2
The gate line for PIT Channel 2 is controlled by the PIT_GATE2 bit in the System Control
Port B (SYSCTLB) register (Port 0061h) or the external input pin PITGATE2. PITGATE2 is
a multiplexed pin; if it is disabled, the gate line is controlled only by the PIT_GATE2 bit in
the System Control Port B (SYSCTLB) register.
The output of the PIT Channel 2 is hardwired internally on the ÉlanSC520 microcontroller
to drive an input of the programmable interrupt controller and can be read in the
PIT_OUT2_STA bit of the System Control Port B (SYSCTLB) register (Port 0061h). See
Chapter 15 for more information on interrupt steering. The output goes to the external output
pin PITOUT2 when the PIT_OUT2_ENB bit is set in the System Control Port B (SYSCTLB)
register.
PIT Channel 2 works in all six modes.
16.5.4 Operating Modes
The modes for the each PIT channel are specified in Counter Mode (CTR_MODE) bit field
in the PIT Mode Control (PITMODECTL) register (Port 0043h).
16.5.4.1 Mode 0: Interrupt on Terminal Count
In interrupt on terminal count mode,
1. When the initial count is loaded into the PIT Channel x Count (PITxCNT) register, the
output of the counter goes Low.
2. The count value decrements by one for each input clock pulse if the gate input is held
High.
3. If the gate input is held Low, count maintains its value until after a rising edge of clock
after the Gate goes High again.
4. The output of the counter is initially Low and will remain Low until the counter reaches
zero. The output then goes High until a new count or a new mode 0 control word is
loaded into the Counter.
16.5.4.2 Mode 1: Hardware-Retriggerable One-Shot
In hardware-retriggerable one-shot mode:
1. After an initial count is loaded into the PIT Channel 2 Count (PIT2CNT) register, a rising
edge on the gate signal causes the output of the counter to go Low.
2. The count value decrements with each successive clock pulse.
3. The gate trigger begins the one-shot pulse with the output going Low until the count
reaches zero.
4. Output then goes High and remains High until the clock pulse after the next trigger.
The duration of the one-shot pulse is:
Duration = Initial count * Period of the clock input
This mode is called hardware-retriggerable because, once an output pulse has started, if
a rising edge is experienced at the gate input, the counter is reloaded with the initial count
and the pulse continues until the new count expires. This mode is supported on PIT Channel
2 only.