AMD Elan SC520, User Manual, Page: 265 / 444

General-Purpose Bus Controller
Élan™SC520 Microcontroller User’s Manual 13-21
command strobes will be deasserted after the GPRDY signal is internally synchronized and
sampled asserted by the 33-MHz clock and after the programmed pulse width value for the
strobe has expired.
Figure 13-16 GPRDY Timing
13.5.10 Interrupts
External devices that assert interrupts use the GPIRQ10–GPIRQ0 signals for this purpose.
The GPIRQx interrupt signals bypass the GP bus controller and are routed to the
programmable interrupt controller (PIC). See Chapter 15, “Programmable Interrupt
Controller”, for more information.
13.5.11 Latency
13.5.11.1 8/16-Bit GP Bus Width
Due to the smaller data width of the GP bus, 32-bit accesses from the Am5
x
86 CPU are
broken up into separate 8-bit or 16-bit GP bus cycles. During this time, no other Am5
x
86
CPU bus cycle can be generated, and neither the GP-DMA or an external PCI bus master
can access SDRAM.
13.5.11.2 Slow GP Bus Cycles
If the interface timing is programmed to have slow GP bus cycles or if GPRDY is used to
stretch cycles for long periods of time, the system performance can be affected because
the CPU bus is monopolized.
Note: Very long GP bus cycles can cause the PCI host bridge target controller to violate
the 10 µs memory write maximum completion time limit set in the PCI Local Bus
Specification, Revision 2.2. In PCI bus 2.2-compliant designs, software must limit the length
of GP bus cycles and GP-DMA demand- or block-mode transfers.
13.5.11.3 Noncacheable GP Bus
All GP bus accesses are noncacheable. Therefore, code execution out of this bus is not
recommended.
Address
Read Data
GPA25–GPA0
GPCSx
GPD15–GPD0
Write Data
GPD15–GPD0
GPRDY
Notes:
The programmable timing would cause the
cycle to end here, but the GPRDY
deassertion stretches the cycle further.
GPRDY assertion then allows the cycle to
continue.
GPMEMRD, GPMEMWR,
GPIORD, or GPIOWR