AMD Elan SC520, User Manual, Page: 239 / 444

ROM/Flash Controller
Élan™SC520 Microcontroller User’s Manual 12-9
12.5.3 Bus Cycles
The ROM controller always returns the amount of read data requested by the Am5
x
86 CPU,
i.e., brdy is returned for all read transfers from ROM. The actual number of ROM accesses
is determined by the cacheability status of the Am5
x
86 CPU transfer, the number of bytes
requested, and the width of the ROM. The minimum number of data to be transferred is
one byte. The maximum number of data to be delivered is 16 bytes (a cache-line fill).
Depending on the ROM width, this leads to different numbers of accesses to fetch the
requested data (see Table 12-5).
12.5.3.1 Single CPU Read Access
Figure 12-7 shows an example for the fetching of 16-bits of data, GPD15–GPD0, from an
8-bit non-page-mode ROM configured for one wait state. The transfer starts with a bus
cycle initiation (i.e., ads asserted). The ROM controller then performs two ROM accesses
and accumulates the amount of requested data prior to terminating the cycle. Note that
only one ROM cycle would be performed had the ROM device been implemented as 16-
or 32-bit.
Table 12-4 Example: ROM Access Timing and Wait States
1
Notes:
1. This example assumes that a 33.333-MHz
crystal is being used in the system.
Wait States Access Timing (ns)
0 10
1 40
2 70
4 130
Table 12-5 Accesses and ROM Width
ROM Width
Minimum Number of
Accesses
Maximum Number of
Accesses (Cache-Line Fill)
8 bit 1 16
16 bit 1 8
32 bit 1 4