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AMD Athlon™ Processor Model 6

Revision Guide

Publication #

24332

Rev:

E

Issue Date:

December 2002

Preliminary Information

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2
3
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Summary of Contents for Athlon 6

Page 1: ...AMD Athlon Processor Model 6 Revision Guide Publication 24332 Rev E Issue Date December 2002 Preliminary Information...

Page 2: ...et forth in AMD s Standard Terms and Conditions of Sale AMD assumes no liability whatsoever and disclaims any express or implied warranty relating to its products including but not limited to the impl...

Page 3: ...December 2002 E Added errata 22 24 July 2002 D Added errata 20 and 21 October 2001 C Added silicon revision A5 information Added erratum 18 and 19 Added Table 2 Cross reference of Erratum to Processo...

Page 4: ...model 6 to deviate from the published specifications Revision Determination This section which starts on page 16 shows the AMD Athlon processor model 6 identification numbers returned by the CPUID ins...

Page 5: ...that have been resolved from early revisions of the processor have been deleted and errata that have been reconsidered may have been deleted or renumbered Table 1 Cross Reference of Product Revision t...

Page 6: ...Errata Number Workstation Server1 Desktop2 Mobile3 16 X X X 17 X 18 X 19 X X X 20 X X X 21 X X X 22 X X X 23 X X X 24 X X X Notes 1 The workstation server segment currently includes the AMD Athlon MP...

Page 7: ...logical address Non conformance When the logical address designated by the INVLPG instruction is mapped by a 4 Mbyte page mapping and LA 21 is equal to one it is possible that the TLB will still retai...

Page 8: ...the other processor B is trying to read the same cacheable I O block and at the same time both processors are also trying to write a different memory based cache block then processor B may hang Should...

Page 9: ...ial cycle is issued Several bus clocks later the WrVictimBlk command for the victim will be issued This violates the specification which states that all processor based commands should be finished bef...

Page 10: ...perly after a microcode patch is loaded Non conformance The processor has the patch RAM BIST function disabled Since BIST is not run on the patch RAM reliable operation of the patch RAM cannot be guar...

Page 11: ...structions that are uncounted only when certain data dependencies exist are LAR LSL VERR VERW if they clear the Zero Flag FXSAVE FXRSTOR if FERR is changed FPU instructions with exceptional data condi...

Page 12: ...validates the instruction cache line with address A and brings the line into the L1 data cache marking it as modified However the instruction buffer which also contains some bytes from address A is no...

Page 13: ...tion exception Non conformance If the RDPMC is executed in real mode with a specific illegal value of ECX 4 then the processor may incorrectly enter the GP fault handler as if it were in 32 bit real m...

Page 14: ...formance When a task gate is used by a CALL or JMP instruction and any debug breakpoint is enabled through the DR7 LE or GE bits the processor may under certain timing scenarios incorrectly use the ne...

Page 15: ...art the processor should immediately enter the debug trap handler Non conformance Under this scenario the processor does not enter the debug trap handler but instead returns to the instruction followi...

Page 16: ...rmation 2 Revision Determination Table 3 shows the AMD Athlon processor model 6 identification numbers returned by the CPUID instruction for each revision of the processor Table 3 CPUID Values for the...

Page 17: ...information AMD Athlon XP Processor Data Sheet Processor Model 6 order 24309 Mobile AMD Athlon 4 Processor Model 6 CPGA Data Sheet order 24319 AMD Athlon MP Processor Model 6 Data Sheet Multiprocesso...

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