AMD Am79C930 Preliminary Manual Download Page 12

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AMD

P R E L I M I N A R Y

Am79C930

TIMING WAVEFORMS

148

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PCMCIA Bus Interface Waveforms

148

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ISA Bus Interface Waveforms

150

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Memory Bus Interface Waveforms

151

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CLOCK WAVEFORMS

152

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TAI WAVEFORMS

153

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PROGRAMMABLE INTERFACE WAVEFORMS

154

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IEEE 1149.1 INTERFACE WAVEFORMS

155

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AC TEST REFERENCE WAVEFORMS

156

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5.0 V PCMCIA AC Test Reference Waveform

156

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3.3 V PCMCIA AC Test Reference Waveform

156

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5.0 V NON-PCMCIA AC Test Reference Waveform

157

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3.3 V NON-PCMCIA AC Test Reference Waveform

157

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PHYSICAL DIMENSIONS

158

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APPENDIX A: Typical Am79C930 System Application

A-1

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Device Configuration

A-1

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Frame Transmission

A-2

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Frame Reception

A-2

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Summary of Contents for Am79C930

Page 1: ...al 3 V and 5 V supply applications Low power mode allows reduced power consumption for critical battery powered applications 144 pin Thin Quad Flat Pack TQFP package available for space critical appli...

Page 2: ...ns planned to be sup ported in volume for this device Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations AM79C930 V C...

Page 3: ...1 TXCMD TXCMD TXMOD TXDATA TXDATA RXPE TXPE HFPE HFCLK LFPE LFCLK FDET LNK ACT RXC Transceiver Attachment Interface MAC Control Unit 80188 core Bus Interface Unit PCMCIA MOE MWE MA 16 0 MD 7 0 XCE SCE...

Page 4: ...R0 System Interrupt Generator SIR1 SIR7 ISA Memory Base ISA I O Base MD 7 0 MA 16 0 80188 Interrupt Generator IREQ PCMCIA Config Registers ALE CA16 Latch Bus Multi plexer CAD7 0 CA15 8 MIR0 MIR1 MIR15...

Page 5: ...I O and DMA TIR0 Interrupt Generator TCR31 TX FIFO 8 Bytes TXD RESET TCR TIR TIR31 TCR0 IRQ DRQ 1 0 RX FIFO 15 Bytes P S S P C R C RXD SFD Detect FDET 40 5 10 20 M U X TXC DPLL M U X RXCIN RXCSEL RXC...

Page 6: ...AY BLOCK DIAGRAM 19 CONNECTION DIAGRAM 20 ISA Plug And Play 20 ISA PLUG AND PLAY PIN LIST 21 Listed By Pin Number 21 Listed By Pin Name 22 ISA PLUG AND PLAY PIN SUMMARY 23 PIN DESCRIPTIONS 25 Pins wit...

Page 7: ...129 TXPE 40 Pin 131 TXMOD 40 Pin 132 ANTSLT 40 Pin 141 ANTSLT LA23 40 Pin 142 TXCMD LA21 41 Pin 143 TXDATA LA20 41 Pin 144 LLOCKE SA15 41 FUNCTIONAL DESCRIPTION 42 Basic Functions 42 System Bus Interf...

Page 8: ...terface 55 Boundary Scan Circuit 56 TAP FSM 56 Supported Instructions 56 Instruction Register and Decoding Logic 56 Boundary Scan Register BSR 56 Other Data Registers 56 Power Saving Modes 56 Power Do...

Page 9: ...cessor Interface Register PIR 80 MIR1 Power Up Clock Time 3 0 PUCT 81 MIR2 Power Down Length Count 7 0 PDLC 81 MIR3 Power Down Length Count 15 8 PDLC 81 MIR4 Power Down Length Count 22 16 PDLC 82 MIR5...

Page 10: ...R Pin Data 103 TIR30 Test Dummy Register 103 TIR31 TEST 103 TAI Configuration Register space TCR 103 TCR0 Network Configuration 104 TCR1 Transmit Configuration 104 TCR2 Clock Recovery 105 TCR3 Receive...

Page 11: ...0 and 3 3 V 130 ABSOLUTE MAXIMUM RATINGS 131 OPERATING RANGES 131 AC CHARACTERISTICS 131 5 0 and 3 3 V PCMCIA Interface AC Characteristics 131 PCMCIA MEMORY READ ACCESS 131 PCMCIA MEMORY WRITE ACCESS...

Page 12: ...ERFACE WAVEFORMS 154 IEEE 1149 1 INTERFACE WAVEFORMS 155 AC TEST REFERENCE WAVEFORMS 156 5 0 V PCMCIA AC Test Reference Waveform 156 3 3 V PCMCIA AC Test Reference Waveform 156 5 0 V NON PCMCIA AC Tes...

Page 13: ...D6 MD7 LLOCKE TXDATA TXCMD ANTSLT VDDU2 VDD5 AVDD ADREF AVSS ADIN2 ADIN1 PWRDWN ANTSLT TXMOD VSST TXPE FDET V SS TXCMD VDDT RXCIN RXSDATA RXPE TXDATA HFPE HFCLK LFPE LFCLK VSST TXC SAR6 SAR5 SAR4 SAR3...

Page 14: ...INPACK 86 TMS 122 RXPE 15 MA12 51 A3 87 TRST 123 RXDATA 16 VDDM 52 WAIT 88 TDI 124 RXCIN 17 VCC 53 A4 89 VCC 125 VDDT 18 MA7 54 A7 90 USER0 126 TXCMD 19 MA6 55 VDDP 91 USER1 127 VSS 20 MA5 56 A12 92...

Page 15: ...M 4 A8 65 MA12 15 SAR2 110 VDDM 16 A9 68 MA13 10 SAR3 111 VDDM 29 ACT 98 MA14 12 SAR4 112 VDDP 55 ADIN1 134 MA15 14 SAR5 113 VDDT 104 ADIN2 135 MA16 13 SAR6 114 VDDT 125 ADREF 137 MA2 24 SCE 39 VDDU1...

Page 16: ...ts PCMCIA or ISA Plug and Play mode I 1 PWRDWN Powerdown indicates that device is in the power down mode TP1 17 MA16 0 Memory Address Bus these lines are used to address locations in the Flash device...

Page 17: ...signal for the transceiver synthesizer TS1 2 ANTSLT ANTSLT Antenna Select used to select between two antennas PTS1 2 TXCMD TXCMD Transmit Command used to select the transmit path in the transceiver T...

Page 18: ...ol through TCR and TIR registers PTS3 PTS1 Name Type IOL IOH Load TP1 Totem pole 4 mA 4 mA 50 pF TS1 Tri state 4 mA 4 mA 50 pF TS2 Tri state 24 mA 4 mA 120 pF PTS1 User programmable tri state 4 mA 4 m...

Page 19: ...TXMOD TXDATA TXDATA RXPE TXPE HFPE HFCLK LFPE LFCLK FDET LNK ACT RXC IEEE 802 11 Network Interface Unit IEEE 802 11 MAC Control Unit 80188 core Bus Interface Unit ISA Plug and Play MOE MWE MA 16 0 MD...

Page 20: ...4 25 26 27 32 33 34 35 36 37 38 39 LA19 SA16 LA17 VDDM XCE MA11 VSSM MA9 MA8 MA13 MWE MA14 MA16 MA15 MA12 VDDM VCC MA7 MA6 MA5 VSSM MA4 MA3 MA2 MA1 MA0 MD0 MD1 VDDM MD2 MD3 VSSM MD4 MD5 MD6 MD7 SA15 L...

Page 21: ...50 LA22 86 TMS 122 RXPE 15 MA12 51 SA3 87 TRST 123 RXDATA 16 VDDM 52 IOCHRDY 88 TDI 124 RXCIN 17 VCC 53 SA4 89 VCC 125 VDDT 18 MA7 54 SA7 90 RFRSH 126 TXCMD 19 MA6 55 VDDP 91 IRQ12 127 VSS 20 MA5 56 S...

Page 22: ...TXPE 129 HFPE 120 MA9 8 SA6 60 VCC 17 IOCHRDY 52 MD0 27 SA7 54 VCC 89 IOR 67 MD1 28 SA8 65 VDD5 139 IOW 66 MD2 30 SA9 68 VDDM 4 IRQ10 94 MD3 31 SAR0 108 VDDM 16 IRQ11 92 MD4 33 SAR1 109 VDDM 29 IRQ12...

Page 23: ...based design TP1 8 MD7 0 Memory Data Bus these lines are used to write and read data to from Flash SRAM and or an extra peripheral device within an Am79C930 based design TS1 1 FCE Flash Chip Enable th...

Page 24: ...ver I 1 FDET Frame Detect start of frame delimiter detection indication TS1 1 RXCIN Receive Clock Input optional clock input that allows for an external PLL IPU 1 SDCLK Serial Data Clock clock output...

Page 25: ...100K SDSEL 2 pull up 100K SDSEL 1 pull up 100K ACT pull up 100K LNK pull up 100K TXMOD pull up 100K STSCHG BALE pull up 100K TXC pull up 100K Following the RESET operation the Am79C930 firm ware or d...

Page 26: ...tive low signal INPACK is asserted when the Am79C930 device is selected and the Am79C930 device can respond to an I O read cycle at the address currently on the address bus This signal is used by the...

Page 27: ...d in the Am79C930 device is only used for the PCMCIA WAKEUP indication The CHANGED bit and the SIGCHG bit of the Card Configuration and Status Register CCSR are not supported by the Am79C930 device Th...

Page 28: ...e 80188 and Transceiver Attachment Interface RFRSH Refresh Input The RFRSH signal is made active by the ISA host to in dicate that the current bus cycle is a refresh operation Memory Interface Pins MA...

Page 29: ...vice deliver the transmit data with a clock for reference In such systems the TXC pin may be configured as an output and the TXC signal will be generated by the Am79C930 device as a derivative from th...

Page 30: ...Data and FCS field The RXDATA input stream is expected to be NRZ data Clock recovery is per formed internal to the Am79C930 device If an external PLL is used for clock recovery then the RXDATA input w...

Page 31: ...Input Output ADIN 1 2 are inputs that accept single ended analog input values for conversion by the internal Am79C930 A D converter Only one input will be sampled at any time for conversion by the in...

Page 32: ...ntion should be paid to the printed circuit board layout to avoid excessive noise on the AVDD line AVSS Analog Ground 1 Pin Ground There is one analog ground pin This ground pin pro vides ground refer...

Page 33: ...83 In both 5 V and 3 V systems these pins should be con nected to a ground supply VDDM Memory Interface Power 3 Pins Power There are three Memory Interface power supply pins These pins provide power t...

Page 34: ...le USER4 USER4 PCMCIA USER4EN LA17 LA17 Pin TCR14 4 Pin Direction Pin Data 0 X I NA LA17 input function 1 0 I NA 1 1 O TIR29 4 Note that a read of the USERDT 4 bit TIR29 4 will al ways give the curren...

Page 35: ...the TX state machine provided that Am79C930 device firmware has enabled the operation by setting the TXS bit of TIR8 In addition to the functionality listed above the USER1 IRQ12 EXTCTS EXINT188 pin...

Page 36: ...pin value regard less of pin configuration setting USER6 USER6 PCMCIA ENXSDF USER6FN USER6EN IRQ Select IRQ Type IRQ5 IRQ5 Pin TCR28 6 TCR7 6 TCR15 3 PnPx70 PnPx71 Pin Direction Pin Data 0 1 X X X X...

Page 37: ...function as an input regardless of the settings of the other control bits listed USER5 USER5 PCMCIA ENXCHBSY USER5FN USER5EN IRQ Select IRQ Type IRQ4 IRQ4 Pin TCR28 5 TCR7 5 TCR15 2 PnPx70 PnPx71 Dire...

Page 38: ...1 TIR2 0 Direction Value 0 0 O LOW reset default condition 0 1 O HIGH 1 X I NA Pin 103 SDSEL3 The SDSEL 3 pin may be configured for input or output operation according to the following table Note that...

Page 39: ...eset default condition Pin 118 LFPE The LFPE pin may be configured for input or output op eration according to the table below Note that a read of the LFPE bit TIR0 1 will always yield the inverted lo...

Page 40: ...ay be configured to drive a trans ceiver control reference signal using input from the TXMOD bit of TIR11 TIR11 2 and the TXMODPOL bit of TCR27 according to the following table Transmit state machine...

Page 41: ...regardless of pin configuration setting TXCMD TXCMD PCMCIA RCEN TXCMFN TXCMEN LA21 Pin LA21 Pin Pin Value TIR11 3 TCR30 5 TCR15 5 Direction Value 0 X X X I NA LA21 input function 1 0 X X O O_TX 1 1 0...

Page 42: ...llows the user to define much of the pin functionality in order to assist in accom modating the Am79C930 device to a number of different network transceivers Pin control is achieved through Transceive...

Page 43: ...erface address bus are set according to the value of SIR1 4 3 The PCMCIA memory access control signals WE OE CE1 are automatically translated into the appropriate memory interface signals RD WR The PC...

Page 44: ...ytes 000h 3F0h i e the correspondence will occur when the device and bank select bits of SIR1 are pointing at the upper quadrant of the 128K Flash memory address space When accessing Am79C930 memory r...

Page 45: ...te addressing mode will alias the upper 96 Kbytes of Flash memory into the upper 96 Kbytes of SRAM space while preserving the location of the lower 32K of SRAM the XCE peripheral and the TAI BIU regis...

Page 46: ...sserted for the proper number of cycles and will cause the 80188 to experience the proper delay for the SRAM memory device in the Am79C930 based system 2 The 80188 firmware must perform a write to the...

Page 47: ...locations may be used for the PCMCIA CIS since these locations are mapped to Attribute Memory space when the PCMCIA mode of operation has been selected Note that the uppermost 16 bytes of Flash space...

Page 48: ...the desired antenna selection is accom plished through the setting of appropriate bits in one of the TIR registers TX FIFO The TAI contains individual FIFOs for RX and TX opera tions The TX FIFO hold...

Page 49: ...diagram are fixed with the values in dicated The CLKGT20 control bit is located in MIR9 7 The timing of the five internal signals can be applied to the external pins TXCMD TXPE and TXMOD in either of...

Page 50: ...he transmission of a frame For example the TIR9 bits indicate the number of bytes currently in the TX FIFO and whether or not the transmission is active Start of Frame Delimiter Detection Automatic St...

Page 51: ...after a programmable delay following an antenna diversity antenna switching operation The switching operation is periodic with the period being set with the Antenna Diversity Timer register of TCR4 Th...

Page 52: ...sment and in selecting an antenna The Baud Determination logic functions as follows Baud Determination testing is performed on a periodic basis where the period is determined by the Antenna Diversity...

Page 53: ...Stop Diversity Switching is unconditionally FALSE If the GOOD count exceeds the value of TCR20 then the GOOD count is compared against the value of the Baud Detect Ratio register TCR21 multiplied by...

Page 54: ...he combination of the test outcomes dictates a stop to di versity switching At such a point a satisfactory antenna has been found antenna switching will cease and the selected antenna will be used for...

Page 55: ...ome transceiver connections the signal TXC is de fined as a transceiver output The Am79C930 device can accommodate both types of transceivers by allow ing the TXC pin to be defined as either output or...

Page 56: ...s Bypass Scan Instruction Register and Decoding Logic After H_RESET or S_RESET the IDCODE instruction is always loaded into the IEEE 1149 1 register The de coding logic gives signals to control the da...

Page 57: ...cations either through the memory window or through SIR4 SIR5 SIR6 or SIR7 Note that a CIS READ operation will cause power down exit but will proceed normally If the Am79C930 device is operating in th...

Page 58: ...n cycle Software Access The Am79C930 device is directly driven by two pieces of software 1 the device driver which runs on the host machine s CPU performs transfers of data between the upper layers of...

Page 59: ...ith the Am79C930 device s CE1 signal ac tive This means that there is aliasing of addresses in I O space This decode function is unaffected by the setting of the SIR1 2 0 register bits PCMCIA Common M...

Page 60: ...o this portion of 80188 memory space 0420h 043Fh 000 32 bytes SRAM Memory 0 0420h 0 042Fh This SRAM space is inaccessible to the 80188 embedded core since the 80188 core maps the MIR registers of the...

Page 61: ...lly exist only in PCMCIA Attribute Memory space They are located at Attribute Memory locations 0800h and 0802h respectively The location of these registers is fixed Therefore the information pro gramm...

Page 62: ...ation Register the Bank Switching Se lect Register and the set of 32 TIR registers Addition ally all Am79C930 resources are accessible through I O accesses i e all memory structures are accessible thr...

Page 63: ...mory SIR6 I O Data SIR6 DPUM 06h XXX 1 byte Indirect access to Port 23 16 SRAM or Flash memory SIR7 I O Data SIR7 DPUU 07h XXX 1 byte Indirect access to Port 31 24 SRAM or Flash memory TIR 0 7 08h 0Fh...

Page 64: ...Plug and Play Memory Resources While the system memory space of the Am79C930 device only accommodates access to 32 Kbytes of memory the Am79C930 device uses device select and bank select bits in SIR1...

Page 65: ...core MBA 0400h 000 32 bytes SRAM Memory 0 0400h 0 041Fh MBA 041Fh This SRAM space is inaccessible to the 80188 embedded core since the 80188 core maps the 32 TIR registers of the TAI into this portion...

Page 66: ...henever the I O Data Port is read or written Whenever any of the I O Data Ports is accessed then the Local Memory Address Port value is automatically incremented by a value of 1 The next table indicat...

Page 67: ...3 16 to SRAM or Flash memory SIR7 I O Data Port 31 24 SIR7 DPUU IOBA 0007h XXX 1 byte Indirect access to SRAM or Flash memory TIR 0 7 IOBA 0008h 000 1 byte TAI IOBA 000Fh each location TIR 8 15 IOBA 0...

Page 68: ...appropriate Plug and Play Auto configuration port Set READ_DATA Auto configuration port The WRITE_DATA port and the READ_DATA port are not active until the Initiation Key has been sent to the Am79C930...

Page 69: ...0 device reset operation Status 05h BIU Card Select Number CSN 06h BIU Logical Device Number 07h BIU Unused 08h 2Fh NA Activate 30h BIU I O Range Check 31h BIU Unused 32h 3Fh NA Memory Base Address 0...

Page 70: ...internally When an access is performed without the presence of an active UCS signal then LCS is assumed and the access is exter nally directed toward the SRAM with the SCE signal or internally to the...

Page 71: ...LMCS register of the 80188 core be set to 07F8h or 0FF8h or 1FF8h The UMCS register of the 80188 core must be set to E038h Also required is that bit 6 of the MIR0 register the mapping select bit is se...

Page 72: ...Nested interrupt mode of the 80188 core no Interrupt Acknowledge cycles are generated instead the interrupt vector for each inter rupt is generated internally Internally generated interrupt vectors re...

Page 73: ...their default values by assertion of the RESET pin Note that some register locations default values are UNDEFINED All SIR registers except SIR2 7 0 and SIR3 6 0 which are unaffected All MIR registers...

Page 74: ...edded controller and TAI sections of the Am79C930 device along with a few locations in the MIR register space When the CORESET bit is asserted then the 80188 section of the Am79C930 device will be pla...

Page 75: ...t as asserting the RESET pin of the Am79C930 device except that as stated above the ISA PnP RESET is limited to a dura tion of 14 CLKIN periods SRES TIR0 5 The SRES bit of TIR0 5 can be used to reset...

Page 76: ...le through the system interface except that the Resource Data space is also mapped into a por tion of the 80188 core memory space Note that all register locations are defined to be 8 bits in width Som...

Page 77: ...down mode If the Am79C930 device is already in the power down mode when DISPWDN notes a transition from 0 to 1 then the power down mode will be exited within three CLKIN periods 4 ECWAIT 0 Embedded C...

Page 78: ...e SIDA bit of MIR0 bit 7 SIR1 Bank Switching Select Register BSS This register contains Bank Select bits for various Am79C930 resources and other control bits Bit Name Reset Value Description 7 ECATR...

Page 79: ...bit generates an inter rupt to the 80188 requesting that the 80188 core place the Am79C930 device into the power down state The interrupt is sig naled in MIR0 bit 5 The PWRDWN bit of SIR3 is identical...

Page 80: ...cription 7 SIDA 0 System Interface Direct Access When SIDA is set to 1 then the system interface side of the BIU is in direct memory access mode such that system interface access cycles will have dire...

Page 81: ...hat PWDNDN will read as a 0 after writing a 1 to PWDNDN but a 0 must still be written to PWDNDN in order to com plete the reset operation If a 0 is not written to PWDNDN then the PWDNDN will be perman...

Page 82: ...esolution of the power down length counter is in increments of PMX1 2 peri ods The nominal PMX1 2 crystal value is 32 768 kHz resulting in a resolution of 31 25 s MIR5 Free Count 7 0 FCNT This registe...

Page 83: ...ns TCR Mask STSCHG Data and SRAM Wait States Bit Name Reset Value Description 7 CLKGT20 1 CLKIN input is greater than 20 MHz This bit must be set to a 1 by the 80188 code whenever the Am79C930 device...

Page 84: ...device has priority over the current master i e worst case READY delay with HOSTLONGWAIT set to 0 is equal to 1 access performed by other master plus the number of wait states for the device being ac...

Page 85: ...tten as a 0 Reads of this bit produce undefined data MIR11 Reserved This register is reserved Bit Name Reset Value Description 7 0 Reserved Reserved Must be written as a 0 Reads of this bit produce un...

Page 86: ...I Configuration Registers TCR The following section describes the directly ac cessible registers of the TAI or TIR The set of 64 TAI registers is intended primarily for use by the 80188 firmware Howev...

Page 87: ...IOBA 000Ah mem 40Ah 11 Transmit Sequence Control 01 000Bh IOBA 000Bh mem 40Bh 12 Byte Counter LSB 01 000Ch IOBA 000Ch mem 40Ch 13 Byte Counter MSB 01 000Dh IOBA 000Dh mem 40Dh 14 Byte Counter Limit LS...

Page 88: ...mem 409h 10 TX FIFO Data XX 0012h mem 40Ah 11 Transmit Sequence Control XX 0013h mem 40Bh 12 Byte Counter LSB XX 0014h mem 40Ch 13 Byte Counter MSB XX 0015h mem 40Dh 14 Byte Counter Limit LSB XX 0016...

Page 89: ...The inverse of the RXP bit value is driven onto the RXPE pin when the RXPE pin has been enabled for output The value read from RXP will always represent the inverted logical sense of the current value...

Page 90: ...der bits of MA as DON T CARE i e a WRITE to TIR2 is occurring The value of the SDCLK pin during this strobe period depends upon the setting of the SDC bit The SDC bit gives the inactive state of the S...

Page 91: ...tA tA tA 2 X tA tA Figure 3 Serial Port Fast Read Timing Bit Name Reset Value Description 7 5 BCNT 2 0 Byte Count From 1 to 5 bits of the FSD 4 0 data may be sent dur ing one fast access to the serial...

Page 92: ...location has no ef fect on the bit value When the unmask bit for any interrupt is set to 0 then the bit in the Interrupt register may still become set but no interrupt to the 80188 em bedded controll...

Page 93: ...ontroller will occur Bit Name Reset Value Description 7 CHBSYCU 0 CHBSY Change Interrupt Unmask 6 ANTSWU 0 Antenna Switch Interrupt Unmask 5 MOREINTU 0 MOREINT Interrupt Unmask 4 TXCNTUN 0 TX Byte Cou...

Page 94: ...l automatically change immediately following the transmission of the last bit of the PFLth byte that follows the last bit of the Start of Frame Delimiter where PFL is defined in TCR3 bits 3 0 Since th...

Page 95: ...TX FIFO i e 8 spaces are available A TXFC value of 0h indicates a full TX FIFO i e 0 spaces are available 0 TXBSY 0 TX Busy This bit is set to 1 by the Am79C930 device when the transmit operation begi...

Page 96: ...2 the USER5FN bit TCR7 5 the ISA PnP registers 70h and 71h and the operating mode of the Am79C930 device The value read from USER5D will always represent the current value of the USER5 IRQ4 pin The c...

Page 97: ...0 BC 11 8 0h Byte Count Upper 4 bits of current byte count for both transmit and receive operations During transmit operations the byte count re flects the number of bytes that have been transmitted...

Page 98: ...internal Receive Reset signal is asserted When this bit is set to 0 the internal Receive Re set signal is deasserted The Receive FIFO is not reset by RXRES 6 RXFR 0 Receive FIFO Reset When this bit is...

Page 99: ...the network side of the receive FIFO Writes to this register should be for diagnostic purposes only and will not be necessary during nor mal operation RX FIFO write and read pointers are automatically...

Page 100: ...f the received message following the Start of Frame Delimiter If the value in this register and TIR22 does not match the length value indicated in the frame header plus overhead for PHY and MAC header...

Page 101: ...Control This register is the Antenna Diversity and A D Control register Bit Name Reset Value Description 7 CHBSY 0 Channel Busy The Am79C930 device will set this bit to a 1 when the clear channel ass...

Page 102: ...ay STRTC is intended for use only at times when the A D conversion process is not controlled by the antenna diversity logic That is whenever RXS 0 writing a 1 to STRTC will however initiate a conversi...

Page 103: ...and then driven out to the USER7 pin of the Am79C930 device when the system interface mode is PCMCIA and the USER7EN bit of TCR14 is set to ONE In all other cases the value of USR7DL will have no eff...

Page 104: ...he transmitter following the end of the dribbling bit period With respect to external transmit timing signals the value of DRB will determine the amount of time that passes from the sending of the las...

Page 105: ...y be written with any value The value writ ten to these bits will be returned when read The value of these bits will not affect device function 4 TXDI 0 Transmit Data Invert When set to a 1 the outgoi...

Page 106: ...eriods when the CLKGT20 bit of MIR9 is set to 1 TCR3 Receive Configuration This register is the Receive Configuration register CONFIGURATION REGISTER INDEX 03h Bit Name Reset Value Description 7 LOOPB...

Page 107: ...riod times 40 when the CLKGT20 bit of MIR9 is set to 1 When the value in this register is 00 then the di versity switching function is disabled TCR5 TX Ramp Up Timing This register is the TX Ramp Up T...

Page 108: ...resolution is 1 TCR7 Pin Data A This register is the Pin Data A register This register is used to deliver and retrieve data from the ANTSLT TXDATA and TXCMD pins and to configure the function of the...

Page 109: ...of the Am79C930 device based design should not include IRQ12 as a choice of IRQ level for possible se lection by the ISA Plug and Play configuration software When this procedure is followed then the...

Page 110: ...TCR9 Start Delimiter CSB This register is the Start Delimiter CSB register CONFIGURATION REGISTER INDEX 09h Bit Name Reset Value Description 7 0 SDLT 15 8 00h Start of Frame Delimiter This register co...

Page 111: ...the settings of the U1INTSC bits of TCR7 4 3 This function may be disabled with an appropriate setting of the U1INTSC bits A corre sponding unmask bit for this interrupt source exists in TCR12 2 RUNE...

Page 112: ...ntrol of the function of the SDSEL 2 pin is de scribed in the Multi Function Pin section 1 SDS1LEN 1 SDSEL1 Enable SDS1LEN is used to determine the function of the SDSEL1 pin The control of the functi...

Page 113: ...REGISTER INDEX 0Fh Bit Name Reset Value Description 7 ANTSLTLEN 0 ANTSLT Enable ANTSLTLEN the ANTSLTLFN bit of TCR30 the ANTSEN bit of TIR26 and the PCMCIA pin are used to determine the function of t...

Page 114: ...TSCHG pin is equal to the inver sion of the MIR9 STSCHGD bit value THIS FUNCTION IS ONLY AVAILABLE IN PCMCIA MODE The complete control of the function of the STSCHG BALE pin is described in the Multi...

Page 115: ...register The resolution of the value in this register is the period of the CLKIN signal when the CLKGT20 bit of MIR9 is set to 0 or twice the period of the CLKIN signal when the CLKGT20 bit of MIR9 is...

Page 116: ...rier sense The number of positive baud detect test results is reset to 0 each time that the antenna selection is changed TCR20 Baud Detect Accept Count for Stop Diversity This register is the Baud Det...

Page 117: ...a 5 0 ACPT 5 0 00h Accept 5 0 The value of these bits indicates the current number of good transitions detected by the baud detector This is a read only register TCR23 Baud Detect Fail Count This regi...

Page 118: ...CLKIN periods if CLKGT20 1 TCR25 RSSI Configuration This register is the RSSI Configuration register This register is used to setup some A D converter parameters CONFIGURATION REGISTER INDEX 19h Bit...

Page 119: ...qual to 20MHz with the CLKGT20 bit set to 0 Note that the actual time for conversion is less than the A2DT pro grammed value by 1 5 CLKIN periods with CLKGT20 0 it is 3 CLKIN periods if CLKGT20 1 This...

Page 120: ...of theACT pin will be open drain When set to a 1 the drive of the ACT pin will be totem pole i e both high and low output values will be driven Complete control of the function of the ACT pin is descr...

Page 121: ...n 5 ENXCHBSY 0 Enable External CHBSY When ENXCHBSY is set to a 1 then the internal CCA result is not used Instead the value of the USER5 IRQ4 pin is used as the source for CCA information When ENXCHBS...

Page 122: ...tion and Data Rate control register This register contains bits that control the function of the ANTSLT TXDATA TXCMD and TXC pins as well as control bits to set the network data rate CONFIGURATION REG...

Page 123: ...0 fCLKIN 200 110 0 fCLKIN 2000 111 0 reserved 000 1 fCLKIN 20 001 1 fCLKIN 40 010 1 fCLKIN 80 011 1 fCLKIN 160 100 1 reserved 101 1 fCLKIN 400 110 1 fCLKIN 4000 111 1 reserved The Data Rate bits are u...

Page 124: ...elReq 0 5 0 Conf Index 0 Configuration Index This field is written with the index number of the entry in the card s Configuration Table which the system chooses for this card When Conf Index 00000 the...

Page 125: ...IA CIS space has been allocated to reside in the flash memory space of a design based on the Am79C930 device This space corresponds to 1K 16 bytes of the uppermost 1K of flash memory Since only even a...

Page 126: ...Input LOW Voltage 0 8 V VIH Input HIGH Voltage 2 0 V VOL Output LOW Voltage IOL1 4 mA 0 45 V IOL2 12 mA 0 45 IOL3 24 mA 0 45 Note 1 5 VOH Output HIGH Voltage Note 2 IOH 4 mA Note 5 2 8 V VOLC Output L...

Page 127: ...ote 6 12 pF CCLK BCLK Pin Capacitance FC 1 MHz Note 6 12 pF Notes 1 IOL1 4mA applies to the following pins STSCHG PWRDWN MA 16 0 MD 7 0 FCE SCE XCE MOE MWE TDO LFPE LFCLK LLOCKE HFPE INPACK HFCLK ANTS...

Page 128: ...Units VIL Input LOW Voltage 0 3 0 8 V VIH Input HIGH Voltage 2 0 VDD 0 3 V VOL Output LOW Voltage IOL1 2 4 mA 0 4 V IOL2 12 mA 0 4 IOL3 8 mA 0 4 Note 1 5 VOH Output HIGH Voltage Note 2 IOH 0 4 mA Not...

Page 129: ...te 6 12 pF CCLK BCLK Pin Capacitance FC 1 MHz Note 6 12 pF Notes 1 IOL1 2 4mA applies to the following pins STSCHG PWRDWN MA 16 0 MD 7 0 FCE SCE XCE MOE MWE TDO LFPE LFCLK LLOCKE HFPE INPACK HFCLK ANT...

Page 130: ...C Devices Temperature TA 0 C to 70 C Supply Voltages VCC VDDT VDDU1 VDDU2 VDDM VDDP 5 V 5 or 3 0 V to 3 6 V Supply Voltages AVDD VDD5 5 V 5 Operating ranges define those limits between which the func...

Page 131: ...ns tELGL CE setup to OE 0 ns tGHEH CE hold from OE READ or CE hold from WE WRITE 20 ns tGLQV OE acess time Note 1 0 200 ns tGLWTV WAIT valid from OE 35 ns tWTLWTH WAIT pulse width Notes 2 3 53 X TCLKI...

Page 132: ...x value for this parameter assumes the following worst case situation Value Worst Case 0 FLASH and SRAM wait states set at 3 1 Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 8018...

Page 133: ...wing worst case situation Value Worst Case 0 FLASH and SRAM wait states set at 3 1 Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins instruction fetch cycle...

Page 134: ...performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins instruction fetch cycle to FLASH memory 2 PCMCIA WRITE cycle is posted internal to Am79C930 device pending the...

Page 135: ...ts is not implied Exposure to Absolute Maximum Ratings for extended periods may affect device reliability OPERATING RANGES Commercial C Devices Temperature TA 0 C to 70 C Supply Voltages VCC VDDT VDDU...

Page 136: ...valid hold from CMD Note 1 15 ns ti32 AEN valid setup to BALE 60 ns ti34 Data enabled from RCMD Notes 2 4 0 110 ns Notes 1 CMD one of MEMR MEMW IOR or IOW 2 RCMD one of MEMR or IOR 3 WCMD one of MEMW...

Page 137: ...ine those limits between which the func tionality of the device is guaranteed MEMORY BUS READ ACCESS Parameter Symbol Parameter Description Test Conditions Min Max Unit tmAD MA 16 0 valid from CLKIN 2...

Page 138: ...ime 0 wait states 95 ns Notes 1 3 1 wait state 145 ns 2 wait states 195 ns tmWP MWE Write Access Time 0 wait states 90 ns Note 3 1 wait state 140 ns 2 wait states 190 ns tmWQ MWE to MD 7 0 driven 10 n...

Page 139: ...those limits between which the func tionality of the device is guaranteed MEMORY BUS READ ACCESS Parameter Symbol Parameter Description Test Conditions Min Max Unit tmAD MA 16 0 valid from CLKIN 2 100...

Page 140: ...ime 0 wait states 160 ns Notes 1 3 1 wait state 260 ns 2 wait states 360 ns tmWP MWE Write Access Time 0 wait states 150 ns Note 3 1 wait state 250 ns 2 wait states 350 ns tmWQ MWE to MD 7 0 driven 10...

Page 141: ...s not implied Exposure to Absolute Maximum Ratings for extended periods may affect device reliability OPERATING RANGES Commercial C Devices Temperature TA 0 C to 70 C Supply Voltages VCC VDDT VDDU1 VD...

Page 142: ...240 ns TRXHL RXC Fall time Note 8 10 ns TRXLH RXC Rise time Note 8 10 ns TTXC TXC Period Notes 1 5 7 500 ns TCLTX TXC Low time Notes 1 5 7 245 ns TCHTX TXC High time Notes 1 5 7 245 ns TTXHL TXC Fall...

Page 143: ...se with CLKP 0 TCR2 4 0 For nonzero values of CLKP use the following formulas If CLKGT20 0 MIR9 7 tRXDSmin 110 CLKP X TCLKIN tRXDHmin 10 CLKP X TCLKIN If CLKGT20 1 MIR9 7 tRXDSmin 110 CLKP X TCLKIN X...

Page 144: ...s not implied Exposure to Absolute Maximum Ratings for extended periods may affect device reliability OPERATING RANGES Commercial C Devices Temperature TA 0 C to 70 C Supply Voltages VCC VDDT VDDU1 VD...

Page 145: ...tup time to TXC Notes 2 4 TCLTX 165 ns tTXDH TXD hold time from TXC Notes 2 4 TCHTX ns tTXDV TXD delay from TXC Notes 2 3 0 150 ns Notes 1 Only applicable when TXC has been configured as an INPUT 2 On...

Page 146: ...ercial C Devices Temperature TA 0 C to 70 C Supply Voltages VCC VDDT VDDU1 VDDU2 VDDM VDDP 3 0 V to 5 25 V Supply Voltages AVDD VDD5 5 V 5 All inputs within the range VSS 0 5 V VIN VDD 0 1 X VDD where...

Page 147: ...ce pins for a given input pin See section on power supply pin descriptions CL 50 pF unless otherwise noted Operating ranges define those limits between which the func tionality of the device is guaran...

Page 148: ...GHAX tGHQZ WE high WAIT tELGL tAVGL tGHEH tGLWTV tWTLWTH tQVWTH 20138B 10 Figure 4 PCMCIA MEMORY READ Access Timing Diagram An REG CE WE Di Din tELWH tWLWH tWMDX WAIT tELWL tAVWL tWHGL tWLWTV tWTLWTH...

Page 149: ...L tIGLIGH tIGLWTL tWTLWTH tIGHEH tWTHQV tIGHQX tIGLQV INPACK tIGLIAL tIGHIAH tIGHQZ tIGQNZ Figure 6 PCMCIA I O READ Access Timing Diagram An REG IOWR Di Din WAIT tAVIWL CE tIWHRGH tRGLIWL tIWHAX tELIW...

Page 150: ...ce Waveforms 20138B 14 CMD one of MEMR MEMW IOR IOW LAn CMD SDout read ti1 ti8 ti34 ti3 ti14 IOCHRDY ti7 ti4 ti20 AEN BALE SAn ti2 ti10 SDin write ti11 ti12 ti13 ti15 ti21 ti22 ti23 ti25 ti26 ti30 ti3...

Page 151: ...this point valid tmRI tmRDHC tmAD tmCD tmOD tmOLZ tmHZ CLKOUT internal tmCD tmOD tmAH tmCH Figure 9 Memory Bus READ Access Timing Diagram 20138B 16 MAn FCE SCE XCE MOE MDo Dout tmAW tmWP tmAD MWE high...

Page 152: ...152 Am79C930 CLOCK WAVEFORMS 20138B 17 CLKIN 0 8 V 2 0 V tCLIN tINHL tCLKIN tINLH tCHIN 0 8 V TXC 0 8 V 2 0 V tCLTX tTXHL tTXC tTXLH tCHTX 0 8 V RXC 0 8 V 2 0 V tCLRX tRXHL tRXC tRXLH tCHRX 0 8 V Figu...

Page 153: ...RMS 20138B 18 ICO Internally Controlled Output ICO RCO RCO tn1 CLKIN CLKOUT internal tn2 RCO tn3 tn4 Figure 12 TAI Timing Diagram 20138B 19 RXD tRXDS RXC tRXDS TXD tTXDD TXC input TXD tTXDV TXC output...

Page 154: ...Am79C930 PROGRAMMABLE INTERFACE WAVEFORMS 20138B 20 RCO Register Controlled Output WAIT or IOCHRDY RCO data change CLKOUT internal RCO drive change tu1 tu2 RCO drive change tu3 CLKIN Figure 14 Program...

Page 155: ...P R E L I M I N A R Y AMD 155 Am79C930 IEEE 1149 1 INTERFACE WAVEFORMS 20138B 21 TCK TDI TMS TDO t31 Output Signals t25 t30 t32 t34 t37 t36 Input Signals t35 Figure 15 IEEE 1149 1 Timing Diagram...

Page 156: ...0 V 20138B 22 output measured parameter value input 2 4 0 8 2 8 0 5 2 4 0 8 2 8 0 5 Figure 16 5 0 V PCMCIA AC Test Reference Waveform 3 3 V PCMCIA AC Test Reference Waveform This waveform indicates th...

Page 157: ...measured parameter value input 2 0 0 8 2 4 0 45 2 0 0 8 2 4 0 45 Figure 18 5 0 V Non PCMCIA AC Test Reference Waveform 3 3 V NON PCMCIA AC TEST REFERENCE WAVEFORM This waveform indicates the AC testi...

Page 158: ...7 0 27 16 038 PQT 2_AH PQT144 5 4 95 ae For reference only BSC is an ANSI standard for Basic Space Centering Trademarks Copyright 1997 Advanced Micro Devices Inc All rights reserved AMD the AMD logo a...

Page 159: ...wer up and system configuration information either PCMCIA CIS or ISA Plug and Play Resource Data that is also stored in the Flash device before power up Note The Am79C930 device allows an uninitialize...

Page 160: ...g intervals as specified in the IEEE 802 11 draft and the Xircom Netwave stan dards the Am79C930 80188 core will write the transmit command to the TAI and the TAI will begin sending the transmit data...

Page 161: ...eIMR GigaPHY HIMIB ILACC IMR IMR IMR2 ISA HUB MACE Magic Packet PCnet PCnet FAST PCnet FAST PCnet Mobile QFEX QFEXr QuASI QuEST QuIET TAXIchip TPEX and TPEX Plus are trademarks of Advanced Micro Devic...

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Summary of Contents for Am79C930

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AMD Am79C930, Preliminary Manual, Page: 12 / 161

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Summary of Contents for Am79C930

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