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Interrupt Control Unit

7-32

7.4.6

In-Service Register (INSERV, Offset 2Ch)
(Slave Mode)

The format of the In-Service register is shown in Figure 7-22. The bits in the In-Service
register are set by the interrupt controller when the interrupt is taken. The in-service bits
are cleared by writing to the End-of-Interrupt (EOI) register.

Figure 7-22

In-Service Register (INSERV, offset 2Ch)

The INSERV register is set to 0000h on reset.

Bits 15–6: Reserved

Bits 5–4: Timer 2/Timer 1 Interrupt In-Service (TMR2–TMR1)—When set to 1, these bits
indicate that the corresponding timer interrupt is currently being serviced.

Bits 3–2: DMA Channel Interrupt In-Service (D1–D0)—When set to 1, the corresponding
DMA channel is currently being serviced.

Bit 1: Reserved

Bit 0: Timer 0 Interrupt In-Service (TMR0)—When set to 1, this bit indicates Timer 0 is
currently being serviced.

15

7

0

Reserved

D0

D1

TMR1

TMR2

Res

TMR0

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Summary of Contents for AM186EM

Page 1: ...Am186 EM and Am188 EM Microcontrollers User s Manual...

Page 2: ...esentations or warranties of any kind including but not limited to any implied warranty of merchantability or fitness for a particular purpose AMD products are not authorized for use as critical compo...

Page 3: ...ine 800 222 9323 toll free for U S and Canada 44 0 1276 803 299 U K and Europe hotline World Wide Web Home Page and FTP Site To access the AMD home page go to http www amd com To download documents an...

Page 4: ...iv...

Page 5: ...4 2 5 SEGMENTS 2 8 2 6 DATA TYPES 2 8 2 7 ADDRESSING MODES 2 10 CHAPTER 3 SYSTEM OVERVIEW 3 1 PIN DESCRIPTIONS 3 1 3 1 1 Pins That Are Used by Emulators 3 15 3 2 BUS OPERATION 3 16 3 3 BUS INTERFACE U...

Page 6: ...7 10 7 2 3 Special Fully Nested Mode 7 11 7 2 4 Operation in a Polled Environment 7 11 7 2 5 End of Interrupt Write to the EOI Register 7 11 7 3 MASTER MODE INTERRUPT CONTROLLER REGISTERS 7 12 7 3 1...

Page 7: ...nt Compare Registers T0CMPA Offset 52h T0CMPB Offset 54h T1CMPA Offset 5Ah T1CMPB Offset 5Ch T2CMPA Offset 62h 8 7 CHAPTER 9 DMA CONTROLLER 9 1 OVERVIEW 9 1 9 2 DMA OPERATION 9 1 9 3 PROGRAMMABLE DMA...

Page 8: ...4 Synchronous Serial Receive Register SSR Offset 18h 11 6 11 3 SSI PROGRAMMING 11 7 CHAPTER 12 PROGRAMMABLE I O PINS 12 1 OVERVIEW 12 1 12 2 PIO MODE REGISTERS 12 3 12 2 1 PIO Mode 1 Register PIOMODE...

Page 9: ...er 5 10 Figure 5 5 Peripheral Chip Select Register 5 12 Figure 6 1 Memory Partition Register 6 1 Figure 6 2 Clock Prescaler Register 6 2 Figure 6 3 Enable RCU Register 6 2 Figure 6 4 Watchdog Timer Co...

Page 10: ...nation Synchronized DMA Transfers 9 13 Figure 10 10 DCE DTE Protocol 10 2 Figure 10 11 CTS RTR Protocol 10 3 Figure 10 1 Serial Port Control Register 10 5 Figure 10 2 Serial Port 0 1 Status Register 1...

Page 11: ...0 Wait State Encoding 5 13 Table 6 7 Watchdog Timer COUNT Settings 6 4 Table 6 8 Watchdog Timer Duration 6 4 Table 7 1 Am186ES and Am188ES Microcontroller Interrupt Types 7 4 Table 7 2 Interrupt Contr...

Page 12: ...Table of Contents xii...

Page 13: ...ith the internal processor clock The Am186EM and Am188EM microcontrollers are available in versions operating at 20 25 33 and 40 MHz PURPOSE OF THIS MANUAL This manual describes the technical features...

Page 14: ...ics and waveforms connection diagrams and pinouts and package physical dimensions 21267 Am186 and Am188 Family Instruction Set Manual Providesadetaileddescriptionandexamplesforeachinstructionincludedi...

Page 15: ...r higher performance and more integration than the 80C186 188 core microcontrollers Upgrading to the Am186EM or Am188EM microcontrollers is attractive for the following reasons n Minimized total syste...

Page 16: ...ide faster access to memory Phase locked loop PLL allows processor to operate at the clock input frequency Nonmultiplexed address bus n New integrated peripherals increase functionality while reducing...

Page 17: ...rs 20 Bit Destination Pointers 20 Bit Source Pointers Control Registers Control Registers Control Registers 0 1 WDT 2 0 1 Max Count B Registers Refresh Control Unit Control Registers Control Registers...

Page 18: ...20 Bit Destination Pointers 20 Bit Source Pointers Control Registers Control Registers Control Registers 0 1 WDT 2 0 1 Max Count B Registers Refresh Control Unit Control Registers Control Registers C...

Page 19: ...the BHE ADEN and RFSH2 ADEN pin descriptions in Chapter 3 and see section 5 5 1 and section 5 5 2 for additional information regarding the AD15 AD0 address enabling and disabling Figure 1 3 illustrate...

Page 20: ...e SRAM Write Enable WE input pins The design uses 2 Mbit 256 Kbyte memory technology to fully populate the available address space Two Flash PROM devices provide 512 Kbytes of nonvolatile program stor...

Page 21: ...ar locations within a segment The addressing modeselectsthespecificregisters for operandandaddress calculations Stack Pointer Register All stack operations POP POPA POPF PUSH PUSHA PUSHF utilize the s...

Page 22: ...er F Bits 15 12 Reserved Bit 11 Overflow Flag OF Set if the signed result cannot be expressed within the number of bits in the destination operand cleared otherwise Bit 10 Direction Flag DF Causes str...

Page 23: ...sts of a 16 bit segment value and a 16 bit offset The offset is the number of bytes from the beginning of the segment the segment address to the data or instruction that is being accessed The processo...

Page 24: ...member of the Am186 and Am188 family of microcontrollers including the Am186EM and Am188EM share the standard 186 instruction set An instruction can reference from zero to several operands An operand...

Page 25: ...C Complement carry flag CMP Compare byte or word CMPS Compare byte or word string CWD Convert word to doubleword DAA Decimal adjust for addition DAS Decimal adjust for subtraction DEC Decrement byte o...

Page 26: ...erflow JNP JPO Jump if not parity parity odd JNS Jump if not sign JO Jump if overflow JP JPE Jump if parity parity even JS Jump if sign LAHF Load AH register from flags LDS Load pointer using DS LEA L...

Page 27: ...Return from procedure ROL Rotate left byte or word ROR Rotate right byte or word SAHF Store AH register in flags SF ZF AF PF and CF SAL Shift left arithmetic byte or word SAR Shift right arithmetic b...

Page 28: ...on is implied by the addressing mode used see Table 2 1 Table 2 1 Segment Register Selection Rules 2 6 DATA TYPES The Am186EM and Am188EM microcontrollers directly support the following data types n I...

Page 29: ...5 Supported Data Types 7 0 Signed Byte Magnitude Magnitude 7 0 MSB Unsigned Byte Signed Word Magnitude MSB 1 0 Magnitude MSB 3 2 1 0 Signed Quad Word Magnitude MSB 63 48 47 32 31 16 15 0 Unsigned Wor...

Page 30: ...egisters 3 Index contents of either the SI or DI index registers Any carry from the 16 bit addition is ignored Eight bit displacements are sign extended to 16 bit values Combinations of the above thre...

Page 31: ...AD15 AD0 on the Am186EM or AO15 AO8 and AD7 AD0 on the Am188EM During a bus hold or reset condition the address bus is in a high impedance state AD7 AD0 Address and Data Bus input output three state...

Page 32: ...igh order address bits from bus cycles t1 t4 These outputs are floated during a bus hold or reset On the Am188EM microcontroller AO15 AO8 combine with AD7 AD0 to form a complete multiplexed address bu...

Page 33: ...al to determine refresh cycles PSRAM refreshes also provide an additional RFSH signal see the MCS3 RFSH pin description ADEN If BHE ADEN is held High or left floating during power on reset the address...

Page 34: ...eset condition GND Ground These pins connect the system ground to the microcontroller HLDA Bus Hold Acknowledge output synchronous This pin is asserted High to indicate to an external bus master that...

Page 35: ...microcontroller interrupt vector table Interrupt requests are synchro nized internally and can be edge triggered or level triggered To guar antee the interrupt is recognized the device issuing the re...

Page 36: ...external master interrupt controller INT4 Maskable Interrupt Request 4 input asynchronous This pin indicates to the microcontroller that an interrupt request has occurred If the INT4 pin is not maske...

Page 37: ...be masked The microcontroller always transfers program execution to the location specified by the nonmaskable interrupt vector in the microcontroller interrupt vector table when NMI is asserted Altho...

Page 38: ...Select 6 output synchronous Latched Address Bit 2 output synchronous PCS6 This pin indicates to the system that a memory access is in progress to the seventh region of the peripheral memory block eit...

Page 39: ...t Status 0 TMRIN1 Input with pullup 1 TMROUT1 Input with pulldown 2 PCS6 A2 Input with pullup 3 PCS5 A1 Input with pullup 4 DT R Normal operation 3 5 DEN Normal operation 3 6 SRDY Normal operation 4 7...

Page 40: ...0 12 Input with pullup DRQ1 13 Input with pullup DT R 4 Normal operation 3 INT2 31 Input with pullup INT4 30 Input with pullup MCS0 14 Input with pullup MCS1 15 Input with pullup MCS2 24 Input with pu...

Page 41: ...serted Low to signify a DRAM refresh bus cycle The use of RFSH2 ADEN to signal a refresh is not valid when PSRAM mode is selected Instead the MCS3 RFSH signal is provided to the PSRAM ADEN If RFSH2 AD...

Page 42: ...ions to be synchronized between the microcontroller and the slave SCLK is derived from the microcontroller internal clock and then divided by 2 4 8 or 16 depending on register settings An access to an...

Page 43: ...le duty cycle TMROUT0 is floated during a bus hold or reset TMROUT1 Timer Output 1 output synchronous This pin supplies to the system either a single pulse or a continuous waveform with a programmable...

Page 44: ...ce logic and external address latch that were required are eliminated WHB is asserted with AD15 AD8 WHB is the logical OR of BHE and WR This pin floats during reset WLB WB Write Low Byte Am186EM Micro...

Page 45: ...tal used by the internal oscillator circuit To provide the microcontroller with an external clock source leave the X2 pin unconnected and connect the source to the X1 pin 3 1 1 Pins That Are Used by E...

Page 46: ...er the address is driven on A015 A08 during the data portion of the bus cycle regardless of the setting of the DA bits If the ADEN pin is pulled Low during processor reset the value of the DA bits in...

Page 47: ...ocontroller Read and Write with Address Bus Disable In Effect CLKOUTA t1 t2 t3 t4 AD15 AD0 Read Data AD15 AD0 Write LCS or UCS Address Data Address Address Phase Data Phase A19 A0 Address MCSx PCSx CL...

Page 48: ...ead and Write with Address Bus Disable In Effect CLKOUTA t1 t2 t3 t4 AD7 AD0 Read Data AO15 AO8 Read or Write AD7 AD0 Write Address Address Data Address Address Phase Data Phase A19 A0 Address LCS or...

Page 49: ...AD0 WHB is the logical OR of BHE and WR WHB is Low when both BHE and WR are Low WLB is the logical OR of AD0 and WR WLB is Low when both AD0 and WR are both Low TheAm188EM microcontrollerprovides one...

Page 50: ...ntroller CLKOUTA is the same frequency as the crystal The PLL takes the crystal inputs X1 and X2 and generates a 45 55 worst case duty cycle intermediate system clock of the same frequency This featur...

Page 51: ...lifier thesevalues need to be offset with the larger load on the output X2 Equal values of these loads tend to balance the poles of the inverting amplifier The characteristics of the inverting amplifi...

Page 52: ...cy and another clock run at the power save frequency Individual drive enable bits allow selective enabling of just one or both of these clock outputs 3 4 5 Power Save Operation The power save mode red...

Page 53: ...de written in this manner will run correctly on the Am188EM microcontroller and on the Am186EM microcontroller Unaligned reads and writes to the PCB result in unpredictable behavior on both the Am186E...

Page 54: ...egister DMA 1 Transfer Count Register DMA 1 Destination Address Low Register DMA 1 Source Address High Register DMA 1 Source Address Low Register DMA 0 Control Register DMA 0 Transfer Count Register D...

Page 55: ...s in offset addresses indicate reserved registers 5C 5E 60 62 66 50 52 54 56 58 5A Timer 2 Mode Control Register Timer 2 Maxcount Compare A Register Timer 2 Count Register Timer 1 Mode Control Registe...

Page 56: ...elocation information for the control block the RELREG register contains a bit that places the interrupt controller into either slave mode or master mode At reset the RELREG register is set to 20FFh w...

Page 57: ...dress data bus during reset For example the RESCON register could be used to provide the software with the position of a configuration switch in the system Using weak external pullup and pulldown resi...

Page 58: ...RL register are listed in Table 4 1 Bits 15 8 Processor Release Level PRL This field is an 8 bit read only identification number that specifies the processor release level The values of the PRL field...

Page 59: ...the clock divisor Set to 0 on reset CLKOUTB can be used as a full speed clock source in power save mode Bit 10 CLKOUTB Drive Disable CBD When set to 1 CBD three states the clock output driver for CLK...

Page 60: ...e initialization RES forces the Am186EM and Am188EM microcontrollers to terminate all execution and local bus activity No instruction or bus activity occurs as long as RES is active After RES is deass...

Page 61: ...O Mode 1 PIOMODE1 0000h PIO Direction 0 PIODIR0 FC0Fh PIO Mode 0 PIOMODE0 0000h Serial Port Interrupt Control SPICON 001Fh Serial port interrupt masked priority 7 Watchdog Timer Interrupt Control WDCO...

Page 62: ...Peripheral Control Block 4 10...

Page 63: ...used to program the Upper Memory Chip Select UCS The LMCS register offset A2h is used to program the Lower Memory Chip Select LCS The Midrange Memory Chip Selects MCS3 MCS0 are programmed through the...

Page 64: ...ates to three wait states can be inserted for all other chip selects Each of the chip select control registers other than the PACS register UMCS LMCS MMCS and MPCS contains a two bit field R1 R0 whose...

Page 65: ...gnals must agree with the programming for any other chip selects with which their assertion would overlap if they were configured as chip selects Although the PCS4 signal is not available on an extern...

Page 66: ...ister UMCS offset A0h The value of the UMCS register at reset is F03Bh Bit 15 Reserved Set to 1 Bits 14 12 Lower Boundary LB2 LB0 The LB2 LB0 bits define the lower bound of the memory accessed through...

Page 67: ...This configures AD15 AD0 to be enabled regardless of the setting of DA If BHE ADEN on the Am186EM or RFSH2 ADEN on the Am188EM is High on the rising edge of RES then DA in the Upper Memory Chip Select...

Page 68: ...ecause of the timing requirements of the LCS output and the nonmultiplexed address bus the number of programmable memory sizes for the LMCS register is reduced compared to the 80C186 and 80C188 microc...

Page 69: ...Am186EM or RFSH2 ADEN on the Am188EM is High on the rising edge of RES then the DA bit in the UMCS register and the DA bit in the LMCS register control the AD15 AD0 disabling See the descriptions of...

Page 70: ...for a half cycle later than that for UCS and LCS The Midrange Memory Chip Selects are configured by the MMCS register Figure 5 3 Figure 5 3 Midrange Memory Chip Select Register MMCS offset A6h The va...

Page 71: ...y is required If R2 is set to 1 external ready is ignored In each case the processor also uses the value of the R1 R0 bits to determine the number of wait states to insert Bits 1 0 Wait State Value R1...

Page 72: ...ot active If PCS6 PCS5 are configured as address pins an access to the MPCS register causes the pins to activate No corresponding access to the PACS register is required to activate the PCS6 PCS5 pins...

Page 73: ...PCS outputs are active for memory bus cycles When MS is set to 0 the PCS outputs are active for I O bus cycles Bits 5 3 Reserved Set to 1 Bit 2 Ready Mode R2 This bit applies only to the PCS6 PCS5 ch...

Page 74: ...the PCS6 PCS5 pins are chip selects the MPCS register also determines whether PCS chip selects are active during memory or I O bus cycles and specifies the ready and wait states for the PCS6 PCS5 outp...

Page 75: ...set to 1 In each case the processor also uses the value of the R3 and R1 R0 bits to determine the number of wait states to insert The ready mode for PCS6 PCS5 is configured through the MPCS register...

Page 76: ...Chip Select Unit 5 14...

Page 77: ...dition then the microcontroller deactivates the HLDA pin in order to perform a refresh cycle The circuit external bus master must remove the HOLD signal for at least one clock to allow the refresh cyc...

Page 78: ...power save mode the refresh counter value must be adjusted to take into account the reduced processor clock rate 6 1 3 Enable RCU Register EDRAM Offset E4h Figure 6 3 Enable RCU Register EDRAM offset...

Page 79: ...The INT4 INT0 interrupt request pins can be used as direct interrupt requests If more inputs are needed INT3 INT0 can also be cascaded with an 82C59A compatible external interrupt control device An e...

Page 80: ...t an interrupt could occur while the register is in an undefined state This can cause interrupts to be accepted even though they were masked both before and after the write to the Interrupt Mask regis...

Page 81: ...Am186EM 4 All three timers constitute one source of request to the interrupt controller As such they share the same priority level with respect to other interrupt sources However the timers have a de...

Page 82: ...shifted left 2 bit positions multiplied by 4 to generate the index into the interrupt vector table 7 1 2 4 Interrupt Servicing A valid interrupt transfers execution to a new program location based on...

Page 83: ...ardware Interrupt Priority Beginning with interrupt type 8 the Timer 0 interrupt the maskable hardware interrupts have both an overall priority see Table 7 1 and a programmable priority The programmab...

Page 84: ...d regardless of the state of the IF interrupt enable flag bit No external interrupt acknowledge sequence is performed for an NMI interrupt see section 7 1 5 A typical use of NMI is to activate a power...

Page 85: ...s supplying the interrupt type the processor generates two interrupt acknowledge bus cycles see Figure 7 1 The interrupt type is written to the AD7 AD0 lines by the external interrupt controller durin...

Page 86: ...et to 1 This places all sources at the lowest priority level 7 3 All level triggered mode LTM bits are reset to 0 resulting in edge triggered mode 4 All interrupt in service bits are reset to 0 5 All...

Page 87: ...registers The modes of interrupt controller operation are fully nested mode cascade mode special fully nested mode and polled mode 7 2 1 Fully Nested Mode In fully nested mode five pins are used as d...

Page 88: ...mode INT0 is an interrupt input interfaced to one 82C59A and INT2 INTA0 serves as the dedicated interrupt acknowledge signal to that peripheral INT1 and INT3 INTA1 are also interfaced to an 82C59A Eac...

Page 89: ...register information without setting the indicated in service bit the Am186EM and Am188EM microcontrollers provide a Poll Status register Figure 7 15 in addition to the Poll register Poll register in...

Page 90: ...ster Mnemonic Register Name Associated Pins Comments 3Ah I1CON INT1 Control INT1 38h I0CON INT0 Control INT0 3Eh I3CON INT3 Control INT3 3Ch I2CON INT2 Control INT2 40h I4CON INT4 Control INT4 36h DMA...

Page 91: ...it enables cascade mode Bit 4 Level Triggered Mode LTM This bit determines whether the microcontroller interprets an INT0 or INT1 interrupt request as edge or level sensitive A 1 in this bit configure...

Page 92: ...Interrupt Control Unit 7 14 Table 7 3 Priority Level Priority PR2 PR0 High 0 0 0 0b 1 0 0 1b 2 0 1 0b 3 0 1 1b 4 1 0 0b 5 1 0 1b 6 1 1 0b Low 7 1 1 1b...

Page 93: ...t as edge or level sensitive A 1 in this bit configures INT2 or INT3 as an active High level sensitive interrupt A 0 in this bit configures INT2 or INT3 as a Low to High edge triggered interrupt In ei...

Page 94: ...s bit determines whether the microcontroller interprets an INT4 interrupt request as edge or level sensitive A 1 in this bit configures INT4 as an active High level sensitive interrupt A 0 in this bit...

Page 95: ...Interrupt Control Registers TCUCON DMA0CON DMA1CON offsets 32h 34h and 36h The value of TCUCON DMA0CON and DMA1CON at reset is 000Fh Bits 15 4 Reserved Set to 0 Bit 3 Interrupt Mask MSK This bit deter...

Page 96: ...program the interrupt pin Figure 7 8 Watchdog Timer Interrupt Control Register WDCON offset 42h The value of WDCON at reset is 000Fh Bits 15 5 Reserved Set to 0 Bit 4 Reserved Must be set to 0 to ens...

Page 97: ...of SPICON at reset is 001Fh Bits 15 5 Reserved Set to 0 Bit 4 Reserved Set to 1 Bit 3 Mask MSK This bit determines whether the serial port can cause an interrupt A 1 in this bit masks this interrupt...

Page 98: ...IRET instruction is executed Time critical software such as interrupt handlers can modify this bit directly to inhibit DMA transfers Because of the function of this register as an interrupt request re...

Page 99: ...Figure 7 11 Interrupt Request Register REQST offset 2Eh The REQST register is undefined on reset Bits 15 11 Reserved Bit 10 Serial Port Interrupt Request SPI This bit indicates the interrupt state of...

Page 100: ...ows the INT1 INT0 requests to circumvent this restriction for the INT0 and INT1 sources Figure 7 12 In Service Register INSERV offset 2Ch The INSERV register is set to 0000h on reset Bits 15 11 Reserv...

Page 101: ...t is required in order for a maskable interrupt source to generate an interrupt Maskable interrupts with programmable priority values that are numerically higher than this field are masked The possibl...

Page 102: ...ual interrupt control registers Figure 7 14 Interrupt Mask Register IMASK offset 28h The IMASK register is set to 07FDh on reset Bits 15 11 Reserved Bit 10 Serial Port Interrupt Mask SPI When set to 1...

Page 103: ...ePoll register is read the current interrupt is acknowledged and the next interrupt takes its place in the Poll register Figure 7 15 Poll Status Register POLLST offset 26h Bit 15 Interrupt Request IRE...

Page 104: ...r POLL offset 24h Bit 15 Interrupt Request IREQ Set to 1 if an interrupt is pending When this bit is set to 1 the S4 S0 field contains valid data Bits 14 5 Reserved Set to 0 Bits 4 0 Poll Status S4 S0...

Page 105: ...shows example code for a specific EOI reset See Table 7 1 on page 7 3 for specific EOI values Figure 7 17 Example EOI Assembly Code Figure 7 18 End of Interrupt Register EOI offset 22h Bit15 Non Speci...

Page 106: ...terrupt controller operation The programmer must assign correct priorities and initialize interrupt control registers before enabling interrupts 7 4 1 Slave Mode Interrupt Nesting Slave mode operation...

Page 107: ...rs T0INTCON T1INTCON T2INTCON DMA0CON DMA1CON offsets 32h 38h 3Ah 34h and 36h These registers are set to 000Fh on reset Bits 15 4 Reserved Set to 0 Bit 3 Mask MSK This bit determines whether the inter...

Page 108: ...gure 7 20 Interrupt Status Register INTSTS offset 30h The INTSTS register is set to 0000h on reset Bit 15 DMA Halt DHLT When set to 1 halts any DMA activity Automatically set to 1 when non maskable in...

Page 109: ...uests an interrupt The bit is reset during the internally generated interrupt acknowledge Figure 7 21 Interrupt Request Register REQST offset 2Eh The REQST register is set to 0000h on reset Bits 15 6...

Page 110: ...Service Register INSERV offset 2Ch The INSERV register is set to 0000h on reset Bits 15 6 Reserved Bits 5 4 Timer 2 Timer 1 Interrupt In Service TMR2 TMR1 When set to 1 these bits indicate that the co...

Page 111: ...set is 0007h Bits 15 3 Reserved Bits 2 0 Priority Field Mask PRM2 PRM0 This field determines the minimum priority which is required in order for a maskable interrupt source to generate an interrupt A...

Page 112: ...n reset Bits 15 6 Reserved Bits 5 4 Timer 2 Timer 1 Interrupt Mask TMR2 TMR1 These bits indicate the state of the mask bit of the Timer Interrupt Control register and when set to a 1 indicate which so...

Page 113: ...The command is executed by writing the correct value in the Specific EOI register at offset 22h Figure 7 25 Specific End of Interrupt Register EOI offset 22h The EOI register is undefined on reset Bit...

Page 114: ...the interrupt vector table Figure 7 26 Interrupt Vector Register INTVEC offset 20h The INTVEC register is undefined on reset Bits 15 8 Reserved Read as 0 Bits 7 3 Interrupt Type T4 T0 Sets the five mo...

Page 115: ...code crashes or hangs the TIMER1 countdown can cause a watchdog interrupt Timer 2 is not connected to any external pins It can be used for real time coding and time delay applications It can also be...

Page 116: ...s programmed to use both of its maximum count registers the output pin creates a waveform by indicating which maximum count register is currently in control The duty cycle and frequency of the wavefor...

Page 117: ...interrupt request has been generated but before the pending interrupt is serviced the interrupt request will still be present Bit 12 Register in Use Bit RIU When the Maxcount Compare A register is bei...

Page 118: ...ear the timer counts to maxcount compare A and then resets the count register to zero and starts counting again against maxcount compare A In this case maxcount compare B is not used Bit 0 Continuous...

Page 119: ...t INT When INT is set to 1 an interrupt request is generated when the count register equals a maximum count When INT is set to 0 the timer will not issue interrupt requests If the EN enable bit is cle...

Page 120: ...um count registers and various actions are triggered based on reaching a maximum count Figure 8 3 Timer Count Registers T0CNT T1CNT T2CNT offsets 50h 58h and 60h The value of these registers at reset...

Page 121: ...signals can be used to generate waveforms of various duty cycles Timer 2 has one compare register T2CMPA If a maximum count compare register is set to 0000h the timer associated with that compare regi...

Page 122: ...Timer Control Unit 8 8...

Page 123: ...able 9 1 Six registers in the peripheral control block define the operation of each channel The DMA registers consist of a 20 bit source address 2 registers a 20 bit destination address 2 registers a...

Page 124: ...operate the two DMA channels Source Address Ch 1 Source Address Ch 0 20 bit Adder Subtractor DMA Control Logic Request Selection Logic Adder Control Logic 20 20 Channel Control Register 1 Channel Con...

Page 125: ...current DMA transfer Figure 9 2 DMA Control Registers D0CON D1CON offsets CAh and DAh The value of D0CON and D1CON at reset is FFF9h Bit 15 Destination Address Space Select DM IO Selects memory or I...

Page 126: ...t on completion of the transfer count The TC bit must also be set to generate an interrupt Bits 7 6 Synchronization Type SYN1 SYN0 The SYN1 SYN0 bits select channel synchronization as shown in Table 9...

Page 127: ...MA Control register However if the TC bit in the DMA control word is set or if unsynchronized transfers are programmed DMA activity terminates when the Transfer Count register reaches 0 Figure 9 3 DMA...

Page 128: ...ted or decremented by 1 Each register can point into either memory or I O space The user must program the upper four bits to 0000b in order to address the normal 64K I O space Since the DMA channels c...

Page 129: ...combined with the four bits of the DMA Destination Address High register see Figure 9 4 to produce a 20 bit destination address Figure 9 5 DMA Destination Address Low Register D0DSTL D1DSTL offsets C...

Page 130: ...mented or decremented by 1 Each register can point into either memory or I O space The user must program the upper four bits to 0000b in order to address the normal 64K I O space Since the DMA channel...

Page 131: ...ter are combined with the four bits of the DMA Source Address High register see Figure 9 6 to produce a 20 bit source address Figure 9 7 DMA Source Address Low Register D0SRCL D1SRCL offsets C0h and D...

Page 132: ...ive it When destination synchronized transfers are requested the DMA controller relinquishes control of the bus after every transfer If no other bus activity is initiated another DMA cycle begins afte...

Page 133: ...lowed immediately by another DMA transfer 2 This source synchronized transfer is immediately followed by another DMA transfer because DRQ is not deasserted soon enough 9 4 1 2 Destination Synchronizat...

Page 134: ...s always given priority over the other or they can be programmed to alternate cycles when both have DMA requests pending see section 9 3 1 bit 5 the P bit DMA cycles always have priority over internal...

Page 135: ...el registers are modified an internally LOCKed string transfer should be used to prevent a DMA transfer from occurring between updates to the channel registers 9 4 5 DMA Channels on Reset On reset the...

Page 136: ...DMA Controller 9 14...

Page 137: ...t operating frequency If power save mode is in effect the divide factor must be reprogrammed The serial port permits 7 bit and 8 bit data transfers DMA transfers through the serial port are not suppor...

Page 138: ...output is set High and the transmit shift register is connected to the receive shift register Data transmitted by the transmit section is immediately received by the receive section The loopback mode...

Page 139: ...e TMODE The TMODE bit enables data transmission and controls the operational mode of the serial port for the transmission of data If TMODE is 0 the transmit section and transmit interrupts of the seri...

Page 140: ...en i e resetting the BRKI bit without interfering with the current data request Bit 4 Receive Data Ready RDR When the RDR bit is 1 the receive buffer register contains data that can be read When the R...

Page 141: ...re before transmitting the data Figure 10 3 Serial Port Transmit Data Register SPTD offset 84h The value of SPTD at reset is undefined Bits 15 8 Reserved Bit 7 0 Transmit Data TDATA This field is writ...

Page 142: ...while the receive data register is being read by software Figure 10 4 Serial Port Receive Data Register SPRD offset 86h The value of SPRD at reset is undefined Bits 15 8 Reserved Bits 7 0 Receive Dat...

Page 143: ...r a 40 MHz clock a baud rate of 9600 can be achieved with BAUDDIV 129 81h A 1 error applies Figure 10 5 Serial Port Baud Rate Divisor Register SPBAUD offset 88h The value of SPBAUD at reset is undefin...

Page 144: ...Asynchronous Serial Port 10 8...

Page 145: ...EN1 a clock SCLK and a data pin SDATA Five registers see Table 11 1 are used to control and monitor the interface n The Synchronous Serial Status register SSS reports the current port status n The Syn...

Page 146: ...state of SCLK is High If power save mode is in effect the SCLK frequency is affected by the reduced processor clock frequency Data is transferred across the SDATA input output pin Data is driven on t...

Page 147: ...smit registers while the SSI is busy PB 1 This bit is reset when the SDEN output is inactive bits DE1 DE0 in the SSC register are both 0 Bit 1 Data Receive Transmit Complete DR DT The DR DT bit is set...

Page 148: ...5 4 SCLK Divide SCLKDIV These bits determine the SCLK frequency SCLK is derived from the internal processor clock by dividing by 2 4 8 or 16 Table 11 2 shows the processor clock frequency divider valu...

Page 149: ...3 Writes to SSD1 or SSD0 cause the PB bit in the SSS register to be set and a transmission sequence to begin as shown in Figure 11 5 on page 11 8 A write to either SSD1 or SSD0 while the port is busy...

Page 150: ...e transmission is not initiated by reading the SSR register when neither of the enable bits is set DE1 DE0 00b This allows the software to read the received data without initiating another receive tra...

Page 151: ...gister can be an address register that holds the value of the last address accessed and the SSD0 register can be the data transmit register In this case the current value in the SSD1 register can be u...

Page 152: ...PB 0 Write to SSD Write to SSC bit DE 0 Poll SSS for PB 0 PB 0 DR DT 0 PB 1 DR DT 0 PB 0 DR DT 1 PB 1 DR DT 0 PB 0 DR DT 1 PB 1 DR DT 0 PB 0 DR DT 1 PB 0 DR DT 0 SCLK SDEN SDATA Write to SSC bit DE 1...

Page 153: ...resistors or as an open drain output After power on reset the PIO pins default to various configurations The column titled Power On Reset State in Table 12 1 lists the defaults for the PIOs The system...

Page 154: ...DT R Normal operation 3 5 DEN Normal operation 3 6 SRDY Normal operation 4 7 1 A17 Normal operation 3 8 1 A18 Normal operation 3 9 1 A19 Normal operation 3 10 TMROUT0 Input with pulldown 11 TMRIN0 Inp...

Page 155: ...e value of PIOMODE1 at reset is 0000h Bits 15 0 PIO Mode Bits PMODE31 PMODE16 This field with the PIO direction registers determines whether each PIO pin performs its pre assigned function or is enabl...

Page 156: ...ue of PDIR1 at reset is FFFFh Bits 15 0 PIO Direction Bits PDIR31 PDIR16 This field determines whether each PIO pin acts as an input or an output The most significant bit of the PDIR field determines...

Page 157: ...is configured as an output or an input in the PIO Direction registers The most significant bit of the PDATA field indicates the level of PIO31 the next bit indicates the level of PIO30 and so on The v...

Page 158: ...Programmable I O Pins 12 6...

Page 159: ...he registers Figure A 1 shows the layout of each of the internal registers The column titled Comment in Table A 1 is used to identify the specific use of interrupt registers when there is a mix of mas...

Page 160: ...h register C4 D0DSTL DMA 0 destination address low register C2 D0SRCH DMA 0 source address high register C0 D0SRCL DMA 0 source address low register A8 MPCS PCS and MCS auxiliary register A6 MMCS Midr...

Page 161: ...register Master mode T1INTCON Timer 1 interrupt control register Slave mode 36 DMA1CON DMA 1 interrupt control register Slave master 34 DMA0CON DMA 0 interrupt control register Slave master 32 TCUCON...

Page 162: ...al FE Reset Configuration Register RESCON Page 4 5 F6 15 7 0 RC Processor Release Level Register PRL Page 4 6 F4 15 7 0 PRL Reserved CAF CAD 15 7 0 CBD Power Save Control Register PDCON Page 4 7 F2 F0...

Page 163: ...1 Destination Address Low Register D1DSTL Page 9 7 D4 15 7 0 Reserved DSA19 DSA16 DMA 1 Source Address High Register D1SRCH Page 9 8 D2 15 7 0 DSA15 DSA0 DMA 1 Source Address Low Register D1SRCL Page...

Page 164: ...15 7 0 TC15 TC0 DMA 0 Transfer Count Register D0TC Page 9 5 C8 15 7 0 Reserved DDA19 DDA16 DMA 0 Destination Address High Register D0DSTH Page 9 6 C6 15 7 0 DDA15 DDA0 DMA 0 Destination Address Low R...

Page 165: ...mory Chip Select Register MMCS Page 5 8 R2 15 7 0 BA19 BA11 1 1 R3 R1 R0 1 Peripheral Chip Select Register PACS Page 5 12 A4 R2 15 7 0 R1 R0 0 UB2 UB0 1 1 1 1 R7 PSE 1 1 1 A19 Low Memory Chip Select R...

Page 166: ...D Page 10 5 84 15 7 0 Reserved TDATA Serial Port Status Register SPSTS Page 10 4 82 15 7 0 Reserved TEMT THRE RDR BRKI OER PER FER Serial Port Control Register SPCT Page 10 2 80 15 7 0 Reserved TXIE R...

Page 167: ...egister PDATA0 Page 12 5 74 PDATA15 PDATA0 15 7 0 PIO Direction 0 Register PDIR0 Page 12 4 72 15 7 0 PDIR15 PDIR0 PIO Mode 0 Register PIOMODE0 Page 12 3 70 15 7 0 PMODE15 PMODE0 15 7 0 EN INT INH 0 MC...

Page 168: ...rol Register T1CON Page 8 3 15 7 0 TC15 TC0 5C Timer 1 Maxcount Compare B Register T1CMPB Page 8 7 15 7 0 TC15 TC0 5A Timer 1 Maxcount Compare A Register T1CMPA Page 8 7 15 7 0 TC15 TC0 58 Timer 1 Cou...

Page 169: ...T Page 8 6 Serial Port Interrupt Control Register SPICON Master Mode Page 7 19 44 15 7 0 MSK Res PR2 PR0 Reserved 1 Watchdog Timer Interrupt Control Register WDCON Master Mode Page 7 18 42 15 7 0 Rese...

Page 170: ...Mode Page 7 13 PR2 PR0 MSK 15 7 0 PR2 PR0 Timer 2 Interrupt Control Register T2INTCON 3A Slave Mode Page 7 29 Reserved 15 7 0 Reserved MSK LTM C SFNM INT0 Control Register I0CON 38 Master Mode Page 7...

Page 171: ...Register TCUCON Master Mode Page 7 17 Timer 0 Interrupt Control Register T0INTCON Slave Mode Page 7 29 Reserved 15 7 0 Reserved TMR2 TMR0 DHLT Interrupt Status Register INTSTS 30 Master Mode Page 7 20...

Page 172: ...rved D0 D1 TMR1 TMR2 Res TMR0 In Service Register INSERV 2C Slave Mode Page 7 32 2A Master Mode Page 7 23 Slave Mode Page 7 33 15 7 0 Reserved PRM2 PRM0 Priority Mask Register PRIMSK Interrupt Mask Re...

Page 173: ...25 Reserved 15 7 0 S4 S0 IREQ Poll Register POLL 24 Master Mode Page 7 26 Reserved 15 7 0 S4 S0 NSPEC End of Interrupt Register EOI 22 Master Mode Page 7 27 Reserved 15 7 0 L2 L0 Specific End of Inte...

Page 174: ...erved SR Synchronous Serial Transmit 0 Register SSD0 Page 11 5 16 15 7 0 Reserved SD Synchronous Serial Transmit 1 Register SSD1 Page 11 5 14 15 7 0 Reserved SD Synchronous Serial Control Register SSC...

Page 175: ...e Divisor 10 7 BHE signal Bus High Enable definition 3 3 bits ALT Alternate Compare Bit 8 4 B W Byte Word Select 9 4 BA19 BA11 Base Address 5 12 BA19 BA13 Base Address 5 8 BAUDDIV Baud Rate Divisor 10...

Page 176: ...ve Data 10 6 RDR Receive Data Ready 10 4 RE TE Receive Transmit Error Detect 11 3 RIU Register in Use 8 3 RMODE Receive Mode 10 3 RSIE Receive Status Interrupt Enable 10 3 RTG Retrigger Bit 8 3 RXIE R...

Page 177: ...ble 11 4 DE1 bit SDEN1 Enable 11 4 DEN signal Data Enable definition 3 4 development tools thirdparty products xiv DHLT bit DMA Halt 7 20 7 30 DINC bit Destination Increment 9 3 DM IO bit Destination...

Page 178: ...Bit Timer 0 Mode Control Register 8 3 Timer 1 Mode Control Register 8 3 Timer 2 Mode Control Register 8 5 InService Register description Master mode 7 22 Slave mode 7 32 Instruction exceptions 7 3 IN...

Page 179: ...field Interrupt Type 7 35 LB2 LB0 field Lower Boundary 5 4 LCS signal Lower Memory Chip Select definition 3 6 LOOP bit Loopback 10 2 Low Memory Chip Select Register description 5 6 LTM bit LevelTrigg...

Page 180: ...10 4 Peripheral Chip Select Register description 5 12 Peripheral Control Block Relocation Register 4 4 physical dimensions xiv pin description xiv PIO Data 0 Register description 12 5 PIO Data 1 Regi...

Page 181: ...DMA 1 Destination Address Low D0DSTL Offset C4h 9 7 DMA 1 Destination Address Low D1DSTL Offset D4h 9 7 DMA 1 Interrupt Control DMA1CON Offset 36h 7 17 7 29 DMA 1 Source Address High D1SRCH Offset D2...

Page 182: ...N Offset 66h 8 5 Timer Interrupt Control TCUCON Offset 32h 7 17 Upper Memory Chip Select UMCS Offset A0h 5 4 Watchdog Timer Interrupt Control WDCON Offset 42h Master mode 7 18 RES signal Reset definit...

Page 183: ...al Chip Select 6 3 8 PIO31 PIO0 Programmable I O Pins 31 0 3 8 PLLBYPS PLL Bypass 3 14 RD Read Strobe 3 11 RES Reset 3 11 RFSH Automatic Refresh 3 7 RFSH2 ADEN Refresh 2 Address Enable 3 11 RXD Receiv...

Page 184: ...ter description 8 3 Timer 2 Count Register description 8 6 Timer 2 Interrupt Control Register description Slave mode 7 29 Timer 2 Maxcount Compare B Register description 8 7 Timer 2 Mode and Control R...

Page 185: ...n 3 14 WD bit Virtual Watchdog Timer Interrupt InService 7 22 WD bit Virtual Watchdog Timer Interrupt Mask 7 24 WD bit Virtual Watchdog Timer Interrupt Request 7 21 WHB signal Write High Byte definiti...

Page 186: ...Index I 12...

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