AMD Am186 ES, User Manual, Page: 140 / 192

DMA Controller 9-8
9.3.5 DMA Destination Address Low Register (Low Order Bits)
(D0DSTL, Offset C4h, D1DSTL, Offset D4h)
Figure 9-5 shows the DMA Destination Address Low register. The sixteen bits of this register
are combined with the four bits of the DMA Destination Address High register (see Figure
9-4) to produce a 20-bit destination address.
Figure 9-5 DMA Destination Address Low Register
The value of D0DSTL and D1DSTL at reset is undefined.
Bits 15–0: DMA Destination Address Low (DDA15–DDA0)—These bits are driven onto
A15–A0 during the write phase of a DMA transfer.
15
7 0
DDA15–DDA0