Architectural Overview
1-12
Am186™CC/CH/CU Microcontrollers User’s Manual
capability allows designs requiring larger amounts of memory to save system cost over
SRAM designs by taking advantage of low DRAM costs.
The DRAM interface uses various chip select pins to implement the RAS/CAS interface
required by DRAMs. The microcontroller’s DRAM controller drives the RAS/CAS interface
appropriately during both normal memory accesses and refresh. The microcontroller
generates all required signals and does not require external logic.
The DRAM multiplexed address pins connect to the microcontroller’s odd address pins,
starting with A1 on the microcontroller connecting to MA0 on the DRAM. The correct row
and column address are generated on these odd address pins during a DRAM access.
The RAS pins are multiplexed with LCS or MCS3, allowing a DRAM bank to be present in
either high or low memory space. MCS2 and MCS1 function as the lower and upper CAS
pins, respectively, and define which byte of data in a 16-bit DRAM is being accessed.
The microcontroller supports the most common DRAM refresh option, CAS-Before-RAS.
All refresh cycles contain three wait states to support the DRAMs at various frequencies.
The DRAM controller never performs a burst access. All accesses are single accesses to
DRAM. If the PCS chip selects are decoded to be in the DRAM address range, PCS
accesses take precedence over the DRAM.
1.4.4.3
Chip Selects (Chapter 5)
The microcontroller provides six chip select outputs for use with memory devices and eight
more chip selects for use with peripherals in either memory or I/O space. The six memory
chip selects can address three memory ranges. Each peripheral chip select addresses a
256-byte block offset from a programmable base address.
The microcontroller can be programmed to sense a ready signal for each of the peripheral
or memory chip select lines. A bit in each chip select control register determines whether
the external ready signal is required or ignored.
In addition, the chip selects can control the number of wait states inserted in the bus cycle.
Although most memory and peripheral devices can be accessed with three or less wait
states, some slower devices cannot. This feature allows devices to use wait states to slow
down the bus.
The chip select lines are active for all memory and I/O cycles in their programmed areas,
whether the cycles are generated by the CPU or by the integrated DMA unit.
General enhancements over the original 80C186 include bus mastering (three-state)
support for all chip selects, and activation only when the associated register is written (not
when it is read).
1.4.5
In-Circuit Emulator Support (Chapter 4)
Because pins are an expensive resource, many play a dual role, and the programmer selects
PIO operation or an alternate function. However, a pin configured to be a PIO may also be
required for emulation support. Therefore, it is important that before a design is committed
to hardware, a user contact potential emulator suppliers for a list of emulator pin
requirements.
The Am186CC/CH/CU microcontrollers are designed to minimize conflicts. In most cases,
pin conflict is avoided. For example, if the ALE signal is required for multiplex bus support,
then it would not be programmed as PIO33. If the multiplexed AD bus is not used for address
determination, then ALE can be programmed as a PIO pin.
Summary of Contents for Am186 CC
Page 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Page 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Page 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Page 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Page 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Page 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Page 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Page 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Page 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...