Glossary
Glossary-8
Am186™CC/CH/CU Microcontrollers User’s Manual
short frame
During an HDLC transfer, a frame containing a number
of bytes between the start and stop flags that is less
than the minimum length specified in the MINRL bit field
of the HxRCON0 register.
signal
Refers to the electrical signal that flows across a pin.
Compare to
pin.
simplex
The ability of a serial communications connection to
transmit data in one direction only.
Compare to
duplex.
SLIC
Subscriber line interface circuit.
SLAC™
Subscriber line audio-processing circuit.
SmartDMA™ channel
An AMD proprietary technique for increasing the perfor-
mance of DMA transfers. SmartDMA channels provide
a method for the transmission and reception of data
across multiple memory buffers and a sophisticated
buffer-chaining mechanism. These channels are always
used in pairs: transmitter and receiver. The transmit
channels can only transfer data from memory to a
peripheral; the receive channels can only transfer data
from a peripheral to memory.
See also
DMA
and
gen-
eral-purpose DMA.
SOHO
Small office/home office.
SRAM
Static random access memory. A type of semiconductor
memory that preserves stored information as long as
there is enough power flow to keep the device running.
SRAM does not need refreshing like DRAM. SRAM is
faster and more dependable, but also is more expen-
sive, takes up more space, and uses more power than
DRAM.
software exception
A software interrupt that occurs when an instruction
causes a particular condition in the processor.
software interrupt
An interrupt initiated by the INT or INTO software
instruction, or by a software exception. A software inter-
rupt does not affect the IF flag in the FLAGS register.
Compare to
hardware interrupt.
source-synchronized transfer
See
synchronized transfer.
SSI
Synchronous serial interface. An AMD proprietary tech-
nology for providing half-duplex, bidirectional data
transfers at transfer rates of up to 25 Mbit/s with a
50-MHz CPU clock. The SSI supports only polled mode,
not interrupt or DMA modes.
stream pipe
A pipe that transfers data as a stream of samples with
no defined USB structure.
synchronization type
A classification that characterizes an isochronous end-
point’s capability to connect to other isochronous
endpoints.
synchronized transfer
A transfer of information in which the transmitter and
receiver coordinate their operations with a clock signal
or some other technique so the receiver knows when
the next piece of information is available from the trans-
mitter. In DMA operations, a synchronized transfer
takes place when either the source of the data (source-
synchronized) or the destination of the data (destina-
tion-synchronized) generates a DRQ to request the
transfer.
Compare to
unsynchronized transfer.
synchronous transmission
Data transmission in which the time of occurrence of
each signal representing a bit is related to a fixed time
frame. Typically, the transmitter sends a clock signal
along with the data so the receiver knows when to
receive each bit.
Compare to
asynchronous transmis-
sion
and
isochronous transmission.
system reset
The reset of the Am186CC/CH/CU microcontrollers (the
CPU plus the internal peripherals) as well as any exter-
nal peripherals connected to the RESOUT pin. An
external reset always causes a system reset; an internal
reset can optionally cause a system reset.
Compare to
internal reset
and
external reset.
T
TDM
Time-division multiplex. A method of transmitting multi-
ple signals (data, voice, and/or video) simultaneously
over one communications medium by interleaving a
piece of each signal one after another.
TIC
Terminal interchip communication.
top of FIFO
The memory address or register where the next item in
a first-in-first-out buffer can be read.
Summary of Contents for Am186 CC
Page 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Page 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Page 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Page 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Page 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Page 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Page 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Page 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Page 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...