General Circuit Interface (GCI)
Am186™CC/CH/CU Microcontrollers User’s Manual
17-7
MEOMRQ bit being set, the GCI controller deactivates the outgoing MX bits in response
to incoming MR bits going inactive, and leaves them inactive.
17.5.1.2
Receiving Data
1. Configure the HDLC channels and time slot assigners to receive the data. For details,
see Chapter 15, “High-Level Data Link Control (HDLC),” and Chapter 16, “HDLC
External Serial Interface Configuration (TSAs).”
2. Configure the GCI channels:
a. If using the TIC bus access procedure, set the TICEN bits in the GTIC register. For
information about the TIC bus access procedure, see “TIC Bus Support” on
page 17-16.
b. If receiving Monitor channel data, set the applicable configuration options in the
GPCON register (the MCHEN, MCHSEL, and BRDIS bits).
c. If receiving IC channel data, set the applicable configuration options in the GPCON
register (the ICSEL and BRDIS bits).
d. For CI/1 channel data, set the applicable configuration option in the GPCON register
(the BRDIS bit).
e. If the bus is in a deactivated state, activate the bus by setting the GCIACT bit in the
GPCON register. For details, see “GCI Bus Deactivation/Activation” on page 17-9.
3. Set the interrupts to be taken with the GIMSK register. Bits in this register enable
interrupts based on interrupts set in the GISTAT register. If software disables an interrupt
in GIMSK, it can still read the interrupt status in the GISTAT register.
4. Wait for the DCLST bit in the GISTAT register to be set, indicating the data clock has
been started by the master clock device.
5. If the bus was in a deactivated state, turn off the GCI activation request by clearing the
GCIACT bit in the GPCON register.
6. For monitor channel transmission, on the first data available interrupt, software must set
the MCARV configuration bit to continue transmission. This bit holds off the remote
transmitter until software has determined the first byte is valid (the first byte is usually a
known address byte). If software fails to determine that the first byte is valid, then software
should abort reception (i.e., this message is for some other downstream device).
7. For monitor channel transmission, the MEOMRD interrupt is set to indicate that an end-
of-message (EOM) has been received by the monitor channel.
At the time the receiver sees the first byte, indicated by the inactive-to-active transition of
incoming MX bits, outgoing MR bits are by definition inactive. The GCI controller activates
outgoing MR bits in response to the activation of incoming MX bits, loads the data byte on
the bus into the Monitor Receive Data register, and generates a Monitor channel receive
data available interrupt. Outgoing MR bits remain active until the next byte is received or
an EOM is detected (incoming MX bits held inactive for two or more frames).
In subsequent receives, the GCI controller receives data into the buffer on each falling edge
of incoming MX bits, and generates a Monitor channel receive data available interrupt. Note
that the data was actually valid at the time the incoming MX bits became inactive, one frame
before becoming active (the Am186CC microcontroller performs a data integrity check to
confirm stable data for two frames). Outgoing MR bits are deactivated at the time data is
read and reactivated one frame later. The receipt of an EOM, which is incoming MX bits
remaining inactive for two or more frames, terminates the reception of data.
Summary of Contents for Am186 CC
Page 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Page 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Page 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Page 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Page 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Page 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Page 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Page 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Page 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...