High-Level Data Link Control (HDLC)
Am186™CC/CH/CU Microcontrollers User’s Manual
15-21
■
The receiver sets the One Receive Data Byte Available (RDATA1) bit in the HDLC
Channel Interrupt Status 0 (HxISTAT) register when the
current byte available is data;
the RDATA1 bit does not reflect the entire FIFO contents. If the next byte is status and
the following byte is data, the receiver does
not set RDATA1.
15.5.9
Software-Related Considerations
■
After setting the HREN bit to enable the receiver, the device software must reset the
HDLC FIFOs by setting the HRESET bit in the HxCON register. This clears any invalid
data in the receive FIFO that might be mistaken as the start of the data stream. Invalid
data is a concern when using Transparent mode (TRANSM = 1 in the HxCON register),
because in Transparent mode the receiver cannot rely on flag sequences to indicate the
start of valid data.
■
When the HDLC channel is disabled, the FIFO status reads as full.
■
In the Am186CC microcontroller, HDLC Channel D is multiplexed with the UART and
with flow control on the High-Speed UART. The Interface 4 Select (ITF4) bits in the
System Configuration (SYSCON) register must be configured for the HDLC interface.
15.5.10
Comparison to Other Devices
In addition to HDLC, the HDLC channels support the SDLC, LAP-B, LAP-D, PPP, and v.120
communications protocols. The HDLC channels can also be used in transparent mode to
support the v.110 protocol.
The HDLC protocol is similar to these other bit-oriented protocols:
■
The Advanced Data Communication Control Procedures (ADCCP) developed by the
American National Standards Institute (ANSI X3.66) is virtually identical to the HDLC
protocol.
■
The Link Access Procedure Balanced (LAP-B), adopted by the International Telegraph
and Telephone Consultative Committee (CCITT) as part of its X.25 packet-switched
network standard, is a subset of HDLC.
■
Although not a standard, IBM’s Synchronous Data Link Control (SDLC) is in widespread
use. SDLC is a subset of HDLC, with some differences.
15.6
INITIALIZATION
On both external and internal reset, the following occurs:
■
The multiplexed HDLC signals default to the signals shown in Table 15-1 on page 15-4.
■
All HDLC registers default to 00h except the HxSTATE, HxTD, HxRD/HxRDP, and
HxRFSx registers.
■
The ITF4 bit in the SYSCON register is cleared, which defaults external interface D to
HDLC with flow control.
■
The EXSYNC bit in the SYSCON register is cleared, which configures HDLC Channel C
for raw DCE or PCM highway modes.
CC
CC
CC
Summary of Contents for Am186 CC
Page 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Page 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Page 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Page 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Page 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Page 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Page 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Page 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Page 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...