Interrupts
7-20
Am186™CC/CH/CU Microcontrollers User’s Manual
7.5.6.7
Array Bounds Exception (Interrupt Type 05h)
If an array index is outside the array bounds, a BOUND instruction generates an Array
Bounds exception. The array bounds are located in memory at a location indicated by one
of the instruction operands. The other operand indicates the value of the index to be
checked. For more information, see the
Am186 and Am188 Family Instruction Set Manual,
order #21267.
7.5.6.8
Unused Opcode Exception (Interrupt Type 06h)
If the processor attempts to execute an undefined opcode, it generates an Unused Opcode
exception.
7.5.6.9
ESC Opcode Exception (Interrupt Type 07h)
If the processor attempts to execute an ESC opcode (D8h–DFh), it generates the ESC
Opcode exception. The processor does not check the escape opcode trap bit. The return
address of this exception points to the ESC instruction that caused the exception. If a
segment override prefix preceded the ESC instruction, the return address points to the
segment override prefix.
Note: All numeric coprocessor opcodes cause a trap. The Am186CC/CH/CU
microcontrollers do not support the numeric coprocessor interface.
7.5.7
Software-Related Considerations
■
The watchdog timer can generate an NMI. This interrupt can be taken at any time. Unlike
the maskable interrupts, the controller is not inhibited from taking a second NMI request
while the NMI interrupt service routine is executing. Therefore a watchdog timer-
generated NMI can interrupt, or be interrupted by, an externally generated NMI. For more
information about the watchdog timer NMI, see “Considerations for NMI, Software
Interrupts, and Traps” on page 7-14.
■
Writing a zero to the appropriate channel bit in the Interrupt Request (REQST) register
clears the pending interrupt. This facility provides a simple way to clear a spurious edge-
triggered interrupt that may have occurred when initially configuring a PIO pin as an
interrupt source.
7.5.8
Comparison to Other Devices
The interrupt controller supports the Fully Nested Master mode and Polled mode operation
available in all AMD Am186 devices. The interrupt controller does
not support Slave mode,
Cascade mode, or Special Fully Nested mode. Support for the NMI and software interrupts
are similar to Master mode in AMD’s Am186ES microcontroller.
7.6
INITIALIZATION
On both an external and internal reset, the following occurs:
■
All priority bits in the Channel Control (CHxCON) registers are set to 1. This places all
sources at the lowest priority (level 7). The overall priority of the interrupts determines
the priority in which each interrupt is granted by the interrupt controller until
programmable priorities are changed by reconfiguring the CHxCON registers.
■
All mask bits in the Channel Control (ChxCON) registers are set to 1, so all interrupts
are masked.
■
All Level-Triggered Mode (LTM) bits in the Channel Control (CHxCON) registers are
cleared, resulting in edge-triggered mode.
■
All source bits in the Channel Control (CHxCON) registers are cleared, defining the
source as that channel’s external interrupt source.
Summary of Contents for Am186 CC
Page 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Page 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Page 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Page 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Page 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Page 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Page 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Page 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Page 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...