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AMD Geode™ GX Processor/CS5535 Companion Device GeodeROM Porting Guide

List of Figures

32430C

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Summary of Contents for CS5535

Page 1: ...AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide April 2006 Publication ID 32430C...

Page 2: ...plied warranty of mer chantability fitness for a particular purpose or infringement of any intellectual property right AMD s products are not designed intended authorized or warranted for use as compo...

Page 3: ...deLink Architecture 13 3 1 GeodeLink MSR Addressing 14 3 2 Descriptors 14 4 0 Initialization 15 4 1 Processor Initialization 15 4 2 AMD Geode CS5535 Companion Device Initialization 20 4 3 Virtual Syst...

Page 4: ...4 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide Contents 32430C...

Page 5: ...ures 32430C List of Figures Figure 3 1 GeodeLink Architecture Topology 13 Figure 4 1 Clock Control 15 Figure 7 1 GLIU Descriptor Map 31 Figure 7 2 CPU Core Cache Descriptors 31 Figure 7 3 CPU Core Cac...

Page 6: ...6 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide List of Figures 32430C...

Page 7: ...GX Processor CS5535 Companion Device GeodeROM Porting Guide 7 List of Tables 32430C List of Tables Table 4 1 Default Region Configuration Properties Bit Descriptions 18 Table 4 2 Diverse Device I O Lo...

Page 8: ...8 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide List of Tables 32430C...

Page 9: ...5535 device system Where appro priate the changes list the Entry Conditions that briefly describe the machine state required to execute that function as well as some pseudo code for implementing the c...

Page 10: ...10 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide Assumption 32430C...

Page 11: ...modules on the GeodeLink interface the address of that module must be known Addresses are obtained by either scanning the GeodeLink interface or having prior knowledge of the chip topology This is di...

Page 12: ...12 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide Model Specific Registers 32430C...

Page 13: ...modules are connected to GLIU ports 1 7 as shown in Figure 3 1 Port 0 is always the GLIU itself GLIUs can be chained together and up to a maximum of six GLIUs can be connected allowing for 32 modules...

Page 14: ...mplemented MSR accesses not in periph eral modules go to the bit bucket 3 1 1 Addressing Example GX Processor GeodeLink Modules Addresses Source CPU Core Destination GeodeLink Control Processor GLCP 2...

Page 15: ...are controlled by three divisors as shown in Figure 4 1 The Feed back Divisor FbDIV in the PLL sets sppl_raw_clk Sppl_raw_clk is divided by the GeodeLink Divisor MDIV and the CPU Divisor VDIV to deri...

Page 16: ...ation The CPUID check should be done as soon as possible Use the CPUID instruction Check the Major and Minor Revision fields located in the GLCP_CHIP_REVID register MSR Address 4C000017h 7 0 for the s...

Page 17: ...e Load RDSYNC counter with sync value Note See the AMD Geode GX Processors Data Book publication ID 31505 for bit descriptions and allocation 4 1 4 Test Extended DRAM Entry Conditions 4 GB descriptor...

Page 18: ...through register CR0 and both caches can be disabled through MSRs regardless of the CR0 state 4 1 5 4 Region Configuration Region Configuration MSRs are used to describe the caching properties of eac...

Page 19: ...region MRSs are assigned Memory Region 0 Configu ration R0 through Memory Region 5 Configuration R5 Descriptor Allocation Register PHY_CAP MSR Address GLIU0 10000086h GLIU1 40000086h Each GLIU descrip...

Page 20: ...ister GX GLPCI MSR Address 50000201Eh must match the device number to route MSR transactions across the PCI bus Example set IDSEL mov eax 02000000h IDSEL AD25 device 15 mov eax 04000000h IDSEL AD30 de...

Page 21: ...rest 16 64 are hooked to ASMI Location NA Description Used for A20 support as well as USB keyboard emulation Initialization VSA technology Location 6000h Description SMBus is an industry standard two...

Page 22: ...for 4 Flash devices Description NA Initialization The default values for the LBARs are located in BDCFG INC in the platform directory but can be changed at Boot via setup The Flash interface is config...

Page 23: ...ry and I O requests which are converted by the PCI Adapter PA into PCI memory and I O requests that target the USBC It also sup ports in bound MSR transactions to the MSRs 4 2 7 AC97 Audio Controller...

Page 24: ...m 4 to 16 MB To inhibit operating system DRAM detection code from reporting the frame buffer as part of system memory a GLIU offset descriptor is set to send transactions to the PCI bus and program Re...

Page 25: ...RAM functional Interrupts enabled DMA initialized PCI bus functional Procedure 4 5 1 1 Monochrome Support GeodeROM includes the appropriate INT 10h support for monochrome video adapters SoftVG needs a...

Page 26: ...26 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide Initialization 32430C...

Page 27: ...k clock used for the memory clock The Dot clock is used for video display control The Core and GeodeLink clocks can be programmed and restarted by reseting the GX processor 5 1 2 Scratchpad Initializa...

Page 28: ...28 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide Implementation 32430C...

Page 29: ...tup Options Clock configuration complete control of system PLLs Default Use strap setting for core GeodeLink interface frequency is calculated based on DIMM type PM settings Default Off Audio enable d...

Page 30: ...30 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide 32430C...

Page 31: ...Mask Offset RO Range Offset No Swiss Cheese Offset ROM Subtractive to PCI Subtractive to PCI Subtractive to PCI Memory Mapped VSA Subtractive to PCI Memory Mapped Frame Buffer Memory Mapped Video Reg...

Page 32: ...sters PCI Frame Buffer VSA Extended Memory System and Option ROMs Conventional Memory RCONF_DEFAULT ROMRC RCONF_DEFAULT ROMBASE RCONF_DEFAULT DEVRG RCONF_SMM RCONF_DEFAULT SYSTOP RCONF_DEFAULT SYSRC R...

Page 33: ...mper Settings or CMOS CPU Speed to get PCI Clock DRAM Clock Setting from SPD Set All Clocks GLCP_SYS_RSTPPL MSR Addr 4C00014h Set PLL Flag Internal PLL Reset Halt Uses CPU ID instruction Load CMOS NVR...

Page 34: ...Setup Stack Shadow ROM Initialize and Enable Cache Northbridge Initialization and CPU Bug Fixes Chipset Initialization SuperI O Initialization CS5535 descriptor set here after shadow Enable Interrupts...

Page 35: ...recorded in the table s below Table A 1 Revision History Revision PDF Date Revisions Comments A 30 Jun 2005 Initial release B 22 Mar 2006 The goal was to remove Confidential to make this an non NDA do...

Page 36: ...One AMD Place P O Box 3453 Sunnyvale CA 94088 3453 USA Tel 408 749 4000 or 800 538 8450 TWX 910 339 9280 TELEX 34 6306 www amd com...

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