7–2
Chapter 7: Register Descriptions
Configuration Space Register Content
Stratix V Hard IP for PCI Express
June 2012
Altera Corporation
f
For comprehensive information about these registers, refer to Chapter 7 of the
Express Base Specification Revision 3.0.
describes the Type 0 Configuration settings.
1
In the following tables, the names of fields that are defined by parameters in the
parameter editor are links to the description of that parameter. These links appear as
green
text.
describes the Type 1 Configuration settings
.
Table 7–2. PCI Type 0 Configuration Space Header (Endpoints), Rev3.0 Spec: Type 0 Configuration Space Header
Byte Offset
31:24
23:16
15:8
7:0
0x000
0x004
Status
Command
0x008
0x00C
0x00
Header Type
)
0x00
Cache Line Size
0x010
Base Address Register (BAR) and Expansion ROM Settings
0x014
Base Address Register (BAR) and Expansion ROM Settings
0x018
Base Address Register (BAR) and Expansion ROM Settings
0x01C
Base Address Register (BAR) and Expansion ROM Settings
0x020
Base Address Register (BAR) and Expansion ROM Settings
0x024
Base Address Register (BAR) and Expansion ROM Settings
0x028
Reserved
0x02C
0x030
Expansion ROM base address
0x034
Reserved
Capabilities Pointer
0x038
Reserved
0x03C
0x00
0x00
Interrupt Pin
Interrupt Line
Note to
(1) Refer to
for a comprehensive list of correspondences between the Configuration Space registers and the
.
Table 7–3. PCI Type 1 Configuration Space Header (Root Ports) Rev3.0 Spec: Type 1 Configuration Space Header (Part 1
of 2)
Byte Offset
31:24
23:16
15:8
7:0
0x0000
0x004
Status
Command
0x008
0x00C
BIST
Header Type
Primary Latency
Timer
Cache Line Size
0x010
0x014