Chapter 6: Board Test System
6–19
Using the Board Test System
July 2012
Altera Corporation
Stratix V GX FPGA Development Kit
User Guide
The XCVR3 Tab
The
XCVR3
tab allows you to perform loopback tests on the SMA port.
Figure 6–9
shows the
XCVR3
tab.
1
The external loopback mode will not pass due to only having a transmit port
available. To test in internal loopback, adjust the setting using the PMA button (serial
loopback = 1).
The following sections describe the controls on the
XCVR3
tab.
Status
The
Status
control displays the following status information during the loopback test:
■
PLL lock
—Shows the PLL locked or unlocked state.
■
Channel lock
—Shows the channel locked or unlocked state. When locked, all
lanes are word aligned and channel bonded, and all TX and RX PLL lanes are
phase locked to data; RX lanes are word aligned and deskewed.
Figure 6–9. The XCVR3 Tab
electronic components distributor
