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Chapter 2: Board Components

2–49

On-Board Memory

Altera Corporation

Stratix III 3SL150 Development Board

Reference Manual

DDR2 SDRAM DIMM

The board has 1 GByte DDR2 SDRAM DIMM memory interface with a 72-bit data
width on the vertical I/O banks, which is typically used as a 64-bit interface with the
additional 8 bits serving as error correction coding (ECC) bits for each of the 8-byte
lanes. The target frequency is 400 MHz (800 Mbps) with potential operation of up to
533 MHz (1,066 Mbps). The theoretical bandwidth of the entire DDR2 interface is
6,388 Mbps plus ECC, or 7,187 Mbps raw throughput.

The data interface to the FPGA fabric runs at either one-half or one-quarter the
physical layer data rate when using the Altera DDR2 MegaCore

®

function, which

equates to a doubling or quadrupling of the physical data bus width (144 bits or
288 bits, respectively). For example, a 72-bit interface with a 400-MHz external clock
speed can have a 400-MHz 144-bit internal bus or a 200-MHz 288-bit interface.

lists the DDR2 DIMM interface signals. Signal names and type are relative

to the Stratix III device regarding the I/O setting and direction. JEDEC bus widths are
used.

Table 2–45. DDR2 DIMM Interface I/O Signals (Part 1 of 4)

Board Reference

Description

Schematic

Signal Name

I/O Standard

Stratix III

Pin Number

J19 pin 188

Address bit 0

DDR2_DIMM_A0

SSTL-18 class I

AM19

J19 pin 183

Address bit 1

DDR2_DIMM_A1

SSTL-18 class I

AM18

J19 pin 63

Address bit 2

DDR2_DIMM_A2

SSTL-18 class I

AF16

J19 pin 182

Address bit 3

DDR2_DIMM_A3

SSTL-18 class I

AN16

J19 pin 61

Address bit 4

DDR2_DIMM_A4

SSTL-18 class I

AM17

J19 pin 60

Address bit 5

DDR2_DIMM_A5

SSTL-18 class I

AL19

J19 pin 180

Address bit 6

DDR2_DIMM_A6

SSTL-18 class I

AK18

J19 pin 58

Address bit 7

DDR2_DIMM_A7

SSTL-18 class I

AD16

J19 pin 179

Address bit 8

DDR2_DIMM_A8

SSTL-18 class I

AE16

J19 pin 177

Address bit 9

DDR2_DIMM_A9

SSTL-18 class I

AM16

J19 pin 70

Address bit 10

DDR2_DIMM_A10

SSTL-18 class I

AH19

J19 pin 57

Address bit 11

DDR2_DIMM_A11

SSTL-18 class I

AL16

J19 pin 176

Address bit 12

DDR2_DIMM_A12

SSTL-18 class I

AF20

J19 pin 196

Address bit 13

DDR2_DIMM_A13

SSTL-18 class I

AE23

J19 pin 174

Address bit 14

DDR2_DIMM_A14

SSTL-18 class I

AG19

J19 pin 173

Address bit 15

DDR2_DIMM_A15

SSTL-18 class I

AP12

J19 pin 71

Bank address bit 0

DDR2_DIMM_BA0

SSTL-18 class I

AN18

J19 pin 190

Bank address bit 1

DDR2_DIMM_BA1

SSTL-18 class I

AL17

J19 pin 54

Bank address bit 2

DDR2_DIMM_BA2

SSTL-18 class I

AD15

J19 pin 125

Data write mask (byte enables) bit 0

DDR2_DIMM_DM0

SSTL-18 class I

AL12

J19 pin 134

Data write mask (byte enables) bit 1

DDR2_DIMM_DM1

SSTL-18 class I

AP10

J19 pin 146

Data write mask (byte enables) bit 2

DDR2_DIMM_DM2

SSTL-18 class I

AJ15

J19 pin 155

Data write mask (byte enables) bit 3

DDR2_DIMM_DM3

SSTL-18 class I

AL22

J19 pin 202

Data write mask (byte enables) bit 4

DDR2_DIMM_DM4

SSTL-18 class I

AE22

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Summary of Contents for Stratix III 3SL150

Page 1: ...101 Innovation Drive San Jose CA 95134 www altera com MNL 01030 1 5 Reference Manual Stratix III 3SL150 Development Board Feedback Subscribe Stratix III 3SL150 Development Board Reference Manual ...

Page 2: ...or products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to...

Page 3: ...LEDs 2 20 Power Display 2 21 Setup Elements 2 21 JTAG Control DIP Switch 2 21 MAX II Device Control DIP Switch 2 22 System Reset and Configuration Switches 2 23 Power Select Rotary Switch 2 23 PGM Config Select Rotary Switch 2 24 Clocking Circuitry 2 25 Stratix III FPGA Clock Inputs 2 26 Stratix III FPGA Clock Outputs 2 27 General User Interfaces 2 28 User Defined Push Button Switches 2 28 User De...

Page 4: ...9 DDR2 SDRAM Devices 2 53 QDRII SRAM 2 55 P SRAM 2 58 Flash Memory 2 63 Power Supply 2 67 Power Distribution System 2 67 Power Measurement 2 68 Security Key and Battery Backup 2 69 Statement of China RoHS Compliance 2 70 Additional Information Document Revision History Info 1 How to Contact Altera Info 2 Typographic Conventions Info 2 ...

Page 5: ...C specification visit www altera com Design advancements and innovations such as Programmable Power Technology and selectable core voltage ensure that designs implemented in Stratix III FPGAs operate faster but consume less power than previous generation Stratix devices f For more information about Stratix III device Programmable Power Technology refer to the following documents Stratix III Progra...

Page 6: ...MegaCore functions refer to the Video and Image Processing Suite User Guide Board Component Blocks The board features the following major component blocks 1 152 pin Altera Stratix III EP3SL150F FPGA in a ball grid array BGA package 142 000 logic elements LEs 5 499 Kbits of memory 384 multiplier blocks Eight phase locked loops PLLs 16 global clock networks 736 user I Os 1 1 V core power 256 pin Alt...

Page 7: ...ceive LED TX RX per HSMC interface One HSMC present LED per HSMC interface Six Ethernet LEDs User Quad 7 segment display Power consumption display Push buttons User reset push button CPU reset Four general user push buttons System reset push button user configuration One factory push button switch factory configuration DIP switches MAX II control DIP switch Eight user DIP switches Speaker header D...

Page 8: ... be damaged Therefore use anti static handling precautions when touching the board Figure 1 1 Stratix III Development Board Block Diagram 1 5 V HSTL Statix III EP3SL1501152 EP3SL340H1152 125 MHz XTAL MAX II Device x16 2 5 V CMOS 1 8 V CMOS Power Measure Display 72 Mbit QDRII 18 18 CMOS LVDS 4 MB SSRAM x32 64 MB Flash x16 1 GByte DDR2 x72 USB 2 0 1 8 V SSTL 50 MHz XTAL 1 8 V CMOS Quad 7 Seg User LE...

Page 9: ...n page 2 25 General User Interfaces on page 2 28 Components and Interfaces on page 2 39 On Board Memory on page 2 48 Power Supply on page 2 67 Statement of China RoHS Compliance on page 2 70 1 A complete set of board schematics a physical layout database and GERBER files for the Stratix III development board reside in the Stratix III Development Kit documents directory f For information about powe...

Page 10: ... U9 24 MHz Crystal Y4 DDR2 SDRAM U17 U20 DDR2 SDRAM DIMM Connector J19 Power Select Rotary Switch SW6 Power LED D16 HSMC Port A J18 HSMC Port B J8 HSMC Port A Present LED D17 Power Display U27 User DIP Switch SW5 HSMC Port A TX RX Activity LEDs D11 D12 HSMC Port B Present LED D10 Speaker Header J1 HSMC Port B TX RX Activity LEDs D2 D3 User Display U28 QDRII SRAM U15 Behind the LCD Screen JTAG Cont...

Page 11: ...USB PHY Y3 6 MHz crystal USB PHY FTDI reference clock Y4 24 MHz MAX II 24 MHz device clock Y5 125 MHz 125 MHz clock oscillator used for the system clock Y6 50 MHz 50 MHz clock oscillator used for data processing J16 SMA clock input SMA connector that allows the provision of an external clock input J17 SMA clock output SMA connector that allows the provision of an external clock output General User...

Page 12: ...nection The connector is fed by a 10 100 1000 base T PHY device with an RGMII interface to the Stratix III device J8 and J18 HSMC Port A and Port B HSMC connectors to allow for expansion via the addition of HSMCs Power Supply J21 DC power jack 14 20 V DC power source SW4 Input Switches the board s power on and off Table 2 1 Stratix III Development Board Part 3 of 3 Board Reference Type Description...

Page 13: ... V CMOS 2 5 V LVDS 88 3 clock inputs HSMC Port B 2 5 V CMOS 2 5 V LVDS 88 3 clock inputs Device I O total 628 Stratix III device I O total 736 Table 2 4 Stratix III Device Pin Count Part 2 of 2 Function I O Type I O Count Special Pins Figure 2 2 System I O Bank Diagram Bank 7A 40 Bank 7B 24 Bank 7C 32 Bank 8C 32 Bank 1A 48 Bank 1C EP3SL150 QDR II USER PB 1 5 V 73 pins 2 5 V 74 pins User FLASH SRAM...

Page 14: ... VCCPGM 2 5 V 3 0 V VCCPD 2 5 V VCCA_PLL 2 5 V VCC_CLKIN 2 5 V VCCBAT 1 2 V to 3 3 V VCCIO The board s target device the EP3SL150F1152C2 comprises the following 57 000 adaptive logic modules ALMs 142 000 LEs 1 775 KBytes of RAM 736 user I O 8 PLLs 16 global clocks 384 18 18 multipliers in finite impulse response FIR mode The board is designed to migrate to the EP3SL340H1152C3 device which provides...

Page 15: ...re not available in the F1152 package Figure 2 3 EP3SL150F1152 Device I O Bank Resources Figure 2 4 EP3SL340F1517 Device I O Bank Diagram Bank 7A 40 Bank 7B 24 Bank 7C 32 Bank 8C 32 Bank 1A 48 Bank 1C EP3SL150 Bank Name Number of I Os Bank Name Number of I Os 40 Bank 2C 40 Bank 2A Bank 6A Bank 6C Bank 5C Bank 5A 48 48 40 40 48 Bank 8B 24 Bank 8A 40 Bank 4A 40 Bank 4B 24 Bank 4C 32 Bank 3C 32 Bank ...

Page 16: ...s are relative to the MAX II device U5 Figure 2 5 MAX II Device s Block Diagram Cypress 480 Mb s USB x16 FTDI 12 Mb s USB x8 Config Status LEDs 8 MB SRAM x32 64 MB Flash x16 MAX II CPLD JTAG Header 24 MHz MAX II Device Control DIP Switch Power Display RESET_CONFIG PB CPU_RESET PB FACTORY_CONFIG PB PWR_SEL JTAG Control DIP Switch Stratix III Device PS Config JTAG Config USB Data Bus PGM_CONFIG_SEL ...

Page 17: ...s shared with flash and P SRAM bit 12 FSM_A12 1 8 V A30 U9 pi A12 and U4 pin H5 and U10 pin H5 T12 Address bus shared with flash and P SRAM bit 13 FSM_A13 1 8 V A33 U9 pin B5 and U4 pin G3 and U10 pin G3 M11 Address bus shared with flash and P SRAM bit 14 FSM_A14 1 8 V B31 U9 pin C5 and U4 pin G4 and U10 pin G4 R12 Address bus shared with flash and P SRAM bit 15 FSM_A15 1 8 V A31 U9 pin D7 and U4 ...

Page 18: ...nd U4 pin G6 N6 Data bus shared with flash and SRAM bit 8 FSM_D8 1 8 V J25 U9 pin E1 and U4 pin B1 T4 Data bus shared with flash and SRAM bit 9 FSM_D9 1 8 V A24 U9 pin E3 and U4 pin C1 M6 Data bus shared with flash and SRAM bit 10 FSM_D10 1 8 V A26 U9 pin F3 and U4 pin C2 R5 Data bus shared with flash and SRAM bit 11 FSM_D11 1 8 V B25 U9 pin F4 and U4 pin D2 P7 Data bus shared with flash and SRAM ...

Page 19: ...FSM_D30 1 8 V D23 U10 pin F1 C15 Data bus shared with flash and SRAM bit 31 FSM_D31 1 8 V B28 U10 pin G1 L13 Flash address valid FLASH_ADVn 1 8 V C7 U9 pin F6 K14 Flash chip enable FLASH_CEn 1 8 V K25 U9 pin B4 L15 Flash clock FLASH_CLK 1 8 V K24 U9 pin E6 M16 Flash output enable FLASH_OEn 1 8 V K23 U9 pin F8 L11 Flash ready busy FLASH_RDYBSYn 1 8 V L16 U9 pin F7 M15 Flash reset FLASH_RESETn 1 8 V...

Page 20: ... USB_FD4 2 5 V AF34 A7 USB data from MAX II to Stratix III bit 5 USB_FD5 2 5 V AG33 D8 USB data from MAX II to Stratix III bit 6 USB_FD6 2 5 V AA25 B7 USB data from MAX II to Stratix III bit 7 USB_FD7 2 5 V AE32 C9 USB full from MAX II to Stratix III device USB_FULL 2 5 V AE11 J14 USB clock from MAX II to Stratix III device USB_IFCLK 2 5 V U1 A11 USB read enable from MAX II to Stratix III device U...

Page 21: ... 2 5 V U12 pin 51 B11 Cypress USB data bus bit 15 USB_PHY_FD15 2 5 V U12 pin 52 C7 Cypress USB clock USB_PHY_IFCLK 2 5 V R89 A4 Cypress USB command data select USB_PHY_CMD_DATA 2 5 V U12 pin 29 E6 Cypress USB read enable USB_PHY_REN 2 5 V U12 pin 30 B4 Cypress USB write enable USB_PHY_WEN 2 5 V U12 pin 31 D6 Cypress USB empty USB_PHY_EMPTY 2 5 V U12 pin 1 C4 Cypress USB full USB_PHY_FULL 2 5 V U12...

Page 22: ...27 pin 7 F5 MAX II output to power 7 segment display PWR_SEG_DP 2 5 V U27 pin 5 F2 MAX II output to power 7 segment display PWR_SEG_MINUS 2 5 V U27 pin 13 F6 MAX II output to power 7 segment display PWR_DIG_SEL1 2 5 V U27 pin 1 F1 MAX II output to power 7 segment display PWR_DIG_SEL2 2 5 V U27 pin 10 G3 MAX II output to power 7 segment display PWR_DIG_SEL3 2 5 V U27 pin 4 G2 MAX II output to power...

Page 23: ...g regulators LT4601_CLK90 2 5 V U33 pin A8 J3 Synchronous clock for switching regulators LT4601_CLK180 2 5 V U34 pin A8 N3 JTAG clock FPGA_JTAG_TCK 2 5 V F30 J18 pin 35 and J8 pin 35 and U2 pin 3 P2 JTAG mode select FPGA_JTAG_TMS 2 5 V H28 J18 pin 36 and J8 pin 36 and U2 pin 6 L6 JTAG data input MAX_JTAG_TDI 2 5 V U3 pin 14 and U2 pin 14 M5 JTAG data output MAX_JTAG_TDO 2 5 V U3 pin 11 and U2 pin ...

Page 24: ...gnal MAX_FACTORY 1 8 V D36 G12 MAX II status signal MAX_USER 1 8 V D35 E15 MAX II status signal MAX_EMB 1 8 V D1 E13 MAX II status signal DEV_SEL 1 8 V U2 pin 1 and J2 pin 1 E14 Control signal MWATTS_MAMPS 1 8 V SW2 pin 1 D13 Control signal VOLTS_WATTS 1 8 V SW2 pin 2 R16 Control signal RESET_CONFIGn 1 8 V S7 N14 PFL enable MAX_DIP0 1 8 V SW2 pin 5 M13 N A MAX_DIP1 1 8 V SW2 pin 6 N15 N A MAX_DIP2...

Page 25: ...push button switches Power Select rotary switch PGM Config Select rotary switch Configuration This section discusses FPGA flash memory and MAX II device programming methods supported by the Stratix III development board FPGA Programming Over USB You can configure the FPGA at any time the board is powered on using the USB 2 0 interface and the Quartus II Programmer in JTAG mode The JTAG chain is ma...

Page 26: ...Bypass HSMA_Bypass USB 2 0 TDO TDI TMS TCK GPIO Pins DEV_SEL HSMA_Bypass MAX_EN GPIO Pins GPIO Pins GPIO Pins HSMC Port A HSMC Port A HSMC Port B JTAG Header JTAG Control DIP Switch Jumper Table 2 7 JTAG Settings 1 Number Description FPGA Bypass SW1 1 HSMA Bypass SW1 2 HSMB Bypass SW1 3 MAX Enable SW1 4 PFL Enable SW2 5 5 Device Select DEV_SEL Jumper J2 1 Embedded USB Blaster 2 3 Stratix III targe...

Page 27: ...the configuring from flash memory feature Flash Programming over USB Interface You can program the flash memory at any time the board is powered up using the USB 2 0 interface and the Quartus II Programmer s JTAG mode The development kit implements the Altera PFL megafunction for flash programming The PFL is a block of logic that is programmed into an Altera programmable logic device FPGA or CPLD ...

Page 28: ...HY Driven by the Marvell 88E1111 PHY D15 ENET RX Illuminates when receive data is active from the Ethernet PHY Driven by the Marvell 88E1111 PHY D6 10 MBytes Illuminates when Ethernet PHY is using the 10 Mbps connection speed Driven by the Marvell 88E1111 PHY D7 100 MBytes Illuminates when Ethernet PHY is using the 100 Mbps connection speed Driven by the Marvell 88E1111 PHY D8 1000 MBytes Illumina...

Page 29: ...rence SW1 is a four position JTAG control DIP switch provided to either remove or include devices in the active JTAG chain Additionally the JTAG control DIP switch is also used to disable the embedded USB Blaster cable when using an external USB Blaster cable Table 2 10 lists the switch position name and description Table 2 9 Board Specific LEDs Component Reference and Manufacturing Information Bo...

Page 30: ...in only if installed 0 HSMC Port B not in JTAG chain 4 MAX_ENABLE 1 MAX II device disabled 0 MAX II device enabled Table 2 10 JTAG Control DIP Switch Signal Names and Descriptions Part 2 of 2 DIP Switch Signal Name Description Table 2 11 JTAG Control Switch Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number SW1 Four position slider ...

Page 31: ...to the MAX II device The FACTORY_CONFIG pin forces a reconfiguration of the FPGA with the factory default FPGA design which is located at the base of flash memory See Table 2 14 Table 2 15 lists the push button switch component reference and manufacturing information For information about user defined push buttons refer to User Defined Push Button Switches on page 2 28 Power Select Rotary Switch A...

Page 32: ...y Switch Number Name Pin and Description Number Schematic Signal Name Power Pin Name Description 0 VCCL VCCL FPGA core voltage power 1 1 1V_VCC VCC FPGA I O registers power 2 2 5V_A VCCA VCCPT FPGA analog power programmable power technology 3 2 5V_VCCPD VCCPD FPGA I O pre driver power 4 2 5V_VCCPGM VCCPGM FPGA configuration pins power 5 6 1 8 V_S3 VCCIO 1A 1C 3A 3B 3C 4B 4C 8A 8B 8C FPGA I O power...

Page 33: ...ems High speed clock oscillators 50 MHz FPGA PLL input 125 MHz FPGA PLL input 125 MHz MAX II CPLD input 24 MHz MAX II CPLD input Reference clocks 6 MHz USB PHY reference clock FTDI device 24 MHz USB PHY reference clock Cypress device 25 MHz Ethernet PHY reference clock SMA connectors for clocking input and output signals Table 2 18 PGM Config Select Rotary Switch Component Reference and Manufactur...

Page 34: ...II CPLD and HSMC ports Figure 2 7 Stratix III FPGA Clock Inputs Bank 8C 1 8 V CLK14N CLKIN_125 CLK14P CLK15N CLK15P CLK12N CLK12P CLK13N CLK13P CLK5N CLK5P CLK4N CLK4P CLK7N CLK7P CLK6N CLK6P CLK1N CLK1P USB_IFCLK 500 MHz CLK0N CLK0P CLK3N CLK3P CLK2N CLK2P ENET_S_CLKP ENET_S_CLKN CLK11N CLK11P CLK10N CLK10P CLK8N CLK8P CLK9N CLK9P Bank 7C 1 5 V Bank 3C 1 8 V Bank 4C 1 8 V Bank 6C 2 5 V Bank 5C 2 ...

Page 35: ..._N DDR2_DEVB_CK_N DDR2 DIMM DDR2_DIMM_CLK_N2 DDR2_DIMM_CLK_N2 DDR2_DIMM_CLK_N2 DDR2_DIMM_CLK_N2 DDR2_DIMM_CLK_N2 DDR2_DIMM_CLK_N2 HSMB_CLK_OUT_N2 HSMB_CLK_OUT_P2 HSMB_CLK_OUT_N1 HSMB_CLK_OUT_P1 HSMC Port B HSMA_CLK_OUT_N2 HSMA_CLK_OUT_P2 HSMA_CLK_OUT_N1 HSMA_CLK_OUT_P1 HSMC Port A Table 2 19 Stratix III Development Board Clocking Parts List Board Reference Description Manufacturer Manufacturer Par...

Page 36: ...itches on page 2 23 Board references S2 through S5 are push button switches allowing user interactions with the Stratix III device When the switch is pressed and held down the device pin is set to a logic 0 when the switch is released the device pin is set to a logic 1 There is no board specific function for these four push button switches Table 2 20 Stratix III Development Board Clock Distributio...

Page 37: ...tton Switch Signal Names and Functions Board Reference Description Schematic Signal Name Stratix III Device Pin Number Other Connections S2 User defined push button USER_PB3 K17 S3 User defined push button USER_PB2 A16 S4 User defined push button USER_PB1 A17 S5 User defined push button USER_PB0 B17 S6 User defined push button CPU_RESET AP5 U5 pin M9 Note to Table 2 21 1 The pull up resistors for ...

Page 38: ...ng Stratix III device pin number SW5 pin 7 User defined DIP switch pin 7 USER_DIPSW6 1 8 V L19 SW5 pin 8 User defined DIP switch pin 8 USER_DIPSW7 1 8 V L20 Table 2 23 User Defined DIP Switch Pin Out SW5 Part 2 of 2 Board Reference Description Schematic Signal Name I O Standard Stratix III Device Pin Number Table 2 24 User Defined DIP Switch Component Reference and Manufacturing Information Board ...

Page 39: ...7 segment display Power 7 segment display Table 2 26 General User Defined LED Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Website D20 D27 Green LEDs 1206 SMT clear lens 2 1 V Lumex Inc SML LX1206GC TR www lumex com Table 2 27 HSMC User Defined LEDs Board Reference Description Schematic Signal Name I O Standard St...

Page 40: ...d display signal SEVEN_SEG_C 2 5 V AC12 U28 pin 8 User defined display signal SEVEN_SEG_D 2 5 V AM5 U28 pin 9 User defined display signal SEVEN_SEG_E 2 5 V AF11 U28 pin 7 User defined display signal SEVEN_SEG_F 2 5 V AM6 U28 pin 5 User defined display signal SEVEN_SEG_G 2 5 V AP3 U28 pin 2 User defined display signal SEVEN_SEG_DP 2 5 V AK6 U28 pin 13 User defined display signal SEVEN_SEG_MINUS 2 5...

Page 41: ... so it can be easily removed for access to components under the display or to use the header for debugging or other purposes Table 2 32 summarizes the character LCD interface pins Signal name and direction are relative to the Stratix III FPGA For functional descriptions see Table 2 33 Table 2 31 Power 7 Segment Display Component Reference and Manufacturing Information Board Reference Description M...

Page 42: ... The particular model used does not have a backlight and the LCD drive pin is not connected Table 2 33 Character LCD Display Pin Definitions Pin Number Symbol Level Function 1 VDD Power supply 5 V 2 VSS GND 0V 3 V0 For LCD drive 4 RS H L Register select signal H Data input L Instruction input 5 R W H L H Data read module to MPU L Data write MPU to module 6 E H H to L Enable 7 14 DB0 DB7 H L Data b...

Page 43: ...nal name and direction are relative to the Stratix III FPGA Figure 2 11 LCD Display Dimensions 15 24 0 600 P2 54 x 7 24 00 0 945 30 00 0 50 1 18 0 020 24 00 0 945 16 00 0 630 V A 2 54 0 100 13 14 11 50 0 453 3 00 0 118 7 38 0 291 REF 1 2 A K 2 00 0 079 85 00 0 50 3 346 0 020 _ _ 71 20 2 803 81 00 3 189 66 00 2 598 V A 56 21 2 213 4 325 1 703 14 1 00 0 039 PAD 1 80 0 071 Ο Ο Ο Ο 1 00 0 039 5 PLS Ο ...

Page 44: ...hip is from New Japan Radio Corporation part number NJU6676 J24 pin 10 LCD data bus bit 4 OLED_DATA4 2 5 V AL32 J24 pin 11 LCD data bus bit 5 OLED_DATA5 2 5 V AB30 J24 pin 12 LCD data bus bit 6 or SCLK OLED_DATA6 2 5 V AC26 J24 pin 13 LCD data bus bit 7 or SDATA OLED_DATA7 2 5 V AA30 J24 pin 28 Parallel interface selection high 68 series low 80 series OLED_BS1 2 5 V Y26 J24 pin 1 LCD chip select O...

Page 45: ... 65 X 132 8 580 bit Display Data Latch Low Address Deocder Line Address Deocder Column Address Decoder Vss VDD Oscillator Bus Holder Busy Flag Instruction Decoder Status Voltage Followers Voltage Regulator Voltage Converter Multiplexer Line Counter Initial Display Line Common Direction Page Address Register Column Address Counter Column Address Register MPU Interface Reset Common Timing Display Ti...

Page 46: ...rence and manufacturing information Figure 2 13 Graphics LCD Timing Diagram A0 CS1 D0 D7 Write D0 D7 Read WR RD t CYC8 t CCH W R t CCL W R tAW8 tAH8 tDS8 tACC8 tOH8 tDH8 t f t r Table 2 36 Graphics LCD Display Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Website J24 FPC FFC 30 position flick lock connector bottom ...

Page 47: ... Nios II JTAG universal asynchronous receiver transmitter UART f For more information about the data sheet and related documentation contact FTDI at www ftdichip com Table 2 38 lists the FTDI USB interface component reference and manufacturing information 10 100 1000 Ethernet A Marvell 88E1111 device is used for 10 100 1000 base T Ethernet connection The device is an auto negotiating Ethernet PHY ...

Page 48: ...25 Pin Out Part 1 of 2 Board Reference Description Schematic Signal Name I O Standard Stratix III Pin Number U25 pin 8 RGMII interface transmit clock ENET_GTX_CLK 2 5 V AB33 U25 pin 23 Management bus interrupt ENET_INTn 2 5 V AB32 U25 pin 73 1000 MBytes link established ENET_LED_LINK1000 2 5 V A28 U25 pin 25 Management bus data clock ENET_MDC 2 5 V Y2 U25 pin 24 Management bus data ENET_MDIO 2 5 V...

Page 49: ...T_RX_P LVDS AA33 U25 pin 80 SGMII interface 625 MHz clock ENET_S_CLKN LVDS W34 U25 pin 79 SGMII interface 625 MHz clock ENET_S_CLKP LVDS W33 U25 pin 4 MII interface 25 MHz clock ENET_TX_CLK 2 5 V AB34 U25 pin 11 RGMII interface transmit data bus bit 0 ENET_TX_D 0 2 5 V AF28 U25 pin 12 RGMII interface transmit data bus bit 1 ENET_TX_D 1 2 5 V AD34 U25 pin 14 RGMII interface transmit data bus bit 2 ...

Page 50: ...shown in Figure 2 16 The HSMC interface has programmable bi directional I O pins that can be used as 2 5 V LVCMOS which is 3 3 V LVTTL compatible These pins can also be used as various differential I O standards including but not limited to LVDS mini LVDS and RSDS with up to 17 channels full duplex 1 As noted in the HSMC specification LVDS and single ended I O standards are only guaranteed to func...

Page 51: ...output HSMA_JTAG_TDO 2 5 V N A J18 pin 38 JTAG data input HSMA_JTAG_TDI 2 5 V N A J18 pin 39 Dedicated CMOS clock out HSMA_CLK_OUT0 2 5 V AD28 J18 pin 40 Dedicated CMOS clock in HSMA_CLK_IN0 2 5 V W10 J18 pin 41 Dedicated CMOS I O bit 0 HSMA_D0 2 5 V AK9 J18 pin 42 Dedicated CMOS I O bit 1 HSMA_D1 2 5 V AJ9 J18 pin 43 Dedicated CMOS I O bit 2 HSMA_D2 2 5 V AL7 J18 pin 44 Dedicated CMOS I O bit 3 H...

Page 52: ...in HSMA_CLK_IN_N1 LVDS or 2 5 V W3 J18 pin 101 LVDS TX or CMOS I O bit 8 HSMA_TX_P8 LVDS or 2 5 V AC6 J18 pin 102 LVDS RX or CMOS I O bit 8 HSMA_RX_P8 LVDS or 2 5 V AF2 J18 pin 103 LVDS TX or CMOS I O bit 8 HSMA_TX_N8 LVDS or 2 5 V AC5 J18 pin 104 LVDS RX or CMOS I O bit 8 HSMA_RX_N8 LVDS or 2 5 V AF1 J18 pin 107 LVDS TX or CMOS I O bit 9 HSMA_TX_P9 LVDS or 2 5 V AB6 J18 pin 108 LVDS RX or CMOS I ...

Page 53: ...n 151 LVDS TX or CMOS I O bit 16 HSMA_TX_N16 LVDS or 2 5 V AB11 J18 pin 152 LVDS RX or CMOS I O bit 16 HSMA_RX_N16 LVDS or 2 5 V Y3 J18 pin 155 LVDS or CMOS clock out HSMA_CLK_OUT_P2 LVDS W8 J18 pin 156 LVDS or CMOS clock in HSMA_CLK_IN_P2 LVDS T2 J18 pin 157 LVDS or CMOS clock out HSMA_CLK_OUT_N2 2 5 V W7 J18 pin 158 LVDS or CMOS clock in HSMA_CLK_IN_N2 2 5 V T1 N A User LED intended to show RX d...

Page 54: ...r CMOS I O bit 4 HSMB_TX_P4 LVDS or 2 5 V R10 J8 pin 72 LVDS RX or CMOS I O bit 4 HSMB_RX_P4 LVDS or 2 5 V M1 J8 pin 73 LVDS TX or CMOS I O bit 4 HSMB_TX_N4 LVDS or 2 5 V R9 J8 pin 74 LVDS RX or CMOS I O bit 4 HSMB_RX_N4 LVDS or 2 5 V N1 J8 pin 77 LVDS TX or CMOS I O bit 5 HSMB_TX_P5 LVDS or 2 5 V R7 J8 pin 78 LVDS RX or CMOS I O bit 5 HSMB_RX_P5 LVDS or 2 5 V L2 J8 pin 79 LVDS TX or CMOS I O bit ...

Page 55: ... pin 128 LVDS RX or CMOS I O bit 12 HSMB_RX_N12 LVDS or 2 5 V E1 J8 pin 131 LVDS TX or CMOS I O bit 13 HSMB_TX_P13 LVDS or 2 5 V K8 J8 pin 132 LVDS RX or CMOS I O bit 13 HSMB_RX_P13 LVDS or 2 5 V C1 J8 pin 133 LVDS TX or CMOS I O bit 13 HSMB_TX_N13 LVDS or 2 5 V K7 J8 pin 134 LVDS RX or CMOS I O bit 13 HSMB_RX_N13 LVDS or 2 5 V D1 J8 pin 137 LVDS TX or CMOS I O bit 14 HSMB_TX_P14 LVDS or 2 5 V L8 ...

Page 56: ...on refer to AN 435 Using DDR and DDR2 SDRAM in Stratix III and Stratix IV Devices AN 438 Constraining and Analyzing Timing for External Memory Interfaces in Stratix III and Cyclone III Devices N A User LED intended to show RX Data activity on the HSMC HSMB_RX_LED 2 5 V AJ12 N A User LED intended to show TX Data activity on the HSMC HSMB_TX_LED 2 5 V AG34 Table 2 42 HSMC Port B Interface Signal Nam...

Page 57: ...R2_DIMM_A0 SSTL 18 class I AM19 J19 pin 183 Address bit 1 DDR2_DIMM_A1 SSTL 18 class I AM18 J19 pin 63 Address bit 2 DDR2_DIMM_A2 SSTL 18 class I AF16 J19 pin 182 Address bit 3 DDR2_DIMM_A3 SSTL 18 class I AN16 J19 pin 61 Address bit 4 DDR2_DIMM_A4 SSTL 18 class I AM17 J19 pin 60 Address bit 5 DDR2_DIMM_A5 SSTL 18 class I AL19 J19 pin 180 Address bit 6 DDR2_DIMM_A6 SSTL 18 class I AK18 J19 pin 58 ...

Page 58: ...3 DDR2_DIMM_DQ13 SSTL 18 class I AE15 J19 pin 140 Data bit 14 DDR2_DIMM_DQ14 SSTL 18 class I AP9 J19 pin 141 Data bit 15 DDR2_DIMM_DQ15 SSTL 18 class I AN10 J19 pin 24 Data bit 16 DDR2_DIMM_DQ16 SSTL 18 class I AN12 J19 pin 25 Data bit 17 DDR2_DIMM_DQ17 SSTL 18 class I AM12 J19 pin 30 Data bit 18 DDR2_DIMM_DQ18 SSTL 18 class I AG15 J19 pin 31 Data bit 19 DDR2_DIMM_DQ19 SSTL 18 class I AH15 J19 pin...

Page 59: ...9 pin 218 Data bit 53 DDR2_DIMM_DQ53 SSTL 18 class I AL29 J19 pin 226 Data bit 54 DDR2_DIMM_DQ54 SSTL 18 class I AJ29 J19 pin 227 Data bit 55 DDR2_DIMM_DQ55 SSTL 18 class I AJ27 J19 pin 110 Data bit 56 DDR2_DIMM_DQ56 SSTL 18 class I AF24 J19 pin 111 Data bit 57 DDR2_DIMM_DQ57 SSTL 18 class I AG24 J19 pin 116 Data bit 58 DDR2_DIMM_DQ58 SSTL 18 class I AF23 J19 pin 117 Data bit 59 DDR2_DIMM_DQ59 SST...

Page 60: ...19 pin 195 On die termination control bit 0 DDR2_DIMM_ODT0 SSTL 18 class I AE19 J19 pin 77 On die termination control bit 1 DDR2_DIMM_ODT1 SSTL 18 class I AD19 J19 pin 52 Clock enable bit 0 DDR2_DIMM_CKE0 SSTL 18 class I AJ16 J19 pin 171 Clock enable bit 1 DDR2_DIMM_CKE1 SSTL 18 class I AP7 J19 pin 186 Differential output clock 0 DDR2_DIMM_CLK_N0 SSTL 18 class I AM14 J19 pin 138 Differential outpu...

Page 61: ... G34 U17 pin H7 Address bit 2 DDR2_DEVA_A2 SSTL 18 class I U22 G31 U17 pin J2 Address bit 3 DDR2_DEVA_A3 SSTL 18 class I U22 N24 U17 pin J8 Address bit 4 DDR2_DEVA_A4 SSTL 18 class I U22 L29 U17 pin J3 Address bit 5 DDR2_DEVA_A5 SSTL 18 class I U22 M30 U17 pin J7 Address bit 6 DDR2_DEVA_A6 SSTL 18 class I U22 L31 U17 pin K2 Address bit 7 DDR2_DEVA_A7 SSTL 18 class I U22 P25 U17 pin K8 Address bit ...

Page 62: ...9 On die termination control pin DDR2_DEVA_ODT SSTL 18 class I U22 M28 Table 2 47 DDR2 Device A Interface I O Part 2 of 2 Board Reference Description Schematic Signal Name I O Standard Stratix III Pin Number Table 2 48 DDR2 SDRAM Devices A and B Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Website U17 U20 333 MHz ...

Page 63: ...20 pin G1 Bank address bit 2 DDR2_DEVB_BA2 SSTL 18 class I U22 R30 U20 pin C8 Data bit 0 DDR2_DEVB_DQ0 SSTL 18 class I U22 P29 U20 pin C2 Data bit 1 DDR2_DEVB_DQ1 SSTL 18 class I U22 P32 U20 pin D7 Data bit 2 DDR2_DEVB_DQ2 SSTL 18 class I U22 N30 U20 pin D3 Data bit 3 DDR2_DEVB_DQ3 SSTL 18 class I U22 N31 U20 pin D1 Data bit 4 DDR2_DEVB_DQ4 SSTL 18 class I U22 R26 U20 pin D9 Data bit 5 DDR2_DEVB_D...

Page 64: ...J15 U15 pin P5 Address bit 9 QDRII_A9 1 5 V HSTL class I G16 U15 pin P7 Address bit 10 QDRII_A10 1 5 V HSTL class I E14 U15 pin P8 Address bit 11 QDRII_A11 1 5 V HSTL class I B14 U15 pin R3 Address bit 12 QDRII_A12 1 5 V HSTL class I J16 U15 pin R4 Address bit 13 QDRII_A13 1 5 V HSTL class I H16 U15 pin R5 Address bit 14 QDRII_A14 1 5 V HSTL class I F12 U15 pin R7 Address bit 15 QDRII_A15 1 5 V HS...

Page 65: ... HSTL class I J12 U15 pin D3 Read data bit 10 QDRII_Q10 1 5 V HSTL class I J11 U15 pin E3 Read data bit 11 QDRII_Q11 1 5 V HSTL class I G8 U15 pin F2 Read data bit 12 QDRII_Q12 1 5 V HSTL class I G11 U15 pin G3 Read data bit 13 QDRII_Q13 1 5 V HSTL class I B2 U15 pin K3 Read data bit 14 QDRII_Q14 1 5 V HSTL class I B5 U15 pin L2 Read data bit 15 QDRII_Q15 1 5 V HSTL class I F6 U15 pin N3 Read data...

Page 66: ...ce for 2M 18 Cypress Semiconductor CY7C1263V18 400BZXCES www cypress com Table 2 52 P SRAM Device Pin Out Part 1 of 4 Board Reference Description Schematic Signal Name I O Standard StratixIII Device Pin Number Other Connections U4 and U10 pin A3 Address bus shared with flash and P SRAM bit 1 FSM_A1 1 8 V H23 U5 pin T8 and U9 pin B1 U4 and U10 pin A4 Address bus shared with flash and P SRAM bit 2 F...

Page 67: ...nd U10 pin G2 Address bus shared with flash and P SRAM bit 20 FSM_A20 1 8 V B29 U5 pin M1 and U9 pin C8 U4 and U10 pin H6 Address bus shared with flash and P SRAM bit 21 FSM_A21 1 8 V C29 U5 pin R14 and U9 pin A8 U4 pin B6 Data bus shared with flash and P SRAM bit 0 FSM_D0 1 8 V G27 U5 pin P4 and U9 pin E4 U4 pin C5 Data bus shared with flash and P SRAM bit 1 FSM_D1 1 8 V F28 U5 pin R1 and U9 pin ...

Page 68: ...10 pin D5 Data bus shared with flash and P SRAM bit 19 FSM_D19 1 8 V J22 U5 pin R7 U10 pin E5 Data bus shared with flash and P SRAM bit 20 FSM_D20 1 8 V J21 U5 pin P8 U10 pin F5 Data bus shared with flash and P SRAM bit 21 FSM_D21 1 8 V C24 U5 pin T7 U10 pin F6 Data bus shared with flash and P SRAM bit 22 FSM_D22 1 8 V E25 U5 pin N8 U10 pin G6 Data bus shared with flash and P SRAM bit 23 FSM_D23 1...

Page 69: ... E20 U10 pin B2 Byte write select bit 3 SRAM_BEn3 1 8 V H20 U10 and U4 pin J2 Clock SRAM_CLK 1 8 V C21 U10 and U4 pin B5 Chip select SRAM_CSn 1 8 V A21 U10 and U4 pin A2 Output enable SRAM_OEn 1 8 V A22 U10 and U4 pin A6 Power save mode SRAM_PSn 1 8 V AL18 U4 pin J1 Data wait SRAM_WAIT0 1 8 V G20 U10 pin J1 Data wait SRAM_WAIT1 1 8 V F20 U10 and U4 pin G5 Write enable SRAM_WEn 1 8 V B22 Table 2 52...

Page 70: ... to 80 MHz Up to 104 MHz Fixed Variable Fixed Variable Fixed Variable Latency set A11 A10 A9 4 0 0 1 2 1 0 0 5 0 1 0 3 0 0 0 7 1 0 1 4 0 0 1 Read latency min 4 2 4 5 3 5th 7 4 7 First read data fetch clock 5th 3rd 5th 6th 4th 6th 8th 5th 8th Write latency min 2 2 3 3 4 4 First write data loading clock 3rd 3rd 3rd 4th 5th 5th Figure 2 18 SRAM Read Timing Waveforms 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14...

Page 71: ...and U10 pin A3 and U5 pin T8 U9 pin C1 Address bus shared with flash and P SRAM bit 2 FSM_A2 1 8 V G23 U5 pin T9 and U4 pin A4 and U10 pin A4 and U5 pin T9 U9 pin D1 Address bus shared with flash and P SRAM bit 3 FSM_A3 1 8 V F23 U5 pin R9 and U4 pin A5 and U10 pin A5 and U5 pin R9 U9 pin D2 Address bus shared with flash and P SRAM bit 4 FSM_A4 1 8 V D27 U5 pin P9 and U4 pin B3 and U10 pin B3 and ...

Page 72: ...21 FSM_A21 1 8 V C29 U5 pin R14 and U4 pin H6 and U10 pin H6 and U5 pin R14 U9 pin G1 Address bus shared with flash and P SRAM bit 22 FSM_A22 1 8 V C31 U5 pin N12 U9 pin H8 Address bus shared with flash and P SRAM bit 23 FSM_A23 1 8 V D31 U5 pin T15 U9 pin B6 Address bus shared with flash and P SRAM bit 24 FSM_A24 1 8 V F27 U5 pin P12 U9 pin F2 Data bus shared with flash and P SRAM bit 0 FSM_D0 1 ...

Page 73: ... 8 V A25 U5 pin P7 and U4 pin E2 U9 pin H5 Data bus shared with flash and P SRAM bit 13 FSM_D13 1 8 V J20 U5 pin T5 and U4 pin F2 U9 pin G7 Data bus shared with flash and P SRAM bit 14 FSM_D14 1 8 V K20 U5 pin N7 and U4 pin F1 U9 pin E7 Data bus shared with flash and P SRAM bit 15 FSM_D15 1 8 V K21 U5 pin R6 and U4 pin G1 U9 pin E6 Clock FLASH_CLK 1 8 V K24 U5 pin L15 U9 pin F6 Address valid FLASH...

Page 74: ...Factory design Table 2 57 Flash Sector Map Top and Bottom Parameter Dies Die Stack Configuration Size KBytes 512 Mbit Flash 2 256 Mbits with 1 CE Block Address Range 256 Mbit Top Parameter Die 32 517 1FFC000 1FFFFFF 32 514 1FF0000 1FF3FFF 128 513 1FE0000 1FEFFFF 128 259 1000000 100FFFF 256 Mbit Bottom Parameter Die 128 258 770000 77FFFF 760000 76FFFF 128 4 32 3 010000 01FFFF 000000 00FFFF 32 0 Tab...

Page 75: ...Partial Plane QDRII VDDQ Partial Plane RMEASURE Partial Plane FPGA VCCPD 1 1V Partial Plane ENET PHY DVDD Partial Plane FPGA VCC FPGA_VCCD_PLL 1 8V RMEASURE 1 8V RMEASURE Partial Plane 1 8V 1 8V Partial Plane DIMM VDD VDDQ Partial Plane DEV VDD VDDQ 1 8V Partial Plane QDRII VDD Power Net R MEASURE 1 1V VCCL Partial Plane FPGA VCCL VREF_DIMM 0 9V VIN VVLDOIN VTT _DIMM Power Net DIMM Termination Res...

Page 76: ... subnet is named then the power is the total output power for that voltage Table 2 59 Power Measurement Rails Number Measured Net Name Power Pin Name Description 1 VCCL VCCL FPGA core power 2 1 1V_VCC VCC FPGA I O registers power VCCD_PLL FPGA PLL digital power 3 2 5V_A VCCPT FPGA programmable power technology VCCA_PLL FPGA PLL analog power 4 2 5V_VCCPD VCCPD Pre driver power for I Os 5 2 5V_VCCPG...

Page 77: ...stored on the Stratix III device and is used to decrypt the incoming configuration data bit stream before configuration and initialization can begin This section discusses the following two methods of storing Stratix III device s 256 bit encryption key Volatile Non volatile In the volatile scheme the 256 bit key itself can be reprogrammed as needed In this case a 2 5 V battery is required to power...

Page 78: ...rominated biphenyls PBB Polybrominated diphenyl Ethers PBDE Stratix III development board X 0 0 0 0 0 12 V power supply 0 0 0 0 0 0 Type A B USB cable 0 0 0 0 0 0 User guide 0 0 0 0 0 0 Notes to Table 2 60 1 0 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the SJ T11363 2006 standard 2 X indicates that the co...

Page 79: ...tratix III pin numbers for DDR2_DEVB_DQ2 and DDR2_DEVB_DQ3 signals in Table 2 49 Updated the document template November 2008 1 4 Updated QDRII interface pin information in Table 2 50 November 2008 1 3 Updated DDR2 DIMM board memory size Updated Stratix III pin numbers for the differential output clock signals in Table 2 45 August 2008 1 2 Updated JTAGS settings in Table 2 7 Updated Power Select Ro...

Page 80: ... chiptrip gdf file Italic Type with Initial Capital Letters Indicate document titles For example Stratix IV Design Guidelines italic type Indicates variables For example n 1 Variable names are enclosed in angle brackets For example file name and project name pof file Initial Capital Letters Indicate keyboard keys and menu names For example the Delete key and the Options menu Subheading Title Quota...

Page 81: ...ia presentation c A caution calls attention to a condition or possible situation that can damage or destroy the product or your work w A warning calls attention to a condition or possible situation that can cause you injury The envelope links to the Email Subscription Management Center page of the Altera website where you can sign up to receive update notifications for Altera documents The feedbac...

Page 82: ...Info 4 Additional Information Typographic Conventions Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual ...

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