Altera Stratix II GX EP2SGX90 Reference Manual Download | Manualshive

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Altera Corporation

Reference Manual

2–13

May 2006

Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board

Board Components & Interfaces

Figure 2–6. SMA Connector Block Diagram

lists transceiver block’s transmit and receive signals,

corresponding SMA reference designators and FPGA pins.

Transcei

v

er Block 1

1 Channel

Transcei

v

er Block 2

4 Channels

Transcei

v

er Block 3

1 Channel

Stratix II GX Device
Transceiver Block

TX: 40 inch trace length

SMA Connectors

(J27, J2

8

)

(J29, J26)

(J43, J45)

(J42, J44)

(J39, J40)

(J3

8

, J41)

(J32, 33)

(J30, J31)

(J36, J37)

(J34, 35)

(J47, J4

8

)

(J49, J46)

Table 2–8. Transceiver Block Corresponding Signals, SMA Designator, and
FPGA Pin (Part 1 of 2)

Block

Signal

SMA Reference

Designator

Stratix II GX Pin

Transceiver Block 1,
1 Channel

TX_P0

J27

A4

TX_N0

J28

A5

RX_P0

J29

C1

RX_N0

J26

C2

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Summary of Contents for Stratix II GX EP2SGX90

Page 1: ...Drive San Jose CA 95134 408 544 7000 www altera com Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board Reference Manual Development Board Version 1 0 0 Document Version 1 0 0 Document Date May 2006 ...

Page 2: ...s performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the ap plication or use of any information product or service described herein except as expressly agreed to in writing by Alter...

Page 3: ...2 9 ICS557 03 U5 Spread Spectrum Clock Generator for PCI Express 2 10 ICS8543 U8 General Purpose 1 4 Differential Fanout Buffer 2 11 ICS83023 U7 Differential I O to Single Converter for Trigger Clock 2 11 Interfaces 2 12 SMA Connectors for High Speed I O 2 12 USB Interface 2 14 General User Interfaces 2 16 Debug Header J1 2 16 LEDs D1 Through D8 2 18 7 Segment Displays D9 D10 2 19 Push Button Swit...

Page 4: ...iv Altera Corporation Preliminary May 2006 Contents Stratix II GX EP2GX90 Signal Integrity Development Board Reference Manual ...

Page 5: ...al support on this product go to www altera com mysupport For additional information about Altera products consult the sources shown below Chapter Date Version Changes Made All May 2006 1 0 0 First publication Information Type USA Canada All Other Locations Technical support www altera com mysupport www altera com mysupport 800 800 EPLD 3753 7 00 a m to 5 00 p m Pacific Time 1 408 544 8767 7 00 a ...

Page 6: ...nces to sections within a document and titles of on line help topics are shown in quotation marks Example Typographic Conventions Courier type Signal and port names are shown in lowercase Courier type Examples data1 tdi input Active low signals are denoted by suffix n e g resetn Anything that must be typed exactly as it appears is shown in Courier type For example c qdesigns tutorial chiptrip gdf ...

Page 7: ... to maintain signal integrity In fact increasing data rates for both I O interfaces and memory interfaces can present significant data transmission problems and performance issues The Stratix II GX device s embedded transceivers provide enhanced transmit pre emphasis technology that conditions the signal prior to transmission as well as programmable receiver equalization circuitry Also because the...

Page 8: ...ntial output and six channels of receive differential input at up to 6 375 Gbps Power supply management 5 V 3 3 V and 1 2 V switching regulators 3 3 V and 1 5 V 1 2 V linear regulators USB interface Operates like a COM port on a host PC Eliminates the need for Full USB software and hardware implementation USB software driver General user interface Debugging header LEDs 7 Segment LEDs Push buttons ...

Page 9: ...y De coupling Quartus II software transceiver architecture and Altera MegaWizard Plug In Manager demonstrations supporting devices and interfaces included Demonstrating Stratix II GX device transceiver features Characterization testing of high speed serial interfaces Interoperability testing between various devices via on board SMA connectors Power supply evaluation on board regulation and banana ...

Page 10: ...scharge Precaution Without proper anti static handling the board can be damaged Therefore use anti static handling precautions when touching the board Table 1 1 Board Protocol Support Protocol Data Rate Gbps Clock Frequency MHz Clock Source 6G CEI 6 25 156 25 On board oscillator 5G scrambled 5 156 25 On board oscillator 4G FC 1 4 25 SMA clock input XAUI 3 125 156 25 On board oscillator PCI Express...

Page 11: ...upply Thermal management FPGA configuration Flash memory 1 Board schematics the physical layout database and manufacturing files for the Stratix II GX EP2SGX90 transceiver signal integrity development board are included in the Transceiver SI Development Kit Stratix II GX Edition in the following directory install path SIIGX_SI_Kit v1 0 0 Docs BoardDesignFiles f For information on powering up the S...

Page 12: ...ock Generator U5 Differential Fan out Buffer U8 Differential to Single Ended Buffer U7 156 25 MHz Oscillator U9 25 MHz Crystal U6 EPCS64 Device U22 16 Mbytes Flash Memory U19 USB Connector J2 USB Interface U2 Temperature Sensor with Alarm U17 SMA Transmit Receive Connectors J26 through J49 Power Supply Input 10 pin Configuration Header for EPCS64 Device J23 10 pin JTAG Configuration Header for FPG...

Page 13: ...iver Signal Integrity Development Board Board Components Interfaces Figure 2 2 shows the diagonal view of the Stratix II GX EP2SGX90 transceiver signal integrity development board Figure 2 2 Diagonal View of the Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board ...

Page 14: ... 25 MHZ oscillator and the SMA external clock inputs to supply the clocks to the three quad transceivers 2 24 I O DIP switch S8 Eight toggle DIP switches for selecting PCIe clock speed PCIe clock spread spectrum setting and the output enable of the clocks to the three quad transceivers 2 22 Debugging Interfaces I O Debug header J1 A twenty pin connector that is connected to 20 general I Os on the ...

Page 15: ...r 2 9 Buffer Clock U7 Differential to single ended converter for providing trigger clocks 2 9 Input SMA external clock input connectors J5 J6 SMA connectors for providing an external clock to the three quad transceivers 2 12 Output SMA trigger clock connector J3 SMA connector for the PCIe trigger clock 2 12 Output SMA trigger clock connector J4 SMA connector for the basic trigger clock associated ...

Page 16: ...thermal management i e turning the cooling fan on and off to regulate the FPGA temperature 2 25 Table 2 1 Stratix II GX Transceiver SI Development Board Components Interfaces Part 3 of 3 Type Component Interface Board Reference Description Page Table 2 2 Stratix II GX Features Architectural Feature Results Altera s third generation FPGA with embedded transceivers Provides a robust design solution ...

Page 17: ...ed transceivers enhanced PLLs for spread spectrum and general purpose clocking and fast PLLs for high speed differential I O clocking which support the high speed interfaces described in this chapter See Figure 2 3 The clocking block is comprised of High speed clock oscillators 156 25 MHz oscillator 50 MHz oscillator 25 MHz crystal SMA connectors for clocking input and output signals Table 2 3 lis...

Page 18: ...TSSOP package 3 3V and high speed current steering logic HCSL output Part ICS557 03 Spread spectrum clock generator for PCIe clocks The integrated circuit system s ICS PLL uses a 25 MHz crystal input and produces two pairs of differential outputs at 25 MHz 100 MHz 125 MHz and 200 MHz clock frequencies The PLL also provides spread selection of 25 0 5 0 75 and no spread U7 25 MHz Differential I O to...

Page 19: ...CS8543 U8 ICS83023 U7 ICS557 03 ICS83023 refclk1 in Quad1 refclk0 in Quad2 PCI Express Trigger Clock J3 refclk1 in Quad2 refclk1 in Quad3 refclk0 in Quad1 refclk0 in Quad3 Global Clock for FPGA Block Global Clock for FPGA Block General Purpose Clocking Buffer 2 1 Multiplexer to a 1 4 LVDS Fanout Buffer U8 Spread Spectrum Clock Generator for PCI Express U5 ICS8543 50 MHz Oscillator Output Clock fro...

Page 20: ...d spread selection Using phase locked loop PLL techniques the device takes a 25 MHz crystal input and produces two pairs of differential outputs HCSL at 25 MHz 100 MHz 125 MHz and 200 MHz clock frequencies The device also provides spread selection of 0 25 0 5 0 75 and no spread Table 2 5 lists output clock DIP switch settings Table 2 6 lists spread spectrum output selection DIP switch settings Tab...

Page 21: ...termines which clock input i e clk or pclk is used the chosen signal is then converted to four output clocks See Figure 2 4 Figure 2 4 ICS8543 Clock Buffer Block Diagram ICS83023 U7 Differential I O to Single Converter for Trigger Clock The ICS83023 is a differential I O to a single ended clock buffer which is used for both the PCI Express and Basic trigger clocks See Figure 2 5 Figure 2 5 ICS8302...

Page 22: ...er signal integrity development board has SMA connectors supporting the most commonly used high speed interface protocols The SMA connectors are helpful for equipment testing The board has six channels of transmit TX differential output as well as six channels of receive RX differential input running at up to 6 375 Gbps See Figure 2 6 Table 2 7 lists the SMA to FPGA pinout table Table 2 7 SMA to F...

Page 23: ...PGA pins Transceiver Block 1 1 Channel Transceiver Block 2 4 Channels Transceiver Block 3 1 Channel Stratix II GX Device Transceiver Block TX 40 inch trace length SMA Connectors J27 J28 J29 J26 J43 J45 J42 J44 J39 J40 J38 J41 J32 33 J30 J31 J36 J37 J34 35 J47 J48 J49 J46 Table 2 8 Transceiver Block Corresponding Signals SMA Designator and FPGA Pin Part 1 of 2 Block Signal SMA Reference Designator ...

Page 24: ...are and hardware implementation In addition the USB UART design allows the software to be designed as if writing directly to the host PC s COM port which eliminates the need for designing a USB software driver see Figure 2 7 Transceiver Block 2 4 Channels TX_P4 J43 AB4 TX_N4 J45 AB5 RX_P4 J42 AB1 RX_N4 J44 AB2 TX_P3 J39 Y4 TX_N3 J40 Y5 RX_P3 J38 Y1 RX_N3 J41 Y2 TX_P2 J32 N4 TX_N2 J33 N5 RX_P2 J30 ...

Page 25: ...ion into the host PC s COM port Figure 2 7 USB Interface to Stratix II GX Transceiver Signal Integrity Development Board Table 2 9 lists the USB interface to FPGA pinout Table 2 9 USB Interface to FPGA Pinout Table USB Interface U2 Pin Number Schematic Signal Name Stratix II GX U20 Pin Number 40 UART_DATA0 F30 39 UART_DATA1 G31 38 UART_DATA2 D33 37 UART_DATA3 D32 36 UART_DATA4 H29 35 UART_DATA5 G3...

Page 26: ...eference J1 is a simple 20 pin debug header connected to the Stratix II GX device s general user I O The form factor is a dual row header such as a FCI 20 pin header Samtec TSW 110 07 G D Table 2 10 lists the schematic signal name and the corresponding Stratix II GX device pin number Table 2 10 Debug Header Pin Out Part 1 of 2 Header Number Schematic Signal Name Stratix II GX U20 Pin Number 1 D_HE...

Page 27: ...ebug header s board labels Figure 2 9 Debug Header J1 Board Labels 18 D_HED17 AB26 19 D_HED18 AB25 20 D_HED19 AD32 Table 2 10 Debug Header Pin Out Part 2 of 2 Header Number Schematic Signal Name Stratix II GX U20 Pin Number D_HED0 D_HED2 D_HED4 D_HED6 D_HED8 D_HED10 D_HED12 D_HED14 1 3 5 7 9 11 2 4 6 8 10 12 13 14 15 16 J1 Debug Header D_HED16 D_HED18 D_HED1 D_HED3 D_HED5 D_HED7 D_HED9 D_HED11 D_H...

Page 28: ...EP2SGX90 device drives logic 0 the corresponding LED illuminates Table 2 11 lists the schematic signal name and the corresponding Stratix II GX device s pin number Figure 2 10 shows a board image of the user defined LEDs Figure 2 10 User Defined LEDs Table 2 11 User Defined LED Pin Out Board Reference Schematic Signal Name Stratix II GX U20 Pin Number D1 USER_LED0 AE33 D2 USER_LED1 AE32 D3 USER_LE...

Page 29: ...ard s hardware version which simplifies board revision control To save board space the 7 segment displays are a small form factor Each segment is individually controlled by a general purpose I O pin When the EP2SGX90 FPGA pin drives logic 0 the corresponding segment illuminates See Figure 2 12 1 2 RN2 220Ω R_PACK 4 USER_LED0 USER_LED2 USER_LED3 USER_LED4 USER_LED5 USER_LED6 USER_LED7 USER_LED8 7 7...

Page 30: ...Displays Table 2 12 7 Segment Display Pin Outs Board Reference D9 Board Reference D10 Segment Display Name Schematic Signal Name Stratix II GX Pin Name Segment Display Name Schematic Signal Name Stratix II GX Pin Name A DIG_1_A W31 A DIG_2_A Y32 B DIG_1_B W30 B DIG_2_B Y31 C DIG_1_C V23 C DIG_2_C W28 D DIG_1_D W23 D DIG_2_D Y29 E DIG_1_E W33 E DIG_2_E Y34 F DIG_1_F W32 F DIG_2_F Y33 G DIG_1_G Y24 ...

Page 31: ...n as listed in Table 2 13 When the switch is pressed and held down the device pin is set to logic 0 when the switch is released the device pin is set to logic 1 The push button device is a small form factor switch similar to the Panasonic Tactile Switches EVQPAC07K Table 2 13 provides operational descriptions and schematic signal names Table 2 13 Push Button Switches S1 Through S6 Push Button Name...

Page 32: ...7 and S8 are banks of six DIP switches The DIP switches in S7 are user defined and DIP switches in S8 control the PCIe clock speed PCIe clock spread spectrum setting and the output enable of the clocks to the three quad transceivers In the open position the selected signal is driven to logic 1 In the closed position the selected signal is driven to logic 0 3V3 A B A2 B2 PB0_IN Push Button Switch C...

Page 33: ...ws the DIP switch board image Figure 2 15 DIP Switch Board Image Table 2 15 lists the S8 output clock DIP switch settings Table 2 14 User Defined DIP Switch Pinout S7 S7 Switch Stratix II GX Pin S7_1 AH33 S7_2 AH32 S7_3 AF28 S7_4 AF27 S7_5 AJ34 S7_6 AJ33 S7_7 AG29 S7_8 AG28 Table 2 15 Output Clock Setting DIP Switch Pinout S8 Switch 25 MHz 100 MHz 125 MHz 200 MHz SW1 Closed Open Closed Open SW2 Cl...

Page 34: ... The positions for these switches are labelled on the silk screen Table 2 18 lists clock selection switch settings for board reference S9 Table 2 16 Spread Spectrum Output Selection Setting S8 Switch Center 0 25 Down 0 5 Down 0 75 No Spread SW3 Closed Open Closed Open SW4 Closed Closed Open Open Table 2 17 PCIe Clock Quad Transceiver Clock DIP Switch Settings S8 PCIe Clock DIP Switch Setting Quad ...

Page 35: ...ors specifications Table 2 19 Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board Regulators Board Reference Type Voltage Output Provides Power To Manufacturer ManufacturerPart Number U12 Switching regulator 16 V to 5 V USB UART Regulators Texas Instruments PTN78020W U11 Dual output switching regulator 5 V to 3 3 V VCCIO for FPGA 7 segment display LEDs Push buttons EPCS64 device ...

Page 36: ...20 Wall AC DC Power Supply 5 V to 1 2 V Switches 5 V to 3 3 V Switches 5 V to 3 3 V Linear 5 V Parts 16 V to 5 V Switches VCCINT VCCIO and IC 3 3 V to 1 5 V Linear 3 3 V to 1 2 V Linear GXB and EPLL Clock and GXB VCCHTX Table 2 20 Power Supply Pins Maximum Current Consumption Power Supply Net Name in Schematic Power Supply Pins Connected in Stratix II GX Device Maximum Expected Current Consumption...

Page 37: ...sensor which is the Maxim MAX1619 device U17 Accordingly a SMBus interface in the PLD fabric of the Stratix II GX device is required to monitor the thermal data and potentially be an active participant with the active cooling mechanism Figure 2 17 shows the on board thermal management system diagram Figure 2 17 Stratix II GX Thermal Management System The active cooling device is similar to the Rad...

Page 38: ...r design remains in the Stratix II GX device until power is removed from the board 1 The JTAG configuration scheme bonds the JTAG ports to a set of header connections This scheme allows direct device configuration as well as support for the Altera SignalTap II embedded logic analyzer for debugging and logic probing Active Serial Configuration Using EPCS64 Device U22 The active serial configuration...

Page 39: ... Configuration Scheme f For more information about Stratix II GX configuration refer to the Configuring Stratix II and Stratix II GX Devices chapter in volume 1 of the Configuration Handbook DATA DCLK nCS ASDI DATA0 DCLK nCSO nCE nCONFIG nSTATUS MSEL n 0 nCEO CONF_DONE ASDO VCC 1 VCC 1 VCC 1 VCC 1 10 kΩ 10 kΩ 10 kΩ 10 kΩ 3 n Pin 1 N C Stratix II GX Device EPCS64 Device GND ...

Page 40: ...ring non volatile memory Useful when a smaller density but migratable device is used on the board but does not have enough internal memory to support the demo design To reduce the flash controller s development cycle a common flash interface CFI flash memory is used This provides device specific information to the system allowing host software to easily reconfigure for different flash devices On t...

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