Altera Nios II, Hardware Development Manual

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1–2 Chapter 1: Nios II Hardware Development
Software and Hardware Requirements
Nios II Hardware Development Tutorial May 2011 Altera Corporation
Figure 1–1 is a block diagram showing the relationship among the host computer, the
target board, the FPGA, and the Nios II system.
As shown in Figure 1–1 , other logic can exist within the FPGA alongside the Nios II
system. In fact, most FPGA designs with a Nios II system also include other logic. A
Nios II system can interact with other on-chip logic, depending on the needs of the
overall system. For the sake of simplicity, the design example in this tutorial does not
include other logic in the FPGA.
Software and Hardware Requirements
This tutorial requires you to have the following software:
■ Altera Quartus II software version 11.0 or later—The software must be installed on
a Windows or Linux computer that meets the Quartus II minimum requirements.
f
For system requirements and installation instructions, refer to Altera
Software Installation and Licensing .
■ Nios II EDS version 11.0 or later.
■ Design files for the design example—A hyperlink to the design files appears next
to this document on the
Literature: Nios II Processor page of the Altera website .
Figure 1–1. Tutorial Design Example
Nios II System
Character
I/O
Instr
Data
Debug
control
8
Other logic
Altera FPGA
Target Board
LED5
LED0
LED1
LED2
LED3
LED4
LED6
LED7
VCC
Clock
oscillator
System inter
connect fabric
Timer
PIO
System
ID
On-chip
RAM
Nios II/s
core
JTAG
UART
JT
A
G controller
10-pin
JTAG
header