Altera Nios II Embedded Evaluation Kit Cyclone III Edition, User Manual

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1–3 Development Board Version 1.0. Altera Corporation
Nios II Embedded Evaluation Kit, Cyclone III Edition July 2010
Kit Contents
About the Nios II Processor
Nios II is a fully configurable 32-bit processor optimized for use in
Altera’s FPGA. The embedded processor system is easily customized for
a particular application using the SOPC Builder feature of the Quartus II
FPGA design software.
Assembling a microprocessor system involves four elements:
1. Adding and configuring of the core processor and memory
2. Adding peripherals such as memory interfaces, I/O, or interfaces to
external devices (such as the LCD Display)
3. Connecting the I/O pins of the processor in the FPGA to the
external devices
4. Writing C/C++ software application for your custom processor
with the Nios II Embedded Design Suite.
In the vast majority of cases, hardware design can be accomplished using
drop-down menus and drag and drop operations in SOPC Builder. The
sophistication of Altera's designs tools brings creating custom hardware
processor systems within the reach of embedded developers.
About the Nios II Standard Design
The starter reference design for the board entitled “standard” is located in
the
altera\ < version # >\ kits\ cycloneIII_3c25_niosII\examples folder.
The Nios II “standard” is a SOPC Builder system featuring the Nios II
processor and common peripherals that has been put together for you.
Hardware designers can accelerate their SOPC Builder system
development by using the Nios II Standard design example as a starting
point. The board boots up with this pre-built design, so software
developers can use it for software development without having to
concern themselves with the details of generating the FPGA hardware
system.
The Nios II Standard System is a pre-generated hardware system that
includes:
■
Nios II core (32-bit soft processor) Application
■
LCD Controller
■
Multi-port memory controllers