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Altera Nios Cyclone II Edition, Reference Manual

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2–40

Reference Manual

Altera Corporation

Nios Development Board Cyclone II Edition

May 2007

Board Components

Figure 2–18. JTAG Connector (J24) to Cyclone II Device

Figure 2–19. USB Blaster Connected to J24 JTAG Connector

The FPGA’s JTAG pins can also be accessed via the Mictor connector (J25). 
The pins of J24 are connected directly to pins on J25, and care must be 
taken so that signal contention does not occur between the two 
connectors.

TMS

TDI

TCK

TDO

TRST

To Mictor Connector (J25) 

JTAG Signals 

JTAG Connector

(J24) 

FPGA
(U62)

Pin 1

J24

Summary of Contents for Nios Cyclone II Edition

Page 1: ...101 Innovation Drive San Jose CA 95134 www altera com Development Board Version 6XX 40020R Document Version 1 3 Document Date May 2007 Nios Development Board Cyclone II Edition Reference Manual ...

Page 2: ...nding applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the ap plication or use of any information product or service de...

Page 3: ...5 Connector RJ1 2 13 Serial Connector J19 2 15 Expansion Prototype Connectors PROTO1 PROTO2 2 16 CompactFlash Connector CON3 2 23 PMC Connector JH1 JH2 2 26 Mictor Connector J25 2 29 Test Points TP1 TP8 2 31 EPCS64 Serial Configuration Device U69 2 32 Configuration Controller Device U3 2 33 Configuration Status LEDs 2 33 Configuration Reset Buttons 2 34 SW8 CPU Reset 2 34 SW9 Factory Config 2 35 S...

Page 4: ...Appendix A Restoring the Factory Configuration Introduction A 1 Reprogramming the Flash Memory A 1 Reprogramming the EPM7256AE Configuration Controller Device A 1 Appendix B Connecting to the Board via Ethernet Introduction B 1 Connecting the Ethernet Cable B 1 Connecting the LCD Screen B 2 Obtaining an IP Address B 2 LAN Connection B 3 DHCP B 3 Static IP Address B 3 Point to Point Connections B 4...

Page 5: ...ed headers and footers June 2006 1 1 Updated part numbers to RoHS compliant parts Corrected D7 pin information in LED pin table Removed pin labels from J19 figure Added J19 pin table Changed PROTO1 and PROTO2 figures to use board net names Added PROTO1 and PROTO2 pin tables Corrected FPGA pin label for CON3 pin 9 in PMC Connector pin table Added new pin AE15 to PMC Connector pin table Added U69 pi...

Page 6: ...ple AN 75 High Speed Board Design Italic type Internal timing parameters and variables are shown in italic type Examples tPIA n 1 Variable names are enclosed in angle brackets and shown in italic type Example file name project name pof file Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters Examples Delete key the Options menu Subheading Title References to...

Page 7: ...red information that needs special consideration and understanding and should be read prior to starting or continuing with the procedure or process w The warning indicates information that should be read prior to starting or continuing the procedure or processes r The angled arrow indicates you should press the Enter key f The feet direct you to more information on a particular topic Visual Cue Me...

Page 8: ...viii Reference Manual Altera Corporation Nios Development Board Cyclone II Edition May 2007 About this Manual ...

Page 9: ...9 serial port Four push button switches connected to FPGA user I O pins Eight LEDs connected to FPGA user I O pins Dual 7 segment LED display JTAG connectors to Altera devices via Altera download cables 50 MHz oscillator and zero skew clock distribution circuitry Power on reset circuitry General Description The Nios development board comes pre programmed with a Nios II processor reference design H...

Page 10: ...s II processor design in the FPGA wakes up and begins executing boot code from flash memory The board is factory programmed with a default reference design This reference design is a web server that delivers web pages via the Ethernet port For further information on the default reference design refer to Appendix B Connecting to the Board via Ethernet Proto 2 Expansion Prototype Connector User LEDs...

Page 11: ...e course of development you might overwrite or erase the flash memory space containing the default reference design Altera provides the flash image for the default reference design so you can return the board to its default state Refer to Appendix A Restoring the Factory Configuration for more information ...

Page 12: ...1 4 Reference Manual Altera Corporation Nios Development Board Cyclone II Edition May 2007 Overview ...

Page 13: ...eset Config SW10 CON3 D0 D7 CPU Reset SW8 Factory Config SW9 Optional Power Optional Power Supply Supply Optional Power Supply PROTO1 J11 J12 J13 PROTO2 J15 J16 J17 Table 2 1 Nios Development Board Cyclone II Edition Components Interfaces Board Designation Name Description U62 Cyclone II FPGA EP2C35F672C5 or EP2C35F672C5N device User Interface SW0 SW3 Push button switches Four momentary contact sw...

Page 14: ...ector CompactFlash connector for memory expansion JH1 JH2 PMC connector Expansion connector for a PCI mezzanine card J25 Mictor connector Mictor connector providing access to 27 I O pins on the FPGA Allows debugging Nios II systems using a First Silicon Solutions FS2 debug probe TP1 TP8 Test Points Test points providing access to eight FPGA I O pins J24 JTAG connector JTAG connection to the FPGA a...

Page 15: ...button switch to reset the board LED0 LED3 LED6 Configuration status LEDs LEDs that display the current configuration status of the FPGA Clock Circuitry Y2 Oscillator 50 MHz clock signal driven to FPGA J4 External clock input Connector to FPGA clock pin Power Supply J26 DC power jack 16V DC unregulated power source D34 Bridge rectifier Power rectifier allows for center negative or center positive ...

Page 16: ...refer to Configuration Controller Device U3 on page 2 33 f For Cyclone II related documentation including pin out data for the EP2C35 device see the Altera Cyclone II literature page at www altera com literature lit cyc2 jsp Push Button Switches SW0 SW3 SW0 SW3 are momentary contact push button switches to provide stimulus to designs in the FPGA Refer to Figure 2 2 Each switch is connected to an F...

Page 17: ... drives logic 0 the corresponding LED turns on Seven Segment LEDs U8 U9 U8 and U9 connect to the FPGA and each segment is individually controlled by a general purpose I O pin Refer to Figure 2 3 When a pin drives logic 0 the corresponding U8 and U9 LED turns on See Table 2 5 for pin out details Figure 2 3 Dual Seven Segment Display Table 2 4 LED Pin Table LED FPGA Pin Board Net Name D0 AC10 pld_le...

Page 18: ...ios II embedded processor as general purpose memory The factory programmed Nios II reference design identifies the SSRAM devices in its address space as a contiguous 2 Mbyte 32 bit wide zero wait state main memory Table 2 5 Dual Seven Segment Display FPGA Pin U8 U9 Pin Pin Function Board Net Name U8 AE13 10 a hex_0A AF13 9 b hex_0B AD12 8 c hex_0C AE12 5 d hex_0D AA12 4 e hex_0E Y12 2 f hex_0F V11...

Page 19: ...A5 ssram_a5 C2 38 NC A19 ssram_a6 C3 39 NC A20 ssram_a7 L9 42 A6 ssram_a8 F7 43 A7 ssram_a9 L10 44 A8 ssram_a10 J5 45 A9 ssram_a11 L4 46 A10 ssram_a12 C6 47 A11 ssram_a13 A4 48 A12 ssram_a14 B4 49 A13 ssram_a15 A5 50 A14 ssram_a16 B5 81 A15 ssram_a17 B6 82 A16 ssram_a18 A6 99 A17 ssram_a19 C4 100 A18 ssram_a20 G9 85 ADSC_N ssram_adsc_n M3 93 BE_n0 ssram_be_n0 M2 94 BE_n1 ssram_be_n1 M4 95 BE_n2 ss...

Page 20: ...24 ssram_d16 H4 19 D25 ssram_d17 G1 22 D26 ssram_d18 G2 23 D27 ssram_d19 F2 24 D28 ssram_d20 F1 25 D29 ssram_d21 K8 28 D30 ssram_d22 K7 29 D31 ssram_d23 G4 2 D16 ssram_d24 G3 3 D17 ssram_d25 K6 6 D18 ssram_d26 K5 7 D19 ssram_d27 E2 8 D20 ssram_d28 E1 9 D21 ssram_d29 J8 12 D22 ssram_d30 J7 13 D23 ssram_d31 D5 86 OE_n ssram_oe_n J9 87 WE_n ssram_we_n D7 84 ADSP_n ssram_adsp_n H10 83 ADV_n ssram_adv_...

Page 21: ...U63 U63 is a Micron DDR SDRAM chip Depending on the board revision the part number is MT46V16M16TG or MT46V16M16P 6T The DDR SDRAM pins are connected to the FPGA as shown in Table 2 7 Altera provides a DDR SDRAM controller that allows a Nios II processor to access the DDR SDRAM device as a large linearly addressable memory K9 88 GW_n ssram_gw_n E5 89 CLK sram_clk Table 2 6 SSRAM Pin Table Continue...

Page 22: ...1 47 sdram_dm1 T6 29 sdram_a0 V2 30 sdram_a1 R8 31 sdram_a2 W3 32 sdram_a3 R5 35 sdram_a4 U10 36 sdram_a5 P4 37 sdram_a6 V1 38 sdram_a7 T9 39 sdram_a8 T8 40 sdram_a9 AA2 28 sdram_a10 T10 41 sdram_a11 U3 42 sdram_a12 U9 26 sdram_ba0 Y4 27 sdram_ba1 U1 22 sdram_cas_n R7 44 sdram_cke Y3 24 sdram_cs_n V4 23 sdram_ras_n U4 21 sdram_we_n AA6 46 sdram_clk_n AA7 45 sdram_clk_p Table 2 7 DDR SDRAM Pin Tabl...

Page 23: ...by the configuration controller to load the FPGA at power up Refer to Configuration Controller Device U3 on page 2 33 for related information A Nios II processor design in the FPGA can identify the 16 Mbyte flash memory in its address space and can program new data either new FPGA configuration data Nios II software or both into flash memory The Nios II development software includes subroutines fo...

Page 24: ...4 fe_a15 H15 3 fe_a16 H16 54 fe_a17 A17 19 fe_a18 B17 18 fe_a19 G15 11 fe_a20 F15 12 fe_a21 F16 15 fe_a22 G16 2 fe_a23 D8 35 fe_d0 C8 37 fe_d1 F10 39 fe_d2 G10 41 fe_d3 D9 44 fe_d4 C9 46 fe_d5 B8 48 fe_d6 A8 50 fe_d7 H17 32 flash_cs_n F17 34 flash_oe_n G17 13 flash_rw_n B18 16 flash_wp_n C17 53 flash_byte_n 1 D17 17 flash_ry_by_n Note to Table 2 8 1 BYTE_n on U5 is pulled low to keep the flash mem...

Page 25: ...e with the LAN91C111 Ethernet device Figure 2 4 Ethernet RJ 45 Connector Refer to Table 2 9 for connections between the FPGA and the MAC PHY device 1 The Ethernet MAC PHY device shares both address and data connections with the flash memory Table 2 9 Ethernet MAC PHY Pin Table FPGA Pin U4 Pin Pin Function Board Net Name 1 E26 41 Address Enable enet_aen J17 43 Synchronous Ready enet_srdy_n F18 40 V...

Page 26: ...a6 G14 84 Address Line fe_a7 F13 85 Address Line fe_a8 G13 86 Address Line fe_a9 C15 87 Address Line fe_a10 B15 88 Address Line fe_a11 B16 89 Address Line fe_a12 C16 90 Address Line fe_a13 D15 91 Address Line fe_a14 E15 92 Address Line fe_a15 D8 107 Data Line fe_d0 C8 106 Data Line fe_d1 F10 105 Data Line fe_d2 G10 104 Data Line fe_d3 D9 102 Data Line fe_d4 C9 101 Data Line fe_d5 B8 100 Data Line ...

Page 27: ...s are connected to the RXD and TXD signals and visually indicate when data is being transmitted or received Figure 6 and Table 2 10 show the pin connections between the serial connectors and the FPGA A9 70 Data Line fe_d13 C10 69 Data Line fe_d14 D10 68 Data Line fe_d15 B10 66 Data Line fe_d16 A10 65 Data Line fe_d17 E12 64 Data Line fe_d18 D12 63 Data Line fe_d19 J13 61 Data Line fe_d20 J14 60 Da...

Page 28: ...rototyping All 41 I O pins connect to user I O pins on the FPGA Each signal passes through analog switches to protect the FPGA from 5V logic levels These analog switches are permanently enabled The output logic level on the expansion prototype connector pins is 3 3V PROTO1 switches U19 U20 U21 U22 and U25 PROTO2 switches U27 U28 U29 U30 and U31 Table 2 10 Serial Connector Pin Table FPGA Pin J19 Pi...

Page 29: ...OTO1 connector or the CompactFlash connector 1 Do not connect cards to PROTO1 and CON3 at the same time Damage to one or both cards might result f See the Altera web site for a list of available expansion daughter cards that can be used with the Nios development board at www altera com devkits Table 2 11 Figure 2 6 and Figure 2 7 show connections from the PROTO1 expansion headers to the FPGA Unles...

Page 30: ... J11 proto1_io22 J25 32 J11 proto1_io23 J26 33 J11 proto1_io24 M21 35 J11 proto1_io25 T23 36 J11 proto1_io26 R17 37 J11 proto1_io27 K21 38 J11 proto1_cardsel_n P17 39 J11 proto1_io28 J12 Y22 3 J12 proto1_io40 T18 4 J12 proto1_io29 T17 5 J12 proto1_io30 U26 6 J12 proto1_io31 R19 7 J12 proto1_io32 T19 8 J12 proto1_io33 U20 9 J12 proto1_io34 U21 10 J12 proto1_io35 V26 11 J12 proto1_io36 V25 12 J12 pr...

Page 31: ...t Board Cyclone II Edition Board Components Figure 2 6 PROTO1 Expansion Prototype Connector J11 J12 J13 F21 11 J13 proto1_pllclk N26 13 J13 proto1_clkout Table 2 11 PROTO1 Pin Table Continued FPGA Pin PROTO1 Pin Connector Board Net Name Pin 1 J11 J12 J13 Pin 1 Pin 1 ...

Page 32: ...oto1_io21 29 proto1_io22 31 proto1_io24 33 proto1_io25 35 proto1_io27 37 proto1_io28 39 2 GND 4 proto1_io1 6 proto1_io3 8 proto1_io5 10 proto1_io7 12 proto1_io9 14 proto1_io11 16 proto1_io13 18 proto1_io15 20 NC 22 GND 24 GND 26 GND 28 proto1_io20 30 GND 32 proto1_io23 34 NC 36 proto1_io26 38 proto1_cardsel_n 40 GND J12 J11 1 Vunreg 1 NC 3 VCC3_3 5 VCC3_3 7 2 proto1_osc 9 3 proto1_pllclk 11 4 prot...

Page 33: ...J16 proto2_io2 AF23 6 J16 proto2_io3 AE23 7 J16 proto2_io4 AC22 8 J16 proto2_io5 AB21 9 J16 proto2_io6 AD23 10 J16 proto2_io7 AD22 11 J16 proto2_io8 AC21 12 J16 proto2_io9 AD21 13 J16 proto2_io10 AF22 14 J16 proto2_io11 AE22 15 J16 proto2_io12 V18 16 J16 proto2_io13 W19 17 J16 proto2_io14 U17 18 J16 proto2_io15 U18 21 J16 proto2_io16 AF21 23 J16 proto2_io17 AE21 25 J16 proto2_io18 AB20 27 J16 prot...

Page 34: ...o2_io29 AC18 5 J15 proto2_io30 AF19 6 J15 proto2_io31 AE19 7 J15 proto2_io32 AF18 8 J15 proto2_io33 AE18 9 J15 proto2_io34 AA16 10 J15 proto2_io35 Y16 11 J15 proto2_io36 AC17 12 J15 proto2_io37 AD17 13 J15 proto2_io38 AF17 14 J15 proto2_io39 J17 U2 pin 18 9 J17 proto2_osc F20 11 J17 proto2_pllclk AF14 13 J17 proto2_clkout Table 2 12 PROTO2 Pin Table Continued FPGA Pin PROTO2 Pin Connector Board Ne...

Page 35: ...11 proto2_io10 13 proto2_io12 15 proto2_io14 17 GND 19 proto2_io16 21 proto2_io17 23 proto2_io18 25 proto2_io19 27 proto2_io21 29 proto2_io22 31 proto2_io24 33 proto2_io25 35 proto2_io27 37 proto2_io28 39 2 GND 4 proto2_io1 6 proto2_io3 8 proto2_io5 10 proto2_io7 12 proto2_io9 14 proto2_io11 16 proto2_io13 18 proto_2io15 20 NC 22 GND 24 GND 26 GND 28 proto2_io20 30 GND 32 proto2_io23 34 NC 36 prot...

Page 36: ...not present the signal is pulled high through the pull up resistor Pin 41 of CON3 RESET is pulled up to 5V through a 10 Kohm resistor and is controlled by the EPM7256AE configuration controller The FPGA can cause the configuration controller to assert RESET but the FPGA does not drive this signal directly The CompactFlash connector shares several FPGA I O pins with expansion prototype connector PR...

Page 37: ...4 J23 31 D15 proto1_io15 H25 35 IOWR_n proto1_io17 H26 34 IORD_n proto1_io18 K18 42 IORDY_n proto1_io19 K24 37 INTRQ proto1_io22 J25 24 IOCS16_n proto1_io23 J26 19 A1 proto1_io24 M21 20 A0 proto1_io25 T23 18 A2 proto1_io26 R17 7 CS0_n proto1_io27 P17 45 DASP proto1_io28 T18 8 A10 proto1_io29 T17 46 PDIAG proto1_io30 U26 10 A9 proto1_io31 R19 11 A8 proto1_io32 T19 12 A7 proto1_io33 U20 14 A6 proto1...

Page 38: ...t first be configured with a design that includes a PMC interface Damage to either the FPGA or daughter card can result if the FPGA is not configured correctly The factory programmed Nios II reference design does not include a PMC interface V23 43 INPACK_n proto1_io39 Y22 44 REG_n proto1_io40 W16 32 CS1_n cf_cs_n AE16 9 ATA_SEL_n cf_atasel_n AD16 5 Power supply enable cf_power 2 W15 26 CD1_n cf_pr...

Page 39: ...nts exceed the specifications shown in Table 2 14 you must connect an external power source w When connecting an external power supply the fuse for the corresponding voltage should be removed to prevent the two power supplies from interfering with each other Refer to Power Supply Circuitry on page 2 44 for more information Table 2 15 lists the connections between the PMC connector and the FPGA Tab...

Page 40: ...1 45 JH2 pmc_ad14 Y23 46 JH1 pmc_ad15 Y24 31 JH2 pmc_ad16 Y25 32 JH1 pmc_ad17 Y26 29 JH2 pmc_ad18 AA23 29 JH1 pmc_ad19 AA24 28 JH2 pmc_ad20 AA25 28 JH1 pmc_ad21 AA26 27 JH1 pmc_ad22 AB23 26 JH2 pmc_ad23 AB24 23 JH2 pmc_ad24 AB25 23 JH1 pmc_ad25 AB26 22 JH2 pmc_ad26 AC23 22 JH1 pmc_ad27 AC25 21 JH1 pmc_ad28 AC26 20 JH2 pmc_ad29 AD24 19 JH2 pmc_ad30 AD25 20 JH1 pmc_ad31 R20 52 JH1 pmc_be_n0 T22 43 J...

Page 41: ...Nios II processor any on chip signals can be routed to I O pins and probed at J25 External scopes and logic analyzers can connect to J25 and analyze a large number of signals simultaneously f For details on Nios II debugging products that use the Mictor connector see www altera com T20 43 JH1 pmc _par W26 13 JH1 pmc_clk U24 39 JH2 pmc_perr_n U23 42 JH2 pmc_serr_n R25 37 JH1 pmc_devsel_n P24 38 JH2...

Page 42: ...r details see www fs2 com Figure 2 12 An ISA Nios T Connecting to the Mictor Connector J25 Five of the signals connect to both the JTAG pins on the FPGA U62 and the FPGA s JTAG connector J24 The JTAG signals have special usage requirements J25 and J24 cannot be used at the same time Figure 2 13 below shows connections from the Mictor connector to the FPGA Figure 2 13 Mictor Connector Signaling J25...

Page 43: ...bed TP1 TP8 also connect to the configuration controller U3 Table 2 16 Mictor Connector Pin Table FPGA Pin J25 Pin Board Net Name V21 5 mictor_clk AC8 38 mictor0 AD8 36 mictor1 W10 34 mictor2 Y10 32 mictor3 V10 30 mictor4 V9 28 mictor5 AD6 26 mictor6 AD7 24 mictor7 AE5 22 mictor8 AF5 20 mictor9 AD4 18 mictor10 AD5 16 mictor11 AC5 10 mictor12 AC6 8 mictor13 AF4 37 mictor14 AE4 35 mictor15 B21 33 mi...

Page 44: ... Flash Controller component enables Nios II processor systems to access the EPCS device Nios II processor systems can read program code or data from the device and can write new data into the EPCS device U69 is blank by default The Quartus II software can program FPGA configuration data a pof file into U69 through an Altera download cable connected to J27 Alternately software running on a Nios II ...

Page 45: ...nfiguration device U69 FPGA configuration data files are generated by the Quartus II software The Nios II integrated development environment IDE can write new configuration data to the board s flash memory f For complete details on the configuration controller connections see the board schematic For detailed information about the Altera EPM7256AE device see the MAX 7000 family literature at www al...

Page 46: ... the FPGA LED4 Error Red If this LED is on then configuration was not transferred from flash memory into the FPGA This can happen if for example the flash memory contains either a valid user or factory configuration LED1 User Green This LED turns on when the user configuration is being transferred from flash memory and stays illuminated when the user configuration data is successfully loaded into ...

Page 47: ...the FPGA with the factory configuration Refer to Figure 2 16 Figure 2 16 Factory Config Button SW10 Reset Config Reset Config SW10 is the power on reset button Refer to Figure 2 17 When SW10 is pressed a logic 0 is driven to the power on reset controller U18 Refer to Power Supply Circuitry on page 2 44 for more details Whenever SW10 is pressed the configuration controller attempts to reconfigure t...

Page 48: ...mpactFlash reset Reset signals delivered to the expansion prototype connectors PROTO1 PROTO2 Starting Configuration The following four methods start a configuration sequence 1 Board power on 2 Pressing the Reset Config button SW10 3 Asserting driving 0 volts on the pld_reconfigreq_n input pin of the EPM7256AE device U3 pin 94 from the FPGA U62 pin AA14 4 Pressing the Factory Config button SW9 Fact...

Page 49: ...GA in active serial AS configuration mode The FPGA then attempt to read configuration data from the EPCS64 If the FPGA finishes configuration successfully the configuration controller stops If configuration from the EPCS64 does not succeed the configuration controller puts the FPGA into passive serial PS mode and attempts to load the user configuration from flash memory If this also fails because ...

Page 50: ...ration the configuration controller may not be able to successfully configure the FPGA If you alter the factory configuration you can restore the board to its factory programmed state Refer to Appendix B Restoring the Factory Configuration User Application Space The lower 11 MB of flash memory is the user application space This is free space for user designs to store code and data for Nios II prog...

Page 51: ...4 KB starting at offset 0x00FF0000 This partition is for maintaining nonvolatile settings and data such as the MAC address and IP address for the factory programmed web server reference design Persistent data is technically no different than other application data but it is often convenient to think of certain data as independent from the user hardware or software JTAGConnectors J24 J5 The Nios de...

Page 52: ...gure 2 19 USB Blaster Connected to J24 JTAG Connector The FPGA s JTAG pins can also be accessed via the Mictor connector J25 The pins of J24 are connected directly to pins on J25 and care must be taken so that signal contention does not occur between the two connectors TMS TDI TCK TDO TRST To Mictor Connector J25 JTAG Signals JTAG Connector J24 FPGA U62 Pin 1 J24 ...

Page 53: ...rogram the configuration controller design in the EMP7256AE device Reprogramming the configuration controller can result in an inoperable development board f To restore the board to its factory programmed condition see Appendix B Restoring the Factory Configuration Figure 2 20 JTAG Connector J5 to MAX Device Clock Circuitry The Nios development board includes a 50 MHz free running oscillator Y2 an...

Page 54: ...tor from its socket Make sure to note the correct orientation of the oscillator before removing it osc_CLK0 osc_CLK1 sram_CLKIN sdram_CLKIN MAX U3 cpld_CLKOSC sdram_CLK_p sdram_CLK_n DDRSDRAM U63 SSRAM U74 sram_CLK PMC_CLK PMC JH1 JH2 FPGA U62 PLLs PROTO1 proto1_PLLCLK proto1_CLKOUT proto1_OSCCLK Mictor J25 mictor_CLK PROTO2 proto2_PLLCLK proto2_CLKOUT proto2_OSCCLK SMAExternal Input J4 Oscillator...

Page 55: ...PGA Pin Name PLL Signal Source Board Net Name B25 IO N A J25 pin 6 mictor_TRCLK N26 CLK5 PLL2 J13 pin 13 proto1_CLKOUT AF4 CLK13 PLL4 J17 pin 13 proto2_CLKOUT P25 CLK6 PLL2 U2 pin 2 osc_CLK0 AC13 CLK15 PLL4 U2 pin 3 osc_CLK1 N2 CLK0 PLL1 U2 pin 4 sram_CLKIN B13 CLK8 PLL3 U2 pin 6 sdram_CLKIN Table 2 22 FPGA Clock Output Pin Table FPGA Pin FPGA Pin Name PLL 1 Signal Destination Board Net Name AA7 P...

Page 56: ...ip and is not available on any connector or header The 1 2V supply is used only as the power supply for the Cyclone II device core VCCINT and it is not available on any connector or header The 12V supply is provided for the PMC connectors JH1 and JH2 Refer to PMC Connector JH1 JH2 on page 2 26 for more details When workbench power supplies are connected to the board a corresponding fuse must be re...

Page 57: ...s Start point to Programs Altera Nios II EDS installed version and then click Nios II Command Shell 2 From the examples directory change to the factory_recovery directory for your development kit cd factory_recovery niosII_cycloneII_2c35 3 Run the flash restoration script restore_my_flash 4 Follow the script s instructions Reprogramming the EPM7256AE Configuration Controller Device If the configur...

Page 58: ...install path examples factory_recovery niosII_cycloneII_2c35 config_controller pof 4 In the Programmer turn on the Program Configure checkbox and click Start to reprogram the EPM7256AE device 5 Press the Factory Config button to perform a power on reset and reconfigure the FPGA from flash memory You should see the Factory LED turned on and activity on LEDs D0 through D7 Your board is now reconfigu...

Page 59: ...e web server from the host computer Figure B 1 Web Server Reference Design Connecting the Ethernet Cable The Nios II development kit includes an Ethernet RJ45 cable and a male female RJ45 crossover adapter Before you connect these components you must decide how you want to use the network features of your board Select one of the two following connection methods 1 LAN Connection To use your Nios de...

Page 60: ... 2 Point to Point Connection b Connect the other end of the RJ45 connector directly to the network Ethernet port on your host computer Connecting the LCD Screen The Nios II development kit includes a two line x 16 character LCD text screen The web server software displays useful status and progress messages on this display If you wish to use the network features of the board connect the LCD screen...

Page 61: ... IP Address If the DHCP process fails the board uses a static IP address stored in flash memory You need to obtain a safe IP address in your LAN s subnet from your system administrator Once you know a safe IP address you can assign it to your board using the steps below These steps send IP configuration data to the board via an Altera JTAG download cable such as the USB Blaster cable 1 Install the...

Page 62: ... program then close the Nios II command shell 9 Press the SW8 button labeled CPU Reset to reboot the Nios II processor and start the web server using the new IP address The LCD screen displays the static IP address assigned to the board along with other status messages The web server is now ready to display pages using the IP address you assigned See Browsing to Your Board on page B 5 to continue ...

Page 63: ...e steps in Static IP Address on page B 3 Every time you reset the board the web server will attempt to obtain an IP address via DHCP which takes two minutes to time out You can abort the DHCP process or disable DHCP entirely by using the steps in Static IP Address on page B 3 Browsing to Your Board Once your board has a valid IP address obtained from either DHCP self configuration or from flash me...

Page 64: ...B 6 Reference Manual Altera Corporation Nios Development Board Cyclone II Edition May 2007 ...

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