Altera MAX 10 series User Manual Download

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MAX 10 Power Management User Guide

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UG-M10PWR

2015.11.02

101 Innovation Drive

San Jose, CA 95134

www.altera.com

Summary of Contents for MAX 10 series

Page 1: ...MAX 10 Power Management User Guide Subscribe Send Feedback UG M10PWR 2015 11 02 101 Innovation Drive San Jose CA 95134 www altera com...

Page 2: ...ller Architecture 2 7 Hot Socketing 2 9 Hot Socketing Specifications 2 9 Hot Socketing Feature Implementation 2 10 Power Management Controller Reference Design 3 1 Clock Control Block 3 2 I O Buffer 3...

Page 3: ...logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the prop...

Page 4: ...eriphery operations 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered...

Page 5: ...using high efficiency switching power supplies on the board The power savings will be equal to the increased efficiency of the regulators used compared to the internal linear regulators of the MAX 10...

Page 6: ...r consumption of VCC_ONE as listed in the following table Running a design that goes beyond the maximum power consumption of VCC_ONE of the MAX 10 single supply device may cause functional issue on th...

Page 7: ...10 device in the reset state until the POR monitored power supply outputs are within the recommended operating range of the maximum power supply ramp time tRAMP If the ramp time tRAMP is not met the...

Page 8: ...uitry The main POR circuitry waits for all individual POR circuitries to release the POR signal before allowing the control block to start programming the device The main POR is released after the las...

Page 9: ...is to detect a brown out condition during user mode If either the VCCA or VCC voltages go below the POR trip point during user mode the main POR signal is asserted When the main POR signal is asserte...

Page 10: ...t ramping Dual supply device All power supplies must ramp up to full rail before VCC starts ramping Related Information MAX 10 FPGA Device Datasheet Provides details about the MAX 10 ramp time require...

Page 11: ...o set oscena to 1 For the clock frequency of the internal oscillator refer to the MAX 10 FPGA Device Datasheet Related Information MAX 10 FPGA Device Datasheet Provides details about the MAX 10 ramp t...

Page 12: ...cing support without the use of any external devices You can insert or remove the MAX 10 device on a board in a system during system operation This does not affect the running system bus or the board...

Page 13: ...of the device and ground planes This condition can lead to latch up and cause a low impedance path from VCC to ground in the device As a result the device extends a large amount of current possibly ca...

Page 14: ...iven before VCCIO and VCC supplies are powered up This prevents the I O pins from driving out when the device is not in user mode Altera uses GND as reference for hot socketing operation and I O buffe...

Page 15: ...ose I O GPIO output ports cnt_value 7 0 Output Free running counter value in user logic cnt_enter_sleep 7 0 Output Counter value when the system is entering sleep mode condition 2015 Altera Corporatio...

Page 16: ...altclkctrl is an IP provided in the Quartus Prime software This IP is used to control the clock system in the device The GCLKs that drive through the device can be dynamically powered down by controll...

Page 17: ...rforms power up operation on I O buffers and GCLK networks A wake up event is detected when the sleep signal is de asserted A wake up event could be triggered by an internal or external request such a...

Page 18: ...ff all GCLK networks by disabling clk_ena 15 0 signal from LSB to MSB After three clock cycles the clk_ena 15 0 signal is fully disabled and transits into the sleep state 4 The power management contro...

Page 19: ...diagram and exiting sleep mode timing diagram respectively Table 3 2 T1 T2 T3 and T4 Parameters Minimum Value and Definition Parameter Width bits Minimum Value Decimal Description T1 6 1 ioe disable t...

Page 20: ...sign to user mode release the push button USER_PB0 LED0 indicates the sleep status of the device LED0 is turned on when the device enters sleep mode and is turned off when the device is in user mode D...

Page 21: ...show an approximate 93 reduction in the core current 1 2V_ICC consumption and an approximate 56 reduction in I O current 2 5V_ICCIO consumption in sleep mode relative to user mode The total power cons...

Page 22: ...rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in ot...