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Altera HSMC, Reference Manual

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2–14

Chapter 2: Board Components and Interfaces

Component Interfaces

Data Conversion HSMC Reference Manual

© November 2008

Altera Corporation

Table 2–15

 provides the differential to LVDS clock multiplexer pin-out details.

D/A Converter Output SMA Connector (J12, J14)

J12 (channel A) and J14 (channel B) are standard through-hole SMA connectors used 
to interface the DAC5672 D/A converter output with SMA cables.

Audio CODEC Converter (U5)

The Data Conversion HSMC contains three stereo jack and one mic jack connectors 
which provide one stereo output, one stereo input, one amplified stereo headphone 
output, and one microphone input. The stereo jacks are driven by a stereo audio 
CODEC running at 8 to 96 kHz. 

Table 2–16

 lists the audio CODEC board reference 

and manufacturing information.

Table 2–17

 provides the TI TLV320AIC23 audio CODEC pin-out details. 

Table 2–15.

Differential to LVDS Clock Multiplexer (U11, U12) Pin-Out Information

Schematic Signal

HSMC 

Connector 

Pin Number

Device Signal

Device

Pin Number

Description

FPGA_CLK_A_P

95

PCLK0P

1

Non-inverting Differential clock input

FPGA_CLK_A_N

97

PCLK0N

2

Inverting Differential clock input

FPGA_CLK_B_P

155

PCLK1P

3

Non-inverting Differential clock input

FPGA_CLK_B_N

157

PCLK1N

4

Inverting Differential clock input

XT_IN_P

96

PCLK2P

9

Non-inverting Differential clock input

XT_IN_N

98

PCLK2N

10

Inverting Differential clock input

DA(A,B)_CLK_SEL_P

—

QP

15

Non-inverting Differential Clock Output

DA(A,B)_CLK_SEL_N

—

QN

14

Inverting Differential Clock Output

Table 2–16.

 Audio CODEC Converter Component Reference

Board Reference

Description

Manufacturer

Manufacturing

Part Number

Manufacturer 

Website

U5

Stereo Audio CODEC, 8–96 KHz, with 
Integrated Headphone Amplifier

Texas Instruments

TLV320AIC23

www.ti.com

Table 2–17.

Audio CODEC Converter (U5) Pin-Out Information (Part 1 of 2)

HSMC Signal

HSMC Pin

Device Signal

Device

Pin Number

Description

AIC_XCLK

150

XTI/MCLK

25

Crystal or external-clock input. Used for derivation of all 
internal clocks on the AIC23B.

AIC_LRCOUT

146

LRCOUT

7

I2S A/D converter-word clock signal. In audio master 
mode, the AIC23B generates this framing signal and sends 
it to the DSP. In audio slave mode, the signal is generated 
by the DSP.

AIC_LRCIN

145

LRCIN

5

I2S D/A converter-word clock signal. In audio master 
mode, the AIC23B generates this framing signal and sends 
it to the DSP. In audio slave mode, the signal is generated 
by the DSP.

Summary of Contents for HSMC

Page 1: ...101 Innovation Drive San Jose CA 95134 www altera com Data Conversion HSMC Reference Manual Document Version 1 1 Document Date November 2008...

Page 2: ...gn patents and pending ap plications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty bu...

Page 3: ...put SMA Connectors J26 J30 2 6 External Clock Output SMA Connectors J25 J28 2 7 Component Interfaces 2 7 A D Converter U1 U2 2 7 A D Converter Clocks 2 9 A D Converter Input SMA Connector J4 J8 2 11 D...

Page 4: ...iv Contents Data Conversion HSMC Reference Manual November 2008 Altera Corporation Preliminary...

Page 5: ...ital A D and digital to analog D A interfaces including an audio coder decoder CODEC interface This manual describes each of the hardware interfaces on the Data Conversion HSMC f For the latest inform...

Page 6: ...Figure 1 2 Data Conversion HSMC Block Diagram A D Channel A External Clock Input 14 Bit 150 MS s A D Converter SMA SI CKT XT_CLK XT_CLK SI CKT A D Channel B SI CKT CLK SEL 14 Bit 150 MS s A D Converte...

Page 7: ...installing the demo software and examples refer to the user guide provided with your kit Figure 2 1 shows the layout and components of the Data Conversion HSMC Figure 2 1 Data Conversion HSMC Layout...

Page 8: ...ols whether the A D converter operates in power down or power up state 2 4 J15 Channel A J17 Channel B D A converter clock select jumper Controls which of the three input clock signals FPGA clock A B...

Page 9: ...l B D A converter output SMAs SMA outputs for the D A converters 2 14 U5 Audio CODEC Texas Instruments TLV320AK23 Stereo Audio CODEC 96 KHz with integrated headphone amplifier 2 14 J19 Line in audio j...

Page 10: ...atic Signal Name 1 2 3 A D Converter Clock Select J3 or J7 Jumper Setting Table 2 3 Power Down Select Jumper Settings for AD9254 A D Converter U1 U2 A D Converter Jumper Settings 1 Description U1 Chan...

Page 11: ...the D A converter in power down mode It is selectable through J13 channel A and channel B Table 2 7 lists the jumper settings for sleep select options The D A converter when not in use should be put i...

Page 12: ...ock R112 must be removed and R111 be installed Table 2 8 External Clock Output Select Jumper J23 Settings Clock Source Board Reference Schematic Signal Name 1 External Clock Output Select Jumper J23 S...

Page 13: ...14 bit 150 MS s A D converters This device is designed for high speed and high performance applications The inputs to these A D converters are transformer coupled in order to create a balanced input...

Page 14: ...ADA_D11 47 D11 12 Data Output Bit 11 ADA_D12 43 D12 13 Data Output Bit 12 ADA_D13 41 D13 14 Data Output Bit 13 ADA_OR 83 OR 15 Out of Range Indicator AD_SDIO 91 SDIO DCS 18 Serial Port Interface SPI...

Page 15: ...D8 9 Data Output Bit 8 ADB_D9 54 D9 10 Data Output Bit 9 ADB_D10 50 D10 11 Data Output Bit 10 ADB_D11 48 D11 12 Data Output Bit 11 ADB_D12 44 D12 13 Data Output Bit 12 ADB_D13 42 D13 14 Data Output Bi...

Page 16: ...1 F 1 0nF ICS854054 U9 ADB_OE ADB_CLK_P ADB_CLK_N ADB_OE ADB_CLK_N ADB_CLK_P ADB_SPI_CS AD_SDIO AD_SCLK FPGA_CLK_A_P NO_CLK_P NO_CLK_N ADB_CLK_S1 ADB_CLK_S0 PCLK0P PCLK0N PCLK1P PCLK1N PCLK2P PCLK2N P...

Page 17: ...nce and manufacturing information Table 2 14 provides the pin out details of the D A converter channel A and channel B XT_IN_P 96 PCLK2P 9 Non inverting Differential clock input XT_IN_N 98 PCLK2N 10 I...

Page 18: ...ta port B12 DB13 102 DB13 23 Data port B13 CLKA 18 1 Clock input for DACA CLKIQ in interleaved mode CLKB 19 2 Clock input for DACB RESETIQ in interleaved mode GSET 42 3 Gain setting mode H 1 resistor...

Page 19: ...rter Clock Select Jumper J15 J17 on page 2 4 Figure 2 6 D A Converter Clocking Options FPGA_CLK_A_P NO_CLK_P NO_CLK_N DAA_CLK_S1 DAA_CLK_S0 PCLK0P PCLK0N PCLK1P PCLK1N PCLK2P PCLK2N PCLK3P PCLK3N SEL0...

Page 20: ...nverting Differential clock input FPGA_CLK_B_P 155 PCLK1P 3 Non inverting Differential clock input FPGA_CLK_B_N 157 PCLK1N 4 Inverting Differential clock input XT_IN_P 96 PCLK2P 9 Non inverting Differ...

Page 21: ...ng other differential signaling are provided with the board The eight clock data recovery high speed transceiver channels are not connected on this HSMC AIC_DIN 143 DIN 4 I2S format serial data input...

Page 22: ...details of the I2C Serial EEPROM with HSMC connector Figure 2 7 Samtec Header Connector 2 413 90 POS 30 x 7875 050 78 REF 626 REF 036 REF 006 REF 245 REF 150 REF 01 02 285 REF DP Bank 571 29 EQ Spaces...

Page 23: ...ovide various voltage options the board uses several Linear Technologies regulators Table 2 21 lists the Power Supplies board reference and manufacturing information Figure 2 8 I2C Serial EEPROM Schem...

Page 24: ...2 18 Chapter 2 Board Components and Interfaces Power Supply Data Conversion HSMC Reference Manual November 2008 Altera Corporation...

Page 25: ...MA_D3 2 5 V AC5 47 LVDS TX or CMOS I O bit 0 ADA_D11 HSMA_TX_D_P0 LVDS or 2 5 V R7 48 LVDS RX or CMOS I O bit 0 ADB_D11 HSMA_RX_D_P0 LVDS or 2 5 V AB2 49 LVDS TX or CMOS I O bit 0 ADA_D10 HSMA_TX_D_N0...

Page 26: ...5n or CMOS I O data bit 26 ADA_D0 HSMA_TX_D_N5 LVDS or 2 5 V P1 80 LVDS RX 5n or CMOS I O data bit 27 ADB_D0 HSMA_RX_D_N5 LVDS or 2 5 V U1 83 LVDS TX 6p or CMOS I O data bit 28 ADA_OR HSMA_TX_D_P6 LV...

Page 27: ...a bit 46 DA10 HSMA_TX_D_N9 LVDS or 2 5 V L8 110 LVDS RX 9n or CMOS I O data bit 47 DB10 HSMA_RX_D_N9 LVDS or 2 5 V L3 113 LVDS TX 10p or CMOS I O data bit 48 DA9 HSMA_TX_D_P10 LVDS or 2 5 V K4 114 LVD...

Page 28: ...RX 14n or CMOS I O data bit 67 DB0 HSMA_RX_D_N14 LVDS or 2 5 V G3 143 LVDS RX 15p or CMOS I O data bit 68 AIC_DIN HSMA_TX_D_P15 LVDS or 2 5 V E2 144 LVDS TX 15p or CMOS I O data bit 69 AIC_DOUT HSMA_...

Page 29: ...O data bit 5 ADB_D11 HSMB_RX_D_P0 LVDS or 2 5 V F27 49 LVDS TX 0n or CMOS I O data bit 6 ADA_D10 HSMB_TX_D_N0 LVDS or 2 5 V J26 50 LVDS RX 0n or CMOS I O data bit 7 ADB_D10 HSMB_RX_D_N0 LVDS or 2 5 V...

Page 30: ...6p or CMOS I O data bit 29 ADB_OR HSMB_RX_D_P6 LVDS or 2 5 V P25 85 LVDS TX 6n or CMOS I O data bit 30 ADA_OE HSMB_TX_D_N6 LVDS or 2 5 V U26 86 LVDS RX 6n or CMOS I O data bit 31 ADB_OE HSMB_RX_D_N6 L...

Page 31: ...I O data bit 49 DB9 HSMB_RX_D_P10 LVDS or 2 5 V T25 115 LVDS TX 10n or CMOS I O data bit 50 DA8 HSMB_TX_D_N10 LVDS or 2 5 V Y26 116 LVDS RX 10n or CMOS I O data bit 51 DB8 HSMB_RX_D_N10 LVDS or 2 5 V...

Page 32: ...SMB_TX_D_P15 LVDS or 2 5 V W22 144 LVDS TX 15p or CMOS I O data bit 69 AIC_DOUT HSMB_RX_D_P15 LVDS or 2 5 V AB27 145 LVDS RX 15n or CMOS I O data bit 70 AIC_LRCIN HSMB_TX_D_N15 LVDS or 2 5 V Y22 146 L...

Page 33: ...I O bit 1 ADA_D9 HSMA_TX_P1 LVDS or 2 5 V AC9 54 LVDS RX or CMOS I O bit 1 ADB_D9 HSMA_RX_P1 LVDS or 2 5 V AG4 55 LVDS TX or CMOS I O bit 1 ADA_D8 HSMA_TX_N1 LVDS or 2 5 V AC8 56 LVDS RX or CMOS I O...

Page 34: ...it 9 DB11 HSMA_RX_P9 LVDS or 2 5 V AE2 109 LVDS TX or CMOS I O bit 9 DA10 HSMA_TX_N9 LVDS or 2 5 V AB5 110 LVDS RX or CMOS I O bit 9 DB10 HSMA_RX_N9 LVDS or 2 5 V AE1 113 LVDS TX or CMOS I O bit 10 DA...

Page 35: ...HSMA_CLK_IN_N2 2 5 V T1 Table B 1 HSMC Port A Interface Pin Out Information Part 3 of 3 Data Conversion HSMC Schematic Development Board Schematic Board Reference J1 Description Schematic Signal Name...

Page 36: ...LVDS or 2 5 V N8 86 LVDS RX or CMOS I O bit 6 ADB_OE HSMB_RX_N6 LVDS or 2 5 V K3 89 LVDS TX or CMOS I O bit 7 ADA_SPI_CS HSMB_TX_P7 LVDS or 2 5 V M7 90 LVDS RX or CMOS I O bit 7 ADB_SPI_CS HSMB_RX_P7...

Page 37: ...r 2 5 V D1 137 LVDS TX or CMOS I O bit 14 DA1 HSMB_TX_P14 LVDS or 2 5 V L9 138 LVDS RX or CMOS I O bit 14 DB1 HSMB_RX_P14 LVDS or 2 5 V D3 139 LVDS TX or CMOS I O bit 14 DA0 HSMB_TX_N14 LVDS or 2 5 V...

Page 38: ...B 6 Appendix B Pin Out Information for the Stratix III 3SL150 Development Board Data Conversion HSMC Reference Manual November 2008 Altera Corporation...

Page 39: ...to Host ADA_D10 HSMC_D6 2 5 V N7 50 A D A bit 10 to Host ADB_D10 HSMC_D7 2 5 V T2 53 A D A bit 9 to Host ADA_D9 HSMC_D8 2 5 V N8 54 A D B bit 9 to Host ADB_D9 HSMC_D9 2 5 V H15 55 A D A bit 8 to Host...

Page 40: ...DB13 HSMC_RX_p8 2 5 V P2 103 D A A bit 12 from Host DA12 HSMC_TX_n8 2 5 V M1 104 D A B bit 12 from Host DB12 HSMC_RX_n8 2 5 V P1 107 D A A bit 11 from Host DA11 HSMC_TX_p9 2 5 V R2 108 D A B bit 11 f...

Page 41: ...MC_RX_p15 2 5 V M6 145 Audio Codec L R In from Host AIC_LRCIN HSMC_TX_n15 2 5 V R4 146 Audio Codec L R Out to Host AIC_LRCOUT HSMC_RX_n15 2 5 V N6 149 Audio Codec Bclk from Host AIC_BCLK HSMC_TX_p16 2...

Page 42: ...C 4 Appendix C Pin Out Information for the Cyclone III 3C25 Starter Board Data Conversion HSMC Reference Manual November 2008 Altera Corporation...

Page 43: ...Changes Made November 2008 1 1 Updated pin out information in the appendices March 2008 1 0 First publication Contact Note 1 Contact Method Address Technical support Website www altera com support Tec...

Page 44: ...ferences to sections within a document and titles of Quartus II Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example da...

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