Enpirion
®
Power Evaluation Board User Guide
EN5367QI PowerSoC
Figure 5: EN5367QI Evaluation Board Schematic
Use combination
1206/0805 footprint C6-7
0805
0805
0805
0805
1206
1206
1206
1206
0805
0402
0402
08
0
5
0
80
5
0
80
5
0
80
5
0
80
5
0
80
5
PVIN
PVIN
S_IN
C16
04
0
2
J1
1
2
3
5
6
7
9
1
0
1
1
1
3
1
4
1
5
1
7
1
8
1
9
R2
C1
C2
R5
R3
R4
TP23
TP24
U1
EN5367QI
NC1
1
NC2
2
NC3
3
NC4
4
NC5
5
NC6
6
NC7
7
NC8
8
NC9
9
VOU
T
1
0
VOU
T
1
1
VOU
T
1
2
VOU
T
1
3
VOU
T
1
4
VOU
T
1
5
VOU
T
1
6
VOU
T
1
7
NC1
8
1
8
N
C
(SW
)1
9
1
9
N
C
(SW
)2
0
2
0
PGN
D
2
1
PGN
D
2
2
PGN
D
2
3
PGN
D
2
4
PGN
D
2
5
PGN
D
2
6
PGN
D
2
7
SY NC/LLM
36
BGND
35
VDDB
34
BTMP
33
PG
32
PVIN
31
PVIN
30
PVIN
29
PVIN
28
NC5
4
5
4
NC5
3
5
3
N
C
(SW
)5
2
5
2
N
C
(SW
)5
1
5
1
N
C
(SW
)5
0
5
0
N
C
(SW
)4
9
4
9
NC4
8
4
8
AVI
N
4
7
AGN
D
4
6
NC4
5
4
5
VF
B
4
4
SS
4
3
R
L
LM
4
2
EAOU
T
4
1
NC4
0
4
0
POK
3
9
EN
ABL
E
3
8
VD
R
OOP
3
7
ENA
VDROOP
SYNC/LLM
08
0
5
POK
R8
J7
C
1
0
TP26
TP27
C17
R10
R11
R12
R13
TP3
TP4
TP5
TP6
TP7
TP8
TP9
Provision for
dynamic voltage
adjustment
R9
C11
EAOUT
VFB
VFB
EAOUT
VFB
TP29
C3
TP30
FB1
C4
C5
C6
C7
TP10
TP11
TP12
R14
C8
TP13
TP14
TP15
C9
R1
TP16
AVIN
J2
1
3
5
2
4
6
8
7
ENA
VDROOP
SYNC/LLM
POK
AGND
N/U
08
0
5
08
0
5
08
0
5
0805
TP17
J3
J4
J5
J6
+
C13
D1
U2
R15
C14
TP1
1
2
TP2
1
2
R6
C15
VOUT
VOUT
PVIN
SMA
2
TP22
1
2
SCH 05820
PCB 05707
05837 Caps on back
05839 Caps on top and back
SMA
2
TP25
1
2
R7
VIN
GND
VOUT
GND
TP18
TP19
TP20
TP21
VIN
GND
VOUT
04
0
2
GND
C18
C12
Use combination
1206/0805 footprint C4-5
Page 6 of 8
