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Altera DE5-NET, User Manual

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Altera DE5-NET User Manual Download Page 4

 

 

 

 

DE5-Net User Manual 

 

 

www.terasic.com 

June 20, 2018 

 

3 

5.3

 

S

I

570

 AND 

CDCM

 

P

ROGRAMMING BY 

N

IOS 

II ........................................................................................................ 73

 

CHAPTER 6

 

MEMORY REFERENCE DESIGN

 .................................................................................................. 78

 

6.1

 

QDRII+

 

SRAM

 

T

EST

 ............................................................................................................................................. 78

 

6.2

 

DDR3

 

SDRAM

 

T

EST

 ............................................................................................................................................. 81

 

6.3

 

DDR3

 

SDRAM

 

T

EST BY 

N

IOS 

II ............................................................................................................................ 83

 

CHAPTER 7

 

  PCI EXPRESS REFERENCE DESIGN

 ....................................................................................... 87

 

7.1

 

PCI

 

E

XPRESS 

S

YSTEM 

I

NFRASTRUCTURE

 ................................................................................................................ 87

 

7.2

 

PC

 

PCI

 

E

XPRESS 

S

OFTWARE 

SDK .......................................................................................................................... 88

 

7.3

 

R

EFERENCE 

D

ESIGN 

-

 

F

UNDAMENTAL

 ..................................................................................................................... 98

 

7.4

 

PCI

E 

R

EFERENCE 

D

ESIGN 

–

 

DDR3 ....................................................................................................................... 105

 

CHAPTER 8

 

TRANSCEIVER VERIFICATION

 .................................................................................................. 112

 

8.1

 

T

EST 

C

ODE

 ............................................................................................................................................................ 112

 

8.2

 

L

OOPBACK 

F

IXTURE

 ............................................................................................................................................. 112

 

8.3

 

T

ESTING

 ................................................................................................................................................................ 114

 

ADDITIONAL INFORMATION

 ................................................................................................................................... 116

 

 

Summary of Contents for DE5-NET

Page 1: ...ss mainly focus on the distribution of electronic components Line cards we deal with include Microchip ALPS ROHM Xilinx Pulse ON Everlight and Freescale Main products comprise IC Modules Potentiometer...

Page 2: ...DE5 Net User Manual www terasic com June 20 2018 1...

Page 3: ...18 2 5 CLOCK CIRCUIT 19 2 6 RS 422 SERIAL PORT 21 2 7 FLASH MEMORY 22 2 8 DDR3 SO DIMM 25 2 9 QDRII SRAM 32 2 10 SPF PORTS 40 2 11 PCI EXPRESS 42 2 12 SATA 44 CHAPTER 3 SYSTEM BUILDER 48 3 1 INTRODUCT...

Page 4: ...3 SDRAM TEST 81 6 3 DDR3 SDRAM TEST BY NIOS II 83 CHAPTER 7 PCI EXPRESS REFERENCE DESIGN 87 7 1 PCI EXPRESS SYSTEM INFRASTRUCTURE 87 7 2 PC PCI EXPRESS SOFTWARE SDK 88 7 3 REFERENCE DESIGN FUNDAMENTAL...

Page 5: ...ix V GX FPGA features integrated transceivers that transfer at a maximum of 12 5 Gbps allowing the DE5 Net to be fully compliant with version 3 0 of the PCI Express standard as well as allowing an ult...

Page 6: ...iguration via MAX II CPLD and flash memory General user input output 10 LEDs 4 push buttons 4 slide switches 2 seven segment displays Clock System 50MHz Oscillator Programmable oscillators Si570 CDCM6...

Page 7: ...s edge connector power Mechanical Specification PCI Express full height and 3 4 length 1 1 3 3 B Bl lo oc ck k D Di ia ag gr ra am m 94H94HFigure 1 1 shows the block diagram of the DE5 Net board To pr...

Page 8: ...agram of the DE5 Net board Below is more detailed information regarding the blocks in Figure 1 1 Stratix V GX FPGA 5SGXEA7N2F45C2 622 000 logic elements LEs 50 Mbits embedded memory 48 transceivers 12...

Page 9: ...CPLD EPM2210 System Controller and Fast Passive Parallel FPP configuration Memory devices 32MB QDRII SRAM Up to 8GB DDR3 SO DIMM SDRAM 256MB FLASH General user I O 10 user controllable LEDs 4 user pu...

Page 10: ...18 9 Four SFP ports Four SFP connector 10 Gbps PCI Express x8 edge connector Support for PCIe Gen1 2 3 Edge connector for PC motherboard with x8 or x16 PCI Express slot Power Source PCI Express 6 pin...

Page 11: ...1 B Bo oa ar rd d O Ov ve er rv vi ie ew w Figure 2 1 is the top and bottom view of the DE5 Net development board It depicts the layout of the board and indicates the location of the connectors and k...

Page 12: ...the flash memory on power up For programming by on board USB Blaster II the following procedures show how to download a configuration bit stream into the Stratix V GX FPGA Make sure that power is pro...

Page 13: ...M2210 System Controller with the Embedded Blaster CPLD D17 Error Illuminates when the MAX II CPLD EPM2210 System Controller fails to configure the FPGA Driven by the MAX II CPLD EPM2210 System Control...

Page 14: ...l positions as shown in 9Figure 2 3 Figure 2 3 6 Position DIP switch for Configure Mode Select Flash Image for Configuration The Image Select DIP switch SW5 is provided to specify the image for config...

Page 15: ...A User Defined Push buttons The FPGA board includes four user defined push buttons that allow users to interact with the Stratix V GX device Each push button provides a high logic level or a low logic...

Page 16: ...the DOWN position or the UPPER position it provides a low logic level or a high logic level to the Stratix V GX FPGA respectively as shown in 0Figure 2 6 Figure 2 6 4 Slide switches Table 2 4 lists t...

Page 17: ...g a logic 0 on the I O port turns the LED ON Driving a logic 1 on the I O port turns the LED OFF 2 5 V PIN_AW37 D9 LED1 2 5 V PIN_AV37 D10 LED2 2 5 V PIN_BB36 D11 LED3 2 5 V PIN_BB39 D7 1 LED_BRACKET0...

Page 18: ...mes and Functions Board Reference Schematic Signal Name Description I O Standard Stratix V GX Pin Number HEX1 HEX1_D0 User Defined 7 Segment Display Driving logic 0 on the I O port turns the 7 segment...

Page 19: ...MBus which is connected to the Stratix V GX FPGA In addition the 7 bit POR slave address for this sensor is set to 0011000b An optional 3 pin 12V fan located on J15 of the FPGA board is intended to re...

Page 20: ...tor so each bank of FPGA I O bank 3 4 7 8 has two clock inputs The three programming oscillators are low jitter oscillators which are used to provide special and high quality clock signals for high sp...

Page 21: ...atix V GX Pin Number Application Y4 OSC_50_B3B 50 0 MHz 2 5 V PIN_AW35 OSC_50_B3D 1 8 V PIN_BC28 OSC_50_B4A 1 8 V PIN_AP10 OSC_50_B4D 1 8 V PIN_AY18 OSC_50_B7A 1 5 V PIN_M8 OSC_50_B7D 1 5 V PIN_J18 OS...

Page 22: ...0 U49 CLOCK_SCL 2 5 V PIN_AE15 I2C bus direct connected with Si570 CLOCK_SDA 2 5 V PIN_AE16 CDCM61001 U53 PLL_SCL 2 5 V PIN_AF32 I2C bus connected with MAX II CPLD PLL_SDA 2 5 V PIN_AG32 CDCM61004 U28...

Page 23: ...driver outputs into a high impedance state 2 5 V PIN_AG14 RS422_DIN Receiver Output The data is send to FPGA PIN_AE18 RS422_DOUT Driver Input The data is sent from FPGA PIN_AE17 RS422_RE_n Receiver En...

Page 24: ...n the Flash Max and Stratix V GX FPGA Table 2 11 lists the flash pin assignments signal names and functions Table 2 11 Flash Memory Pin Assignments Schematic Signal Names and Functions Schematic Signa...

Page 25: ...PIN_AG26 FSM_D1 Data bus 2 5 V PIN_AD33 FSM_D2 Data bus 2 5 V PIN_AE34 FSM_D3 Data bus 2 5 V PIN_AF31 FSM_D4 Data bus 2 5 V PIN_AG28 FSM_D5 Data bus 2 5 V PIN_AG30 FSM_D6 Data bus 2 5 V PIN_AF29 FSM_D...

Page 26: ...N_AY30 FLASH_WE_n Write enable 2 5 V PIN_AR31 FLASH_ADV_n Address valid 2 5 V PIN_AK29 FLASH_RDY_BSY_n 0 Ready of flash 0 2 5 V PIN_BA29 FLASH_RDY_BSY_n 1 Ready of flash 1 2 5 V PIN_BB32 2 2 8 8 D DD...

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