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Chapter 3
Using the DE2i-150 Board
This chapter gives instructions for using the DE2i-150 board and describes each of its peripherals.
3
3
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1
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F
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In the DE2i-150 power up sequence, there is a monitor circuit that monitors the status of the FPGA
configuration. After it confirms the configuration is complete, the power up sequence will go to
next state. If the configuration is not complete, the CPU will not initiate.
There is a 2-position dip-switch (SW20, as shown in Figure 3.1) on this circuit, which can be used
for two settings.
The first switch configures TIMEOUT, which sets a timer in the monitor circuit to ignore any FPGA
configuration failure. When the counter goes to the set value, the power up sequence state continue
powering up the CPU regardless of whether the FPGA has not been configured normally or not.
The second switch position configures CPU_DIS, which disables CPU power up.
Table 3-1
shows the detailed setting for SW20.
