Altera Cyclone IV, Device Handbook

Page: 297 / 490

Chapter 1: Cyclone IV Transceivers Architecture 1–17
Receiver Channel Datapath
February 2015 Altera Corporation Cyclone IV Device Handbook,
Volume 2
Word Aligner
Figure 1–16 shows the word aligner block diagram. The word aligner receives parallel
data from the deserializer and restores the word boundary based on a pre-defined
alignment pattern that must be received during link synchronization. The word
aligner supports three operational modes as listed in
Table 1–3 .
Manual Alignment Mode
In manual alignment mode, the
rx_enapatternalign
port controls the word aligner
with either an 8- or 10-bit data width setting.
The 8-bit word aligner is edge-sensitive to the
rx_enapatternalign
signal. A rising
edge on
rx_enapatternalign
signal after deassertion of the
rx_digitalreset
signal
triggers the word aligner to look for the word alignment pattern in the received data
stream. It updates the word boundary if it finds the word alignment pattern in a new
word boundary. Any word alignment pattern received thereafter in a different word
boundary causes the word aligner to re-align to the new word boundary only if there
is a rising edge in the
rx_enapatternalign
signal.
The 10-bit word aligner is level-sensitive to the
rx_enapatternalign
signal. The word
aligner looks for the programmed 7-bit or 10-bit word alignment pattern or its
complement in the received data stream, if the
rx_enapatternalign
signal is held
high. It updates the word boundary if it finds the word alignment pattern in a new
word boundary. If the
rx_enapatternalign
signal is deasserted, the word aligner
maintains the current word boundary even when it receives the word alignment
pattern in a new word boundary.
Figure 1–16. Word Aligner Block Diagram
Word Aligner
Bit-Slip
Circuitry
Synchronization
State Machine
Manual
Alignment rx_bitslipboundaryselectout
Run Length
V iolation
rx_rl v
parallel data to
next PCS block
rx_syncstatus
rx_patterndetect
Recei v er
Polarity
In v ersion
rx_enapatternalign
data from
deserializer
rx_bitslip
rx_in v polarity
rx_re v bitorderwa
Recei v er
Bit
Re v ersal
Table 1–3. Word Aligner Modes
Modes PMA-PCS Interface Widths
Allowed Word Alignment
Pattern Lengths
Manual Alignment
8-bit 16 bits
10-bit 7 or 10 bits
Bit-Slip
8-bit 16 bits
10-bit 7 or 10 bits
Automatic Synchronization State
Machine
10-bit 7 or 10 bits