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Altera Cyclone IV GX FPGA, Reference Manual

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2–42

Chapter 2: Board Components

Memory

Cyclone IV GX FPGA Development Board

August 2015

Altera Corporation

Reference Manual

DDR2 SDRAM Bottom Port

The DDR2 SDRAM bottom port consists of two DDR2 devices (U17 and U19). 

Table 2–38

 lists the DDR2 bottom port pin assignments, signal names, and its 

functions. The signal names and types are relative to the Cyclone IV GX device in 
terms of I/O setting and direction.

Table 2–38. DDR2 SDRAM Bottom Port Pin Assignments, Signal Names and Functions (Part 1 of 2)

Board Reference

Description

Schematic Signal 

Name

I/O Standard

Cyclone IV GX 

Device 

Pin Number

U17.R2, U19.R2

Address bus

DDR2B_A12

1.8-V SSTL Class I

AB11

U17.P7, U19.P7

Address bus

DDR2B_A11

AE15

U17.M2, U19.M2

Address bus

DDR2B_A10

AH8

U17.P3, U19.P3

Address bus

DDR2B_A9

AG7

U17.P8, U19.P8

Address bus

DDR2B_A8

AA16

U17.P2, U19.P2

Address bus

DDR2B_A7

AG8

U17.N7, U19.N7

Address bus

DDR2B_A6

AH14

U17.N3, U19.N3

Address bus

DDR2B_A5

AK7

U17.N8, U19.N8

Address bus

DDR2B_A4

AG15

U17.N2, U19.N2

Address bus

DDR2B_A3

AH7

U17.M7, U19.M7

Address bus

DDR2B_A2

AB14

U17.M3, U19.M3

Address bus

DDR2B_A1

AK9

U17.M8, U19.M8

Address bus

DDR2B_A0

AG14

U17.L3, U19.L3

Bank address bus

DDR2B_BA1

AJ9

U17.L2, U19.L2

Bank address bus

DDR2B_BA0

AA12

U17.K7, U19.K7

Row address select

DDR2B_RASn

AG12

U17.L7, U19.L7

Column address select

DDR2B_CASn

AK10

U17.L8, U19.L8

Chip select

DDR2B_CSn

AK12

U17.K3, U19.K3

Write enable

DDR2B_WEn

AH10

U17.K9, U19.K9

Termination enable

DDR2B_ODT

AF13

U17.K2, U19.K2

Clock enable

DDR2B_CKE

AA13

U17.J8, U19.J8

Clock P

DDR2B_CLK_P

AF4

U17.K8, U19.K8

Clock N

DDR2B_CLK_N

AG4

U19.G8,

Data bus byte lane 0

DDR2B_DQ0

AG5

U19.G2

Data bus byte lane 0

DDR2B_DQ1

AJ3

U19.H7

Data bus byte lane 0

DDR2B_DQ2

AK4

U19.H3

Data bus byte lane 0

DDR2B_DQ3

AJ4

U19.H1

Data bus byte lane 0

DDR2B_DQ4

AH2

U19.H9

Data bus byte lane 0

DDR2B_DQ5

AH6

U19.F1

Data bus byte lane 0

DDR2B_DQ6

AF3

U19.F9

Data bus byte lane 0

DDR2B_DQ7

AK5

U19.F3

Write mask byte lane 0

DDR2B_DM0

AE3

U19.F7

Data strobe byte lane 0

DDR2B_DQS0

AD9

Summary of Contents for Cyclone IV GX FPGA

Page 1: ...101 Innovation Drive San Jose CA 95134 www altera com MNL 01058 1 2 Reference Manual Cyclone IV GX FPGA Development Board Feedback Subscribe ...

Page 2: ... products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to o...

Page 3: ...A Configuration using EPCS Device 2 15 Status Elements 2 16 Setup Elements 2 17 Board Settings DIP Switch 2 17 JTAG Chain Select DIP Switch 2 18 PCIe Control DIP Switch 2 19 Configuration Settings 2 19 Configuration Push Buttons 2 20 Clock Circuitry 2 20 General User Input Output 2 21 User Defined Push Buttons 2 21 User Defined LEDs 2 22 General User Defined LEDs 2 22 HSMC User Defined LEDs 2 22 U...

Page 4: ...ntents Cyclone IV GX FPGA Development Board August 2015 Altera Corporation Reference Manual Additional Information Document Revision History Info 1 How to Contact Altera Info 1 Typographic Conventions Info 2 ...

Page 5: ... to facilitate the development of the Cyclone IV GX FPGA designs f For more information on the Cyclone IV device family refer to the Cyclone IV Device Handbook Board Component Blocks The board features the following major component blocks Cyclone IV GX EP4CGX150DF31 FPGA in the 896 pin FineLine BGA FBGA package 1 2 V core power MAX II EPM2210GF256 CPLD in the 256 pin FBGA package 1 8 V core power ...

Page 6: ...play Eight FPGA user LEDs One configuration done LED One error LED Five Ethernet status LEDs One USB status LED One power status LED Five configuration LEDs A two line 16 character LCD display Push buttons One CPU reset push button One MAX II configuration reset push button One program load push button configure the FPGA from flash memory One program select push button select image to load from fl...

Page 7: ...ram Figure 1 1 shows the block diagram of the Cyclone IV GX FPGA development board Figure 1 1 Cyclone IV GX FPGA Development Board Block Diagram EP4CGX150DF31 XCVR x4 10 100 1000 Ethernet RGMII Translator User LEDs Push Button Switches 14 pin LCD Header CPLD x18 64 MB Flash x16 4 MB SSRAM x18 RJ45 Jack Power Measure 1 8 V CMOS 1 8 V CMOS LVDS 1 8 V 2 5 V Port B USB Blaster 100 MHz XTAL SMA Input 1...

Page 8: ... 2015 Altera Corporation Reference Manual Handling the Board When handling the board it is important to observe the following static discharge precaution c Without proper anti static handling the board can be damaged Therefore use anti static handling precautions when touching the board ...

Page 9: ...side in the Cyclone IV GX FPGA development kit documents directory f For information about powering up the board and installing the demonstration software refer to the Cyclone IV GX FPGA Development Kit User Guide This chapter consists of the following sections Board Overview Featured Device Cyclone IV GX Device on page 2 5 MAX II CPLD EPM2210 System Controller on page 2 7 Configuration Status and...

Page 10: ...e B Connector J4 RJ 45 Connector J7 JTAG Connector J6 Configuration Done Load Error EPCS User and Factory LEDs D16 D21 Load Push Button Switch S8 Power LED D11 HSMC Port A J1 User Push Button Switches S1 S4 User DIP Switch SW2 Clock output SMA Connector J9 HSMC Port B J2 Gigabit Ethernet U21 HSMC Bank Selection Jumper J3 Board Settings DIP Switch SW1 DDR2A x32 U8 U15 EPCS Device U18 PCI Express Co...

Page 11: ...0 System Controller S6 CPU reset push button Press to reset the FPGA logic S7 Program select push button Toggles the LEDs which selects the program image that loads either from the flash memory FPP mode or the EPCS device active serial mode to the FPGA S8 Program load push button Configure the FGPA from flash memory based on the program select LEDs setting Clock Circuitry X2 125 MHz oscillator 125...

Page 12: ...E T Ethernet connection via a Marvell 88E1111 PHY and the FPGA based Altera Triple Speed Ethernet MegaCore function in RGMII mode U21 Gigabit Ethernet A Marvell 88E1111 PHY device for 10 100 1000 BASE T Ethernet connection The device is an auto negotiating Ethernet PHY with an RGMII interface to the FPGA J14 PCIe edge connector Interfaces to a PCIe root port such as an appropriate PC motherboard M...

Page 13: ...ribes the features of the Cyclone IV GX EP4CGX150DF31 device Table 2 3 lists the Cyclone IV GX device component reference and manufacturing information Table 2 2 Cyclone IV GX EP4CGX150DF31 Device Features Equivalent LEs Embedded Memory Kbits 18 bit 18 bit Multipliers Transceivers PLLs User I O Package Type 149 760 6 480 360 8 8 475 896 pin FBGA Table 2 3 Cyclone IV GX Device Component Reference a...

Page 14: ...ifferential HSTL 12 Class II is supported only in column I O banks 4 7 and 8 7 BLVDS output uses two single ended outputs with the second output programmed as inverted BLVDS input uses the LVDS input buffer 8 The PCI X I O standard does not meet the IV curve requirement at the linear region 9 The OCT block is located in the shaded banks 4 5 and 7 10 The dedicated clock input I O banks 3A 3B 8A and...

Page 15: ... for clocks Control registers for remote system update Table 2 4 Cyclone IV GX Device I O Pin Count and Usage Function I O Standard I O Count Special Pins Clocks or Oscillators 1 8 V CMOS 9 3 clock inputs 1 clock input DDR2A x32 Top 1 8 V SSTL 63 DDR2B x32 Bottom 1 8 V SSTL 63 Flash SSRAM MAX 1 8 V CMOS 55 Gigabit Ethernet 2 5 V CMOS 1 16 User I O LEDs Push buttons 1 8 V 25 14 pin LCD 2 5 V CMOS 1...

Page 16: ...0 System Controller Power Calculations SLD HUB PFL Power Measurement Results Virtual JTAG PC EP4CGX150 EPCS LTC2418 Controller FLASH Decoder Encoder JTAG Control Control Register Clock Controller Programmable Clock Configuration State Machine User Factory DIP Switch Configuration Push Buttons Configuration Signals GPIO on MAX Device Configuration Status LEDs Table 2 5 MAX II CPLD EPM2210 System Co...

Page 17: ...us flash memory chip enable FPGA_DATA0 2 5 V D3 A3 FPGA data FPGA_DATA1 L1 G9 FPGA data FPGA_DATA2 J16 H9 FPGA data FPGA_DATA3 J13 D1 FPGA data FPGA_DATA4 H16 C2 FPGA data FPGA_DATA5 H13 AE4 FPGA data FPGA_DATA6 H15 AE5 FPGA data FPGA_DATA7 H14 AE10 FPGA data FPGA_DCLK C2 B3 FPGA configuration clock FPGA_CONF_DONE E3 B1 FPGA configuration done FPGA_STATUSn C3 AJ1 FPGA configuration ready FPGA_CONF...

Page 18: ...FSM bus address FSM_A10 N6 AK23 FSM bus address FSM_A11 P4 AH17 FSM bus address FSM_A12 P5 AB21 FSM bus address FSM_A13 N8 AF19 FSM bus address FSM_A14 T6 AF12 FSM bus address FSM_A15 N5 AG27 FSM bus address FSM_A16 M6 AK26 FSM bus address FSM_A17 N7 AH4 FSM bus address FSM_A18 T5 AK3 FSM bus address FSM_A19 R1 AH9 FSM bus address FSM_A20 M7 AG6 FSM bus address FSM_A21 T2 AK25 FSM bus address FSM_...

Page 19: ...CS G3 MAX II EPCS memory chip enable MAX_ERROR G2 FPGA configuration error LED MAX_FACTORY G4 FPGA factory configuration LED MAX_USER G1 FPGA user configuration LED MAX_FAN 1 8 V B1 FPGA fan LED MAX_CSn L16 B12 MAX II chip select MAX_OEn K13 G8 MAX II output enable MAX_WEn K15 A9 MAX II write enable MSEL0 2 5 V L2 AD7 FPGA MSEL0 configuration mode select MSEL2 M1 AC7 FPGA MSEL2 configuration mode ...

Page 20: ... button switch S8 is pressed External USB Blaster for configuring the FPGA using an external USB Blaster Serial configuration EPCS device U18 is used to store configuration data for FPGA device that supports active serial AS configuration and reloads the data to the FPGA upon reconfiguration Use the program select push button switch S7 to select the configuration files to be loaded from either pag...

Page 21: ...rposes The MAX II CPLD EPM2210 System Controller contains the required state machine and control logic to determine the configuration source for the Cyclone IV GX FPGA Figure 2 4 JTAG Chain Embedded Blaster GPIO TCK EP4CGX150 FPGA Analog Switch EPM2210 System Controller HSMC Port A HSMC Port B GPIO TMS GPIO TDO GPIO TDI JTAG Master GPIO DISABLED JTAG Master Slave JTAG Master Slave Installed HSMC C...

Page 22: ...memory over the USB interface using the Quartus II software This method is used to restore the development board to its factory default settings Other methods to program the flash memory can be used as well including the Nios II processor f For more information on the Nios II processor refer to the Nios II Processor page of the Altera website FPGA Configuration from Flash Memory On either power up...

Page 23: ...utton S7 to select the AS configuration scheme After programming the EPCS device press the program load push button S8 load the design from the EPCS device to the FPGA when you power up the board EPCS Programming EPCS programming is possible through a variety of methods One method to program the EPCS device is to use the Serial FlashLoader SFL a JTAG based in system programming solution for Altera...

Page 24: ...ontroller D19 D20 D21 PROGRAM MAX_EPCS MAX_USER MAX_FACTORY Green LEDs Illuminates to show the LED sequence that determines which flash memory image is loaded to the FPGA The image to be loaded depends on the selection of the three LEDs Driven by the MAX II CPLD EPM2210 System Controller D22 USB Green LED Illuminates when the embedded USB Blaster is in use to program the FPGA Driven by the MAX II ...

Page 25: ...le 2 10 shows the switch controls and descriptions Table 2 9 Board Specific LEDs Component References and Manufacturing Information Board Reference Description Manufacturer Manufacturer Part Number Manufacturer Website D17 D18 Red LED Lumex Inc SML LXT0805IW TR www lumex com D1 D2 D11 D16 D19 D22 D24 D27 D30 D31 Green LEDs Lumex Inc SML LXT0805GW TR www lumex com D11 Blue LED Lumex Inc SML LX1206U...

Page 26: ... TDA04H0SB1 www ck components com Table 2 12 JTAG Chain Select DIP Switch Controls Board Reference Schematic Signal Name Description Default 1 SW5 1 EPM2210_JTAG_EN ON Bypass Max II CPLD EPM2210 System Controller OFF Max II CPLD EPM2210 System Controller in chain OFF SW5 2 HSMA_JTAG_EN ON Bypass HSMC port A OFF HSMC port A in chain OFF SW5 3 HSMB_JTAG_EN ON Bypass HSMC port B OFF HSMC port B in ch...

Page 27: ...e detect OFF Disable x4 presence detect ON SW4 4 USB_DISABLE ON Embedded USB Blaster disabled OFF Embedded USB Blaster enabled OFF Note to Table 2 14 1 ON indicates a setting of 0 while OFF indicates a setting of 1 Table 2 15 PCIe Control DIP Switch Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturer Part Number Manufacturer Website SW4 Four posi...

Page 28: ... on board programmable oscillator or a bench supply clock can be distributed to these dedicated clock inputs The clock going to bank 3B is a dedicated clock input for 3G applications The non dedicated clocks are located on banks 3A and 8A of the Cyclone IV GX device The PCIe reference clock is on bank 3A while the 125 MHz clock is on bank 8A Figure 2 5 shows the Cyclone IV GX FPGA development boar...

Page 29: ... S5 resets the MAX II CPLD EPM2210 System Controller The CPU reset push button CPU_RESETn S6 resets the FPGA design loaded into the Cyclone IV GX device This switch also acts as a regular I O pin Table 2 18 lists the user defined push button schematic signal names and their corresponding Cyclone IV GX device pin numbers Table 2 19 lists the user defined push button component reference and the manu...

Page 30: ...ble 2 21 lists the user defined LED component reference and the manufacturing information HSMC User Defined LEDs The HSMC port A and B have two LEDs located nearby There are no board specific functions for the HSMC LEDs However the LEDs are labeled TX and RX and are intended to display data flow to and from the connected HSMC cards The LEDs are driven by the Cyclone IV GX device Table 2 20 User De...

Page 31: ...ber D4 User Defined LEDs Labeled RX for HSMC Port A HSMA_RX_LED 2 5 V C24 D3 User Defined LEDs Labeled TX for HSMC Port A HSMA_TX_LED B25 D6 User Defined LEDs Labeled RX for HSMC Port B HSMB_RX_LED C10 D5 User Defined LEDs Labeled TX for HSMC Port B HSMB_TX_LED D25 Table 2 23 HSMC User Defined LED Component Reference and Manufacturing Information Board Reference Device Description Manufacturer Man...

Page 32: ...anufacturing Information Board Reference Device Description Manufacturer Manufacturer Part Number Manufacturer Website SW2 Eight Position DIP switch C K Components TDA08H0SB1 www ck components com Table 2 26 LCD Pin Assignments Schematic Signal Names and Functions Board Reference Description Schematic Signal Name I O Standard Cyclone IV GX Device Pin Number J13 4 LCD data or command select LCD_D_C...

Page 33: ...LCD component references and the manufacturing information Table 2 27 LCD Pin Definitions and Functions Pin Number Symbol Level Function 1 VDD Power supply 5 V 2 VSS GND 0 V 3 V0 For LCD drive 4 RS H L Register select signal H Data input L Instruction input 5 R W H L H Data read module to MPU L Data write MPU to module 6 E H H to L Enable 7 14 DB0 DB7 H L Data bus software selectable 4 bit or 8 bi...

Page 34: ...ourced entirely from the PCIe edge connector when installed into a PC motherboard Turn the power switch SW3 to the ON position when you install the board into a PC motherboard Although the board can also be powered by a laptop power supply for use on a lab bench it is not recommended to use from both supplies at the same time Ideal diode power sharing devices have been designed into this board to ...

Page 35: ...J14 B15 Add in card receive bus PCIE_RX_N0 AC1 1 J14 B19 Add in card receive bus PCIE_RX_P1 AA2 1 J14 B20 Add in card receive bus PCIE_RX_N1 AA1 1 J14 B23 Add in card receive bus PCIE_RX_P2 W2 1 J14 B24 Add in card receive bus PCIE_RX_N2 W1 1 J14 B27 Add in card receive bus PCIE_RX_P3 U2 1 J14 B28 Add in card receive bus PCIE_RX_N3 U1 1 J14 A13 Motherboard reference clock PCIE_REFCLK_P HCSL V15 J1...

Page 36: ...Speed Ethernet MegaCore design The Marvell 88E1111 PHY uses 2 5 V and 1 1 V power rails and requires a 25 MHz reference clock driven from a dedicated oscillator The device interfaces to a Halo Electronics HFJ11 1G02E model RJ45 with internal magnetics that can be used for driving copper lines with Ethernet traffic The PHY address on the management data input output MDIO bus is 0b10010 0x12 Figure ...

Page 37: ...2 D10 U21 14 RGMII TX data ENET_T_TX_D3 B10 U21 8 RGMII TX clock ENET_T_GTX_CLK D9 U21 9 RGMII TX control ENET_T_TX_EN A27 U21 95 RGMII RX data ENET_T_RX_D0 F5 U21 92 RGMII RX data ENET_T_RX_D1 B9 U21 93 RGMII RX data ENET_T_RX_D2 G14 U21 91 RGMII RX data ENET_T_RX_D3 E13 U21 2 RGMII RX clock ENET_T_RX_CLK B15 U21 94 RGMII RX data valid ENET_T_RX_DV E15 U21 25 Management bus control ENET_T_MDC K21...

Page 38: ...e ground pins are located between the two rows of signal and power pins acting both as a shield and a reference The HSMC host connector is based on the 0 5 mm pitch QSH QTH family of high speed board to board connectors from Samtec There are three banks in this connector Bank 1 has every third pin removed as done in the QSH DP QTH DP series Bank 2 and bank 3 have all the pins populated as done in ...

Page 39: ... 2 HSMA_RX_P2 L2 J1 24 Transceiver RX bit 2n HSMA_RX_N2 L1 J1 25 Transceiver TX bit 1 HSMA_TX_P1 M4 J1 27 Transceiver TX bit 1n HSMA_TX_N1 M3 J1 26 Transceiver RX bit 1 HSMA_RX_P1 N2 J1 28 Transceiver RX bit 1n HSMA_RX_N1 N1 J1 29 Transceiver TX bit 0 HSMA_TX_P0 P4 J1 31 Transceiver TX bit 0n HSMA_TX_N0 P3 J1 30 Transceiver RX bit 0 HSMA_RX_P0 R2 J1 32 Transceiver RX bit 0n HSMA_RX_N0 2 5 V R1 J1 ...

Page 40: ...SMA_RX_D_P3 N25 J1 67 LVDS TX bit 3n or CMOS bit 18 HSMA_TX_D_N3 E30 J1 68 LVDS RX bit 3n or CMOS bit 19 HSMA_RX_D_N3 M26 J1 71 LVDS TX bit 4 or CMOS bit 20 HSMA_TX_D_P4 F28 J1 72 LVDS RX bit 4 or CMOS bit 21 HSMA_RX_D_P4 R24 J1 73 LVDS TX bit 4n or CMOS bit 22 HSMA_TX_D_N4 F29 J1 74 LVDS RX bit 4n or CMOS bit 23 HSMA_RX_D_N4 P25 J1 77 LVDS TX bit 5 or CMOS bit 24 HSMA_TX_D_P5 H30 J1 78 LVDS RX bi...

Page 41: ... 119 LVDS TX bit 11 or CMOS bit 52 HSMA_TX_D_P11 L27 J1 120 LVDS RX bit 11 or CMOS bit 53 HSMA_RX_D_P11 T28 J1 121 LVDS TX bit 11n or CMOS bit 54 HSMA_TX_D_N11 L28 J1 122 LVDS RX bit 11n or CMOS bit 55 HSMA_RX_D_N11 R29 J1 125 LVDS TX bit 12 or CMOS bit 56 HSMA_TX_D_P12 M27 J1 126 LVDS RX bit 12 or CMOS bit 57 HSMA_RX_D_P12 R25 J1 127 LVDS TX bit 12n or CMOS bit 58 HSMA_TX_D_N12 M28 J1 128 LVDS RX...

Page 42: ...Description Schematic Signal Name I O Standard Cyclone IV GX Device Pin Number Table 2 34 HSMC Port B Pin Assignments Schematic Signal Names and Functions Part 1 of 5 Board Reference Description Schematic Signal Name I O Standard Cyclone IV GX Device Pin Number Other Connections J2 17 Transceiver TX bit 3 HSMB_TX_P3 1 5 V C329 1 J2 18 Transceiver RX bit 3 HSMB_RX_P3 R97 2 J2 19 Transceiver TX bit ...

Page 43: ...4 HSMB_TX_D_N2 AB26 J2 62 CMOS bit 15 HSMB_RX_D_N2 AB25 J2 65 CMOS bit 16 HSMB_TX_D_P3 AG30 J2 66 CMOS bit 17 HSMB_RX_D_P3 AE28 J2 67 CMOS bit 18 HSMB_TX_D_N3 V21 J2 68 CMOS bit 19 HSMB_RX_D_N3 AD26 J2 71 CMOS bit 20 HSMB_TX_D_P4 AF28 J2 72 CMOS bit 21 HSMB_RX_D_P4 AC25 J2 73 CMOS bit 22 HSMB_TX_D_N4 AE27 J2 74 CMOS bit 23 HSMB_RX_D_N4 AD25 J2 77 CMOS bit 24 HSMB_TX_D_P5 AE26 J2 78 CMOS bit 25 HSM...

Page 44: ... 52 HSMB_T_TX_D_P11 U29 13 J2 120 CMOS bit 53 HSMB_T_RX_D_P11 U37 19 J2 121 CMOS bit 54 HSMB_T_TX_D_N11 U29 14 J2 122 CMOS bit 55 HSMB_T_RX_D_N11 U37 14 J2 125 CMOS bit 56 HSMB_T_TX_D_P12 U36 19 J2 126 CMOS bit 57 HSMB_T_RX_D_P12 U37 13 J2 127 CMOS bit 58 HSMB_T_TX_D_N12 U29 15 J2 128 CMOS bit 59 HSMB_T_RX_D_N12 U38 18 J2 131 CMOS bit 60 HSMB_T_TX_D_P13 U29 16 J2 132 CMOS bit 61 HSMB_T_RX_D_P13 U2...

Page 45: ...SMB_CLK_IN_P2 1 8 V AG22 U33 3 Dedicated CMOS clock out HSMB_CLK_OUT_P2 AG19 U34 4 HSMB_RX_D_N6 AE19 U38 5 HSMB_RX_D_N7 AJ25 U38 9 HSMB_RX_D_N8 Y20 U38 8 HSMB_RX_D_N9 AE17 U37 4 HSMB_RX_D_N10 AA20 U38 7 HSMB_RX_D_N11 AK19 U37 7 HSMB_RX_D_N12 AG20 U38 3 HSMB_RX_D_N13 AD10 U29 4 HSMB_RX_D_N14 AF18 U38 2 HSMB_RX_D_N15 AG3 U28 4 HSMB_RX_D_N16 AD16 U37 9 HSMB_RX_D_P6 AE20 U38 4 HSMB_RX_D_P7 AG23 U38 6 ...

Page 46: ...MB_TX_D_P9 AJ22 U35 4 HSMB_TX_D_P10 AH26 U36 4 HSMB_TX_D_P11 AK21 U29 8 HSMB_TX_D_P12 AE23 U36 2 HSMB_TX_D_P13 AF10 U29 5 HSMB_TX_D_P14 AK24 U35 8 HSMB_TX_D_P15 AD22 U35 6 HSMB_TX_D_P16 AF25 U35 9 HSMBT_CLK_IN0 AJ16 U30 3 Table 2 34 HSMC Port B Pin Assignments Schematic Signal Names and Functions Part 5 of 5 Board Reference Description Schematic Signal Name I O Standard Cyclone IV GX Device Pin Nu...

Page 47: ...r two are pinned out to FPGA bank 7 and 8 top port These memory interfaces are designed to run at a maximum frequency of 167 MHz for a maximum theoretical bandwidth of over 10 6 Gbps The internal bus in the FPGA is typically 2 or 4 times the width at full rate or half rate respectively For example a 167 MHz 16 bit interface becomes a 83 5 MHz 64 bit bus HSMB_TX_N1 XCVR_TX_N1 Y3 HSMB_TX_N2 XCVR_TX_...

Page 48: ...U8 N3 U15 N3 Address bus DDR2A_A5 B21 U8 N8 U15 N8 Address bus DDR2A_A4 F18 U8 N2 U15 N2 Address bus DDR2A_A3 A21 U8 M7 U15 M7 Address bus DDR2A_A2 D17 U8 M3 U15 M3 Address bus DDR2A_A1 C19 U8 M8 U15 M8 Address bus DDR2A_A0 D18 U8 L3 U15 L3 Bank address bus DDR2A_BA1 B19 U8 L2 U15 L2 Bank address bus DDR2A_BA0 A20 U8 K7 U15 K7 Row address select DDR2A_RASn B18 U8 L7 U15 L7 Column address select DD...

Page 49: ... bus byte lane 2 DDR2A_DQ19 A17 U15 H1 Data bus byte lane 2 DDR2A_DQ20 A23 U15 H9 Data bus byte lane 2 DDR2A_DQ21 E18 U15 F1 Data bus byte lane 2 DDR2A_DQ22 C22 U15 F9 Data bus byte lane 2 DDR2A_DQ23 K18 U15 F3 Write mask byte lane 2 DDR2A_DM2 B16 U15 F7 Data strobe byte lane 2 DDR2A_DQS2 K19 U15 C8 Data bus byte lane 3 DDR2A_DQ24 A13 U15 C2 Data bus byte lane 3 DDR2A_DQ25 C14 U15 D7 Data bus byte...

Page 50: ... U19 N3 Address bus DDR2B_A5 AK7 U17 N8 U19 N8 Address bus DDR2B_A4 AG15 U17 N2 U19 N2 Address bus DDR2B_A3 AH7 U17 M7 U19 M7 Address bus DDR2B_A2 AB14 U17 M3 U19 M3 Address bus DDR2B_A1 AK9 U17 M8 U19 M8 Address bus DDR2B_A0 AG14 U17 L3 U19 L3 Bank address bus DDR2B_BA1 AJ9 U17 L2 U19 L2 Bank address bus DDR2B_BA0 AA12 U17 K7 U19 K7 Row address select DDR2B_RASn AG12 U17 L7 U19 L7 Column address ...

Page 51: ...Data bus byte lane 2 DDR2B_DQ21 AH16 U17 F1 Data bus byte lane 2 DDR2B_DQ22 AJ7 U17 F9 Data bus byte lane 2 DDR2B_DQ23 AB16 U17 F3 Write mask byte lane 2 DDR2B_DM2 AH18 U17 F7 Data strobe byte lane 2 DDR2B_DQS2 AF15 U17 C8 Data bus byte lane 3 DDR2B_DQ24 AH18 U17 C2 Data bus byte lane 3 DDR2B_DQ25 AK17 U17 D7 Data bus byte lane 3 DDR2B_DQ26 AJ18 U17 D3 Data bus byte lane 3 DDR2B_DQ27 AK18 U17 D1 D...

Page 52: ...gnal Names and Functions Part 1 of 2 Board Reference Description Schematic Signal Name I O Standard Cyclone IV GX Device Pin Number U44 46 Address bus FSM_A1 1 8 V AD6 U44 44 Address bus FSM_A2 AK29 U44 42 Address bus FSM_A3 AA21 U44 37 Address bus FSM_A4 AG25 U44 36 Address bus FSM_A5 AH5 U44 48 Address bus FSM_A6 AH27 U44 43 Address bus FSM_A7 AJ12 U44 49 Address bus FSM_A8 AF16 U44 47 Address b...

Page 53: ...led high U44 84 Address strobe Processor Cache Controller active low SSRAM_ADSPn Pulled high U44 85 Address strobe Processor Cache Controller active low SSRAM_ADSCn Pulled low U44 86 Output enable active low SSRAM_Gn G6 U44 87 Byte lane write enable SSRAM_BWn F8 U44 89 Clock SSRAM_CLK F11 U44 98 Chip enable 1 SSRAM_E1n C6 U44 97 Chip enable 2 SSRAM_E2 Pulled high U44 92 Chip enable 3 SSRAM_E3n Pul...

Page 54: ...al names and functions The signal names and types are relative to the Cyclone IV GX device in terms of I O setting and direction Table 2 42 Flash Pin Assignments Schematic Signal Names and Functions Part 1 of 2 Board Reference Description Schematic Signal Name I O Standard Cyclone IV GX Device Pin Number U6 F6 Address valid FLASH_ADVn 1 8 V F24 U6 B4 Chip enable FLASH_CEn E25 U6 E6 Clock FLASH_CLK...

Page 55: ...dress bus FSM_A24 AK27 U6 B6 Address bus FSM_A25 AF21 U6 F2 Data bus FSM_D0 AK14 U6 E2 Data bus FSM_D1 AE6 U6 G3 Data bus FSM_D2 AG21 U6 E4 Data bus FSM_D3 AE9 U6 E5 Data bus FSM_D4 AK28 U6 G5 Data bus FSM_D5 AD23 U6 G6 Data bus FSM_D6 AG24 U6 H7 Data bus FSM_D7 AB22 U6 E1 Data bus FSM_D8 AE22 U6 E3 Data bus FSM_D9 AJ24 U6 F3 Data bus FSM_D10 Y19 U6 F4 Data bus FSM_D11 AH23 U6 F5 Data bus FSM_D12 ...

Page 56: ...ervative absolute maximum levels and reflects the regulator inefficiencies and sharing Figure 2 7 Power Distribution System 1 2V_VCCL_GXB VCCP_PCC VCC 16 V DC INPUT ideal diode mux 12 V PCI Express Motherboard 5 5 A Maximum VCCA 2 5V_VCCA_VCCH_GXB Linear Regulator LTC3853 Linear Regulator LTC3850 Linear Regulator LTC3027 12V_HSMC 1 8V 3 3V 5V 2 5V_USB U43 U50 U41 Shunt installed 2 5 V Shunt not in...

Page 57: ...s named the power is the total output power for that voltage Table 2 44 Power Supply Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Website 16 V power supply EDAC Power Electronics EA1060A www edac com tw Figure 2 8 Power Measurement Circuit SCK DSI DSO CSn 8 Ch To Plane Supply RSENSE EPM2210 EP4CGX150 LTC2418 EPM 2...

Page 58: ... Manufacturing Part Number Manufacturer Website U13 8 channel differential input 24 bit ADC Linear Technology LTC2418 www linear com Table 2 47 Table of Hazardous Substances Name and Concentration Notes 1 2 Part Name Lead Pb Cadmium Cd Hexavalent Chromium Cr6 Mercury Hg Polybrominated biphenyls PBB Polybrominated diphenyl Ethers PBDE Cyclone IV GX FPGA development board X 0 0 0 0 0 16 V power supp...

Page 59: ...able 2 26 All signals are translated from 1 8 V to 2 5 V using a dual quad low voltage level translators except for LCD_DATA4 Updated Table 2 29 The I O standard for PCI Express transmit and receive bus is 1 5 V PCML Updated Table 2 33 HSMA pin J1 44 connects to FPGA pin AD27 Updated the document template December 2010 1 0 Initial release Contact 1 Contact Method Address Technical support Website ...

Page 60: ...t The suffix n denotes an active low signal For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI r An angled arrow instructs you t...

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