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Altera Cyclone III LS Reference Manual Download Page 19

Chapter 2:  Board Components

2–11

Configuration, Status, and Setup Elements

© October 2009  Altera Corporation

Cyclone III LS FPGA Development Board Reference Manual

Configuration, Status, and Setup Elements

This section describes the board's configuration, status, and setup elements.

Configuration

This section describes the FPGA, flash memory, and MAX

 

II CPLD EPM2210 System 

Controller device programming methods supported by the Cyclone III LS FPGA 
development board. The Cyclone III LS FPGA development board supports the 
following three configuration methods:

■

Embedded USB-Blaster is the default method for configuring the FPGA at any 
time using the Quartus II Programmer in JTAG mode with the supplied USB cable.

■

Flash memory download is used for storing FPGA images which the MAX

 

II 

CPLD EPM2210 System Controller uses to configure the Cyclone III LS device 
either on board power up or after the the PGM configure push-button switch (S8) 
is pressed.

■

External USB-Blaster for configuring the FPGA using an external USB-Blaster.

FPGA Programming over Embedded USB-Blaster

The USB-Blaster is implemented using a USB Type-B connector (J4), a FTDI USB 2.0 
PHY device (U11), and an Altera MAX IIZ CPLD (U13). This allows the configuration 
of the FPGA using a USB cable directly connected between the USB port on the board 
(J4) and a USB port of a PC running the Quartus II software. The JTAG chain is 
normally mastered by the embedded USB-Blaster found in the MAX

 

IIZ CPLD 

EPM240Z.

The embedded USB-Blaster is automatically disabled when an external USB-Blaster is 
connected to the JTAG chain. 

Figure 2–4

 illustrates the JTAG chain.

Summary of Contents for Cyclone III LS

Page 1: ...101 Innovation Drive San Jose CA 95134 www altera com Cyclone III LS FPGA Development Board Reference Manual Document Version 1 0 Document Date October 2009...

Page 2: ...gn patents and pending ap plications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty bu...

Page 3: ...GA Programming over External USB Blaster 2 16 Status Elements 2 16 Setup Elements 2 17 Board Settings DIP Switch 2 17 JTAG Chain Header Switch 2 18 Anti Tamper JTAG Select Header Switch 2 19 LCD HSMC...

Page 4: ...iv Cyclone III LS FPGA Development Board Reference Manual October 2009 Altera Corporation ary Additional Information Revision History Info 1 How to Contact Altera Info 1 Typographic Conventions Info 2...

Page 5: ...e a list of the latest HSMCs available or to download a copy of the HSMC specification refer to the Development Board Daughtercards page of the Altera website www altera com The Cyclone III LS FPGAs a...

Page 6: ...5 V core power FPGA configuration circuitry MAX II CPLD EPM2210 System Controller and flash passive serial PS configuration On board USB BlasterTM for use with the Quartus II Programmer On Board ports...

Page 7: ...switches One CPU reset push button switch One MAX II configuration reset push button switch One PGM configure push button switch configure the FPGA from flash memory One PGM select push button switch...

Page 8: ...refore use anti static handling precautions when touching the board Figure 1 1 Cyclone III LS FPGA Development Board Block Diagram EP3CLS200F780 Port B Port A EEPROM 32 Kbit I2C 2x16 LCD Push button S...

Page 9: ...he board and installing the demonstration software refer to the Cyclone III LS FPGA Development Kit User Guide This chapter consists of the following sections Board Overview Featured Device Cyclone II...

Page 10: ...Chain Header JTAG Select Jumpers J11 J12 CRC Error S1 JTAG Anti Tamper Select LEDs D6 D9 LCD HSMC Port B Data Select J18 VCCA Shutdown Push Button Switch S11 Table 2 1 Cyclone III LS FPGA Development...

Page 11: ...1 VCCA shutdown push button switch Turns VCCA power to the FPGA on and off This switch initiates a power on reset S10 MAX II reset push button switch Press to reset the MAX II CPLD EPM2210 System Cont...

Page 12: ...ides a 16 bit 64 Mbyte non volatile memory port U21 EEPROM I2C EEPROM Components and Interfaces J2 HSMC port A Provides 80 CMOS or 17 LVDS channels per the HSMC specification J1 HSMC port B Provides 7...

Page 13: ...Manufacturer Website U15 FPGA Cyclone III LS F780 198K LEs lead free AlteraCorporation EP3CLS200F780C7N www altera com Figure 2 2 EP3CLS200 Device I O Bank Diagram B8 58 I O B7 59 I O B6 48 I O B5 52...

Page 14: ..._at_example txt directory Figure 2 3 illustrates the MAX II CPLD EPM2210 System Controller s functionality and external circuit connections as a block diagram LEDs 1 8 V CMOS 5 1 INIT_DONE Clocks or O...

Page 15: ...nti Tamper FPGA general I O FLASH_ADVn B3 AF18 FSM bus flash memory address valid FLASH_CEn E6 AH22 FSM bus flash memory chip enable FLASH_CLK C6 AH6 FSM bus flash memory clock FLASH_OEn B4 AD7 FSM bu...

Page 16: ...10 AA9 FSM bus address FSM_A19 C9 AE6 FSM bus address FSM_A20 A10 AG18 FSM bus address FSM_A21 D9 AE11 FSM bus address FSM_A22 B9 AB16 FSM bus address FSM_A23 D4 AE13 FSM bus address FSM_A24 B1 AG11 F...

Page 17: ...CURE R5 DIP JTAG security mode ON OFF M2Z_CONF_DONE R13 On board USB Blaster FPGA configuration done M2Z_D0 T15 On board USB Blaster FPGA configuration data M2Z_DCLK N12 On board USB Blaster FPGA conf...

Page 18: ...R1 L15 Programmable oscillator prescaler 1 PLL_RSTn N16 Programmable oscillator reset SECURITY K3 AG12 Anti Tamper FPGA general I O SECURITY_LED0 L1 Anti Tamper example design security LED0 SECURITY_L...

Page 19: ...ble Flash memory download is used for storing FPGA images which the MAX II CPLD EPM2210 System Controller uses to configure the Cyclone III LS device either on board power up or after the the PGM conf...

Page 20: ...TAG chain breaks and the MAX II EPM2210 System Controller gains control of the FPGA JTAG For more information on the anti tamper example design refer to install_dir kits cycloneIIILS_3cls200_fpga exam...

Page 21: ...device FPGA or CPLD The PFL functions as a utility for writing to a compatible flash memory device This pre built design contains the PFL megafunction that allows you to write either page 0 page 1 or...

Page 22: ...nCE CFI Flash FLASH_CEn FLASH_OEn FLASH_WEn FLASH_A 25 1 FLASH_D 15 0 FLASH_CEn FLASH_OEn FLASH_WEn FLASH_WPn FLASH_RYBSYn FLASH_RYBSYn FPGA_nCONFIG FPGA_CONF_DONE FLASH_ADVn FPGA_nSTATUS 2 5 V 10 k...

Page 23: ...ardware page that loads when the PGM configure push button switch S8 is pressed Table 2 7 Flash Memory Map Name Size Address Unused 32 KB 0x03FF FFFF 0x03FF 8000 32 KB 0x03FF 7FFF 0x03FF 0000 32 KB 0x...

Page 24: ...2 9 lists the LED board references names and functional descriptions Table 2 8 PGM Configure Push Button Switch S8 LED Settings 1 PGM_LED0 PGM_LED1 PGM_LED2 Design ON OFF OFF Factory hardware OFF ON...

Page 25: ...receive activity Driven by the Marvell 88E1111 PHY D20 10 Green LED Illuminates to indicate Ethernet linked at 10 Mbps connection speed Driven by the Marvell 88E1111 PHY D16 100 Green LED Illuminates...

Page 26: ...F Cyclone III LS JTAG lock feature active ON 5 USB_DISABLEn ON Embedded USB Blaster disable OFF Embedded USB Blaster enable OFF 6 USER_PGM ON Load factory design from flash memory upon power up OFF Lo...

Page 27: ...control data multiplexing of the LCD and HSMB_D 65 75 signals to the Cyclone III LS device If the shunt is not placed on the jumper the FPGA can control the LCD_HSMB_SEL signal The default value of th...

Page 28: ...finitions The CPU reset push button switch CPU_RESETn S2 is a dedicated reset switch for the embedded processors which is wired to the FPGA DEV_CLRn pin while the MAX II reset push button switch MAX_R...

Page 29: ...0 1 8 V 66 6 MHz HSMB_CLKIN_P 1 N 1 LVDS HSMB_CLKIN_P 2 N 2 LVDS EP3CLS70F780 Migratable to ENET_RX_CLK HSMB_CLKIN_P 1 N 1 2 5 V LVDS 2 5 V 50 MHz 100 MHz CLK_SEL CLKIN_RIGHT_P N CLKIN_LEFT_P N LVDS L...

Page 30: ...HSMB_CLKIN_P2 T2 LVTTL LVTTL input from the installed HSMC port B cable or board Can also support LVDS inputs when the termination resistor is installed HSMB_CLKIN_N2 T1 Note to Table 2 20 1 CDCM6100...

Page 31: ...ch is an input to the Cyclone III LS device and the MAX II CPLD EPM2210 System Controller CPU_RESETn is intended to be the master reset signal for the FPGA design loaded into the Cyclone III LS device...

Page 32: ...ce Pin Number S6 User defined push button switch When the switch is pressed a logic 0 is selected When the switch is released a logic 1 is selected USER_PB0 1 8 V F24 S5 USER_PB1 G17 S4 USER_PB2 E25 S...

Page 33: ...onents under the display You can also use the header for debugging or other purposes The LCD signals are multiplexed with HSMC port B data signals HSMB_D65 through HSMB_D75 The LCD HSMC port B data se...

Page 34: ..._HSMB_SEL is set to a logic 0 LCD_HSMB_D 68 AE1 J19 12 LCD data bus bit 5 LCD_DATA5 when LCD_HSMB_SEL is set to a logic 0 LCD_HSMB_D 69 AF1 J19 13 LCD data bus bit 6 LCD_DATA6 when LCD_HSMB_SEL is set...

Page 35: ...nterface to the FPGA The MAC function must be provided in the FPGA for typical networking applications The Marvell 88E1111 PHY uses 2 5 V and 1 2 V power rails and requires a 25 MHz reference clock dr...

Page 36: ...GMII transmit clock ENET_GTX_CLK 2 5 V AC14 U24 23 Management bus interrupt ENET_INTn N23 U24 25 Management bus control ENET_MDC AH12 U24 24 Management bus data ENET_MDIO AH27 U24 28 Device reset ENET...

Page 37: ...etween the two rows of signal and power pins acting both as a shield and a reference The HSMC host connector is based on the 0 5 mm pitch QSH QTH family of high speed board to board connectors from Sa...

Page 38: ...or 2 5 V AA23 J2 48 LVDS RX bit 0 or CMOS bit 5 HSMA_RX_P0 K24 J2 49 LVDS TX bit 0n or CMOS bit 6 HSMA_TX_N0 AA24 J2 50 LVDS RX bit 0n or CMOS bit 7 HSMA_RX_N0 J24 J2 53 LVDS TX bit 1 or CMOS bit 8 HS...

Page 39: ...it 9 or CMOS bit 45 HSMA_RX_P9 J27 J2 109 LVDS TX bit 9n or CMOS bit 46 HSMA_TX_N9 Y26 J2 110 LVDS RX bit 9n or CMOS bit 47 HSMA_RX_N9 J28 J2 113 LVDS TX bit 10 or CMOS bit 48 HSMA_TX_P10 AA27 J2 114...

Page 40: ...t 74 HSMA_TX_N16 AD27 J2 152 LVDS RX bit 16n or CMOS bit 75 HSMA_RX_N16 K23 J2 155 LVDS or CMOS clock out 2 or CMOS bit 76 HSMA_CLKOUT_P2 M25 J2 156 LVDS or CMOS clock in 2 or CMOS bit 77 HSMA_CLKIN_P...

Page 41: ...ed CMOS I O bit 20 HSMB_D20 H1 J1 72 Dedicated CMOS I O bit 21 HSMB_D21 K2 J1 73 Dedicated CMOS I O bit 22 HSMB_D22 G6 J1 74 Dedicated CMOS I O bit 23 HSMB_D23 J3 J1 77 Dedicated CMOS I O bit 24 HSMB_...

Page 42: ...58 HSMB_D58 Y6 J1 128 Dedicated CMOS I O bit 59 HSMB_D59 AA5 J1 131 Dedicated CMOS I O bit 60 HSMB_D60 W1 J1 132 Dedicated CMOS I O bit 61 HSMB_D61 Y3 J1 133 Dedicated CMOS I O bit 62 HSMB_D62 W2 J1...

Page 43: ...to a logic 1 LCD_HSMB_D74 W6 U27 9 Dedicated CMOS I O bit 75 when LCD_HSMB_SEL is set to a logic 1 LCD_HSMB_D75 W7 J1 155 LVDS or CMOS clock out 2 or CMOS bit 76 HSMB_CLKOUT_P2 T6 J1 156 LVDS or CMOS...

Page 44: ...ank 7 Pin Assignments Signal Names and Functions Part 1 of 2 Board Reference Description Schematic Signal Name I O Standard Cyclone III LS Device Pin Number U6 M8 Address bus DDR2_B7_A0 1 8 V SSTL Cla...

Page 45: ...ne 1 DDR2_DQ10 D23 U6 D3 Data bus byte lane 1 DDR2_DQ11 D22 U6 D1 Data bus byte lane 1 DDR2_DQ12 F21 U6 D9 Data bus byte lane 1 DDR2_DQ13 A25 U6 B1 Data bus byte lane 1 DDR2_DQ14 E21 U6 B9 Data bus by...

Page 46: ...DR2_DM2 1 8 V SSTL Class I D8 U5 B3 Write mask byte lane 3 DDR2_DM3 A9 U5 G8 Data bus byte lane 2 DDR2_DQ16 B11 U5 G2 Data bus byte lane 2 DDR2_DQ17 C12 U5 H7 Data bus byte lane 2 DDR2_DQ18 G10 U5 H3...

Page 47: ...device in terms of I O setting and direction Table 2 39 DDR2 Component References and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Website...

Page 48: ...a bus FSM_D13 AE18 U14 G10 Data bus FSM_D14 AD6 U14 G11 Data bus FSM_D15 AG20 U14 D1 Data bus FSM_D16 AH20 U14 D2 Data bus FSM_D17 AH18 U14 E1 Data bus FSM_D18 AF8 U14 E2 Data bus FSM_D19 AE20 U14 F1...

Page 49: ...block and 1200 ms for a 128 K main block U14 A7 Byte write enable SRAM_BWEn 2 5 V AH8 U14 B5 Byte lane 0 write enable SRAM_BWn0 AC12 U14 A5 Byte lane 1 write enable SRAM_BWn1 AH11 U14 A4 Byte lane 2...

Page 50: ...rite enable FLASH_WEn AH17 U9 C6 Address valid FLASH_WPn U9 A1 Address bus FSM_A1 AD14 U9 B1 Address bus FSM_A2 AA17 U9 C1 Address bus FSM_A3 AE12 U9 D1 Address bus FSM_A4 AF21 U9 D2 Address bus FSM_A...

Page 51: ...E1 Data bus FSM_D8 AE23 U9 E3 Data bus FSM_D9 AF15 U9 F3 Data bus FSM_D10 AD17 U9 F4 Data bus FSM_D11 AF20 U9 F5 Data bus FSM_D12 AH25 U9 H5 Data bus FSM_D13 AE18 U9 G7 Data bus FSM_D14 AD6 U9 E7 Dat...

Page 52: ...An on board multi channel analog to digital converter ADC is used to measure both the voltage and current for several specific board rails The power utilization is displayed using a GUI that can grap...

Page 53: ...lators 1 8V DDR2 Devices Flash VDD Oscillator 0 9VTT 0 9VREF DDR2 ADDR CMD Term Ref VCCIO_B7 C3LS200 Bank 7 1 8 V 0 300 A C3LS_VCCINT C3LS200 VCCINT 1 2 V 5 878 A VCCD_PLL C3LS200 VCCD_PLL 1 2 V 0 100...

Page 54: ...S D 0 7 Table 2 46 Power Rails Measurement Based on the Rail Selected in the Power GUI Switch Schematic Signal Name Voltage V Device Pin Description 1 VCCIO_B1B2 2 5 VCCIO1 FPGA I O power bank 1 HSMB...

Page 55: ...inated biphenyls PBB Polybrominated diphenyl Ethers PBDE Cyclone III LS FPGA development board X 0 0 0 0 0 16 V power supply 0 0 0 0 0 0 Type A B USB cable 0 0 0 0 0 0 User guide 0 0 0 0 0 0 Notes to...

Page 56: ...2 48 Chapter 2 Board Components Statement of China RoHS Compliance Cyclone III LS FPGA Development Board Reference Manual October 2009 Altera Corporation...

Page 57: ...ing table Date and Document Version Changes Made Summary of Changes October 2009 v1 0 Initial release Contact Note 1 Contact Method Address Technical support Website www altera com support Technical t...

Page 58: ...te references to sections in a document and titles of Quartus II Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example d...

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