Altera Cyclone II Reference Manual Download

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2–32

Reference Manual

Altera Corporation

Cyclone II FPGA Starter Development Board

October 2006

Development Board Components

Figure 2–24. SD Card Interface Schematic

Table 2–15

lists the SD Card signal connections to FPGA pins.

RS-232 Serial Port

The development board uses a MAX232 transceiver chip and a 9-pin
D-SUB connector (

Figure 2–25

) for RS-232 communications.

For detailed information on how to use the transceiver, refer to the

BoardDesignFiles\Datasheet

folder in the kit installation directory

connect to the manufacturer’s web site.

Table 2–15. SD Card FPGA Connections

Signal Name

FPGA Pin

Description

SD_DAT

W20

Data to/from SD Card

SD_DAT3

U20

SD Card Chip Select

SD_CMD

Y20

Command line for SD Card

SD_CLK

V20

SD Card Clock

Summary of Contents for Cyclone II

Page 1: ...101 Innovation Drive San Jose CA 95134 408 544 7000 http www altera com Document Version 1 0 Document Date October 2006 Cyclone II FPGA Starter Development Board Reference Manual...

Page 2: ...ding applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the righ...

Page 3: ...ponent Features 1 7 Cyclone II EP2C20 FPGA 1 7 Serial Configuration Device and USB Blaster Circuit 1 8 SRAM 1 8 SDRAM 1 8 Flash Memory 1 8 SD Card Socket 1 8 Push Button Switches 1 8 Toggle Switches 1...

Page 4: ...Toggle Switch Schematic 2 18 Toggle Switch Pin List 2 19 Displays 2 19 LEDs 2 19 LED Schematic 2 19 LED Pin List 2 21 Seven Segment Displays 2 21 Seven Segment Display Schematic 2 22 Seven Segment Di...

Page 5: ...tion in this Portable Document Format PDF type document Search the contents by using the Adobe Acrobat or Reader Edit Find command or click on the binoculars Search toolbar icon The Bookmarks window s...

Page 6: ...ime FTP site ftp altera com ftp altera com Visual Cue Meaning Bold Type with Initial Capital Letters Command names dialog box titles checkbox options and dialog box options are shown in bold initial c...

Page 7: ...umbered steps are used in a list of items when the sequence of the items is important such as the steps listed in a procedure Bullets are used in a list of items when the sequence of the items is not...

Page 8: ...viii Reference Manual Altera Corporation Cyclone II FPGA Starter Development Board October 2006 About This Manual...

Page 9: ...from simple circuits to various multimedia projects all without the need to implement complex application programming interfaces APIs host control software or SRAM SDRAM flash memory controllers Figu...

Page 10: ...r protection 7 5V DC adapter or a USB cable provided in the kit for power Software Features Flexible control of the development board and Altera hardware and software tools provide an effective FPGA b...

Page 11: ...o the FPGA each time power is applied to the board Using the Quartus II software it is possible to reprogram the FPGA at any time and it is also possible to change the non volatile data stored in the...

Page 12: ...A Configuration Procedure For both the JTAG and AS programming methods the Cyclone II FPGA Starter board connects to a host computer via a USB cable Because of this connection type the host computer i...

Page 13: ...the RUN PROG switch on the left side of the board to the PROG position 4 To program the EPCS4 device use the Quartus II Programmer module to select a configuration bit stream file with the pof filenam...

Page 14: ...r Interface KEY0 KEY3 Push button switches Four momentary contact switches for user input to the FPGA SW0 SW9 Toggle switches Ten toggle switches for configuration of the FPGA LEDG0 LEDG7 Individual L...

Page 15: ...FPGA with resistor voltage protection MIC Microphone input Audio CODEC connectors LINEIN Audio Line input LINEOUT Audio line output VGA VGA connector VGA video port SD CARD SD card socket Secure Data...

Page 16: ...e Control Panel GUI SDRAM 8 MByte single data rate synchronous dynamic RAM memory chip Organized as 1M x 16 bits x 4 banks Accessible as memory for the Nios II processor and by the Control Panel GUI F...

Page 17: ...lications for MP3 players and recorders PDAs smart phones voice recorders VGA Output Uses a 4 bit resistor network DAC 15 pin high density D sub connector Supports up to 640x480 at 60 Hz refresh rate...

Page 18: ...1 10 Reference Manual Altera Corporation Cyclone II FPGA Starter Development Board October 2006 Introduction...

Page 19: ...switch 4 momentary push button switches 10 sliding toggle switches Displays LEDs 8 green 10 red 4 seven segment displays Connectors USB Blaster port Two 40 pin expansion headers SD card connector RS 2...

Page 20: ...CS4 device automatically loads stored configuration data into the FPGA each time power is applied to the board Quartus II software on a host computer connected to the board across a USB Blaster cable...

Page 21: ...the RGB data inputs on the monitor must be off driven to 0 volts for a backporch time period b Figure 2 1 VGA Horizontal Timing The display interval starts after the backporch time period b expires Fo...

Page 22: ...Specifications Configuration Resolution HxV a lines b lines c lines d lines VGA 60 Hz 640 x 480 2 33 480 10 Table 2 4 VGA Circuit FPGA Pin Connections Signal Name FPGA Pin Description VGA_R 0 PIN_D9...

Page 23: ...nt Board Development Board Components Figure 2 2 VGA Circuit Schematic Diagram Audio CODEC The development board provides a Wolfson WM8731high quality 24 bit sigma delta audio encoder decoder CODEC fo...

Page 24: ...a sample rate adjustable from 8 kHz to 96 kHz A serial I2C bus interface connected to FPGA pins controls the WM8731 CODEC f For information about the WM8731 CODEC refer to the BoardDesignFiles Datash...

Page 25: ...memory devices refer to the BoardDesignFiles Datasheet folder in the kit installation directory SDRAM Schematic and Pin List Figure 2 4 shows the SDRAM interface signals Table 2 5 Audio Circuit FPGA...

Page 26: ...e 2 6 lists the FPGA pins assigned to the SDRAM Table 2 6 SDRAM FPGA Pin Connections Part 1 of 2 Signal Name FPGA Pin Description DRAM_ADDR 0 PIN_W4 SDRAM Address 0 DRAM_ADDR 1 PIN_W5 SDRAM Address 1...

Page 27: ...IN_Y1 SDRAM Data 6 DRAM_DQ 7 PIN_Y2 SDRAM Data 7 DRAM_DQ 8 PIN_N1 SDRAM Data 8 DRAM_DQ 9 PIN_N2 SDRAM Data 9 DRAM_DQ 10 PIN_P1 SDRAM Data 10 DRAM_DQ 11 PIN_P2 SDRAM Data 11 DRAM_DQ 12 PIN_R1 SDRAM Dat...

Page 28: ...2 7 SRAM FPGA Pin Connections Part 1 of 2 Signal Name FPGA Pin Description SRAM_ADDR 0 PIN_AA3 SRAM Address 0 SRAM_ADDR 1 PIN_AB3 SRAM Address 1 SRAM_ADDR 2 PIN_AA4 SRAM Address 2 SRAM_ADDR 3 PIN_AB4...

Page 29: ...0 SRAM_DQ 1 PIN_AB6 SRAM Data 1 SRAM_DQ 2 PIN_AA7 SRAM Data 2 SRAM_DQ 3 PIN_AB7 SRAM Data 3 SRAM_DQ 4 PIN_AA8 SRAM Data 4 SRAM_DQ 5 PIN_AB8 SRAM Data 5 SRAM_DQ 6 PIN_AA9 SRAM Data 6 SRAM_DQ 7 PIN_AB9...

Page 30: ...FL_ADDR 0 PIN_AB20 FLASH Address 0 FL_ADDR 1 PIN_AA14 FLASH Address 1 FL_ADDR 2 PIN_Y16 FLASH Address 2 FL_ADDR 3 PIN_R15 FLASH Address 3 FL_ADDR 4 PIN_T15 FLASH Address 4 FL_ADDR 5 PIN_U15 FLASH Add...

Page 31: ...IN_AA12 FLASH Address 15 FL_ADDR 16 PIN_AB12 FLASH Address 16 FL_ADDR 17 PIN_AA20 FLASH Address 17 FL_ADDR 18 PIN_U14 FLASH Address 18 FL_ADDR 19 PIN_V14 FLASH Address 19 FL_ADDR 20 PIN_U13 FLASH Addr...

Page 32: ...ssigned to the display segments Switches The development board provides the following user switches Power ON OFF switch RUN PROG switch 4 push button switches 10 Toggle switches Table 2 9 Clock Circui...

Page 33: ...signals from the USB Blaster circuit to the FPGA directly when in the RUN position Figure 2 8 or to the EPCS4 Serial EEPROM configuration device when in the PROG position Figure 2 9 Figure 2 8 RUN PRO...

Page 34: ...PCS4 device Push Button Switches The development board provides four push button switches KEY0 KEY3 located at the bottom right on the development board below the green LEDs LEDG0 LEDG7 Figure 2 10 Th...

Page 35: ...e 2 12 shows a schematic diagram of the push button switches Figure 2 12 Push Button Switch Schematic Diagram Push Button Switch Pin List Table 2 10 lists the FPGA pins assigned to the push button swi...

Page 36: ...he DOWN or OFF position closest to the edge of the board a switch provides a LOW logic level 0 volts to the FPGA In the UP position a switch provides a HIGH logic level 3 3 volts Figure 2 13 Toggle Sw...

Page 37: ...Ds LEDG0 LEDG7 above the four push button switches Figure 2 10 Each LED connects directly to an FPGA general purpose I O pin A HIGH logic level on a pin turns the LED on a LOW logic level on a pin tur...

Page 38: ...2 20 Reference Manual Altera Corporation Cyclone II FPGA Starter Development Board October 2006 Development Board Components Figure 2 15 LED Schematic Diagram...

Page 39: ...applied at the pin lights up the segment a HIGH logic level turns the segment off Table 2 12 LED FPGA Pin Connections Signal Name FPGA Pin Description LEDR 0 PIN_R20 LED Red 0 LEDR 1 PIN_R19 LED Red...

Page 40: ...d Components Figure 2 16 Seven Segment Displays An index from 0 to 6 identifies each segment and its position Figure 2 17 The development board does not connect or use the dot in the display Figure 2...

Page 41: ...gments Table 2 13 Seven Segment Display FPGA Pin Connections Part 1 of 2 Signal Name FPGA Pin Description HEX0 0 PIN_J2 Seven Segment segment 0 0 HEX0 1 PIN_J1 Seven Segment segment 0 1 HEX0 2 PIN_H2...

Page 42: ...Seven Segment segment 1 5 HEX1 6 PIN_D1 Seven Segment segment 1 6 HEX2 0 PIN_G5 Seven Segment segment 2 0 HEX2 1 PIN_G6 Seven Segment segment 2 1 HEX2 2 PIN_C2 Seven Segment segment 2 2 HEX2 3 PIN_C1...

Page 43: ...ntroller on page 2 2 for more information about the USB Blaster circuitry Figure 2 19 USB Type B Connector Expansion Headers The development board provides two 40 pin expansion headers JP2 located on...

Page 44: ...ual Altera Corporation Cyclone II FPGA Starter Development Board October 2006 Development Board Components Figure 2 20 Expansion Headers Expansion Header Schematics Figure 2 21 shows the JP1 expansion...

Page 45: ...tion Reference Manual 2 27 October 2006 Cyclone II FPGA Starter Development Board Development Board Components Figure 2 21 Expansion Header JP1 Schematic Diagram Figure 2 22 shows the JP2 expansion he...

Page 46: ...pins include this circuitry For complete information refer to the schematic found in BoardDesignFiles Schematic in the kit installation directory Expansion Header Pin List Table 2 14 lists the FPGA pi...

Page 47: ...0 18 PIN_D21 GPIO Connection 0 18 GPIO_0 19 PIN_D22 GPIO Connection 0 19 GPIO_0 20 PIN_E21 GPIO Connection 0 20 GPIO_0 21 PIN_E22 GPIO Connection 0 21 GPIO_0 22 PIN_F21 GPIO Connection 0 22 GPIO_0 23...

Page 48: ...PIN_C19 GPIO Connection 1 16 GPIO_1 17 PIN_C20 GPIO Connection 1 17 GPIO_1 18 PIN_D19 GPIO Connection 1 18 GPIO_1 19 PIN_D20 GPIO Connection 1 19 GPIO_1 20 PIN_E20 GPIO Connection 1 20 GPIO_1 21 PIN_...

Page 49: ...nt Board Development Board Components SD Card Connector The Cyclone II FPGA Starter board includes an SD Card connector U8 Figure 2 23 to interface with SD Card devices including flash storage Figure...

Page 50: ...es a MAX232 transceiver chip and a 9 pin D SUB connector Figure 2 25 for RS 232 communications f For detailed information on how to use the transceiver refer to the BoardDesignFiles Datasheet folder i...

Page 51: ...er 2006 Cyclone II FPGA Starter Development Board Development Board Components Figure 2 25 RS 232 Serial Connector RS 232 Circuit Schematic Figure 2 26 shows the RS 232 serial circuit schematic Figure...

Page 52: ...ard or mouse PS 2 Circuit Schematic Figure 2 27 shows the PS 2 serial circuit schematic Figure 2 27 PS 2 Serial Circuit Schematic Diagram PS 2 Serial Circuit Pin List Table 2 17 lists the FPGA pins as...

Page 53: ...video DAC The connector is a standard DB15 15 pin analog VGA connector Refer to VGA DAC on page 2 2 for a description of the circuitry attached to this connector Figure 2 28 VGA Connector Audio Ports...

Page 54: ...different clock frequencies into the FPGA The input is a standard SMA coaxial cable connector J5 Refer to Clock Circuit on page 2 13 for a description of the circuitry attached to this connector Figu...

Page 55: ...Altera Corporation Reference Manual 2 37 October 2006 Cyclone II FPGA Starter Development Board Development Board Components Figure 2 31 Power Supply Connector...

Page 56: ...2 38 Reference Manual Altera Corporation Cyclone II FPGA Starter Development Board October 2006 Development Board Components...

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