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Altera Classic, Data Book

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Summary of Contents for Classic

Page 1: ...Data Book ...

Page 2: ......

Page 3: ...September 1991 ...

Page 4: ...d SPARCstation are trademarks of Sun Microsystems Incorporated UNIX is a trademark c AT T Bell Laboratories Apollo and Domain are registered trademarks and Series 3000 Series 3500 Series400 and Series 4500 are trademarks of Apollo Computer Incorporated a subsidiary of Hewlett Packard Compan HP is a registered trademark of Hewlett Packard Company PAL and PALASM are registered trademarks e Advanced ...

Page 5: ...Channel Adapter Handbook For immediate assistance on technical questions call Altera Applications Hotline 1 800 800 EPLD For information on product availability pricing and order status please contact your Altera Representative or Distributor Phone numbers and addresses of Altera Sales Offices Representatives and Distributors are listed in this data book Ifyou have questions that cannotbe answered...

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Page 7: ...ts Classic EPLDs 35 Describes all Classic EPLDs including the EP330 EP610 EP610A EP610T EP630 EP910 EP910A EP910T EP1810 EP1810T and EP1830 EPLDs MAX 5000 EPLDs 121 Describes all MAX 5000 EPLDs including the EPM5016 EPM5032 EPM5064 EPM5128 EPM5130 and EPM5192 EPLDs MAX 7000 EPLDs 177 Provides preliminary information about the MAX 7000 EPLDs STG SAM EPLDs 187 Describes the EPS464 Synchronous Timing...

Page 8: ...pollo and Sunworkstations device programming unit adapters and software warranty This section also includes a description of third party support Military Products 371 Describes the military products offered by Altera including the Source Control Drawings SCDs for military qualified EPLDs This section also contains information about total dose radiation hardness of Altera EPLDs General Information ...

Page 9: ...LD 107 EP1810T EPLD 113 EP1830 EPLD 117 Classic Military EPLDs 21 MAX 5000 EPLDs EPM5016 EPLD 137 EPM5032 EPLD 143 EPM5064 EPLD 149 EPM5128 EPLD 155 EPM5130 EPLD 161 EPM5192 EPLD 169 MAX 5000 Military EPLDs 22 MAX 7000 EPLDs MAX 7000 EPLDs 179 STG SAM EPLDs EPS464 EPLD 191 EPS448 EPLD 205 Micro Channel EPLDs EPB2001 EPLD 225 EPB2002A EPLD 225 I Altera Corporation Page vii I ...

Page 10: ...ws 3 0 PLDS HPS 26 269 PLS ES 26 269 PLS HPS 26 269 PLS OS 26 269 PC DOS PLCAD SUPREME 28 299 PLDS ENCORE 24 315 PLDS MAX 27 283 PLDS MCMAP 28 225 PLDS SAM 28 307 PLS EDIF 24 319 PLS MAX 27 283 PLS MCKIT 29 PLS SAM 28 307 PLS SUPREME 28 299 Workstation PLS WS HP 26 331 PLS WS SN 27 341 Hardware PL ASAP 32 357 PL MPU 33 359 389 PLP6 389 Programming Adapters 33 361 390 Altera Corporation I ...

Page 11: ...Contents ISeptember 1991 Section 1 Introduction to Altera EPLDs Programmable Logic Overview 3 Product Selection Guide 17 i Altera Corporation Page 11 ...

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Page 13: ...ry products to create sophisticated EPLDs that solve many logic design problems Altera provides the broadest line of CMOS EPLDs in the industry with products ranging in density from 300 to 40 000 maximum gates offered in a variety of packages with 20 to 288 pins These EPLDs together with Altera developmentsoftware enable systemmanufacturersto create custom logic functions for a wide variety of app...

Page 14: ...ons to logic integration that include both PAL speed and FPGA density See Figure 2 Figure 2 PLD Speed vs Density 100 N I 2 z 0 Q 50 Q 0 en Q c as en 100 10 000 Usable Density 20 000 AItera offers several families of EPLDs that satisfy many common board and system integration needs EPLD families are divided into two architectural categories the first provides maximum flexibility for general purpose...

Page 15: ...l bus interface The EPS464 Synchronous Timing Generator SIG and EPS448 Stand Alone Microsequencer SAM EPLDs offer the logic and speed required for complex control logic state machines and imaging and display applications o Mask Programmed Logic Devices MPLDs provide a low costmasked alternative to EPLDs for customers with high volume production A variety of package options is offered including dua...

Page 16: ...list and microcoded assembly language See Figure 4 Design entry methods can be freely combined to create a single EPLD design Design compilers perform minimization and logic synthesis design fitting analogous to automatic place and route and generate programming data Design verification via functional simulation timing simulation and delay prediction for speed critical paths is also available Hard...

Page 17: ...mum flexibility for integrating random logic functions Each EPLD also contains an AND array that provides product terms A product term is simply an n input AND gate where n is the number of connections EPLD schematics use a shorthand AND array notation to represent several large AND gates with common inputs Figure 5 shows three different representations of the same logic function Circuit A is pres...

Page 18: ...bidirectional pin I Register Options r DF D Q CLRN K I CLRN TFF PRN T Q CLRN PRN S Q R CLRN 1 0 Control OUTPUT f l L J I 1 ______ Logic Array IPage8 The logic array consists of a programmable AND fixed oR array Inputs to the AND array come from the true and complement of the dedicated input and clock pins and from the macrocell and 110 feedback paths For each macrocell the logic array typically co...

Page 19: ... 8 shows an OR function that requires six product terms in its current form By using the programmable XOR gate and De Morgan s inversion the OR function can be transformed into a NAND function A B C D E F A B C D E F This inversion from OR to AND translates the equation and reduces the number of fixed OR terms required in the logic array Altera software automatically applies De Morgan s inversion ...

Page 20: ...ps can be configured for either positive or negative edge triggered operation In addition product term clocks allow gated clock and clock enable logic to be implemented However global clock signals have faster clock to output delay times than internally generated product term clock signals The EPLD 110 block contains a tri state buffer controlled by a macrocell product term and drives the I O pin ...

Page 21: ...dditional 30 to 40 delay to the EPLD input output path Consequently a programmable Turbo Bit is provided to disable the input transition detection circuitry and permanently enable the logic array giving the user a choice of either extra speed or lower power consumption The EPLD also exhibits better system noise rejection characteristics in the turbo mode which should be used where noisy environmen...

Page 22: ...ric field and energize electrons to jump from the drain region to the floating gate Electrons are attracted to the floating gate and become trapped when the voltage is removed If the gate remains at a low voltage during programming electrons arenotattracted and the floating gate remains uncharged Trapped charge changes the threshold of the EPROM cell from a relatively low value with no charge pres...

Page 23: ...ipment Foremost among these tests are cell margin tests which guarantee the in service retention of EPROM bit programming Cell margintesting determines the amount ofcharge trapped on the floating gate structure Charge loss occurs when electrons leak from the floating gate structure over time and results in a net reduction in programmed cell threshold Charge gain results from an accumulation of cha...

Page 24: ...ogramming process to ensure EPLD design security Parasitic bipolar transistors are present in the fundamental structure of CMOS devices Typically the base emitter and base collector junctions of these transistors are not forward biased so the transistors are not turned on Figure 13 shows a cross section ofa CMOS wafer and primary parasitic transistors Byconnecting the P type substrate to the most ...

Page 25: ... 3 Inputs When removing power from the EPLD the order should be reversed first inputs are removed or taken low then Vee is removed or lowered Simultaneous application of inputs and Vee to the device which might occur as a power supply ramps during power up should be safe Care should be taken to ensure that inputs cannot rise faster than supply under extreme conditions Figure 14 Hot Socket Protecti...

Page 26: ...rge switching currents can flow through power supply and output pins during high performance operation If a 50 pF capacitor is charged from 0 to 5 V in 10 ns a dynamic current of 24 mA will flow If 24 outputs on an EPLD switch simultaneously for example in an EP910 the total transient current can exceed 600 rnA This current can severely degrade Vee supply voltage due to the inductive properties of...

Page 27: ...ltera o General purpose EPLDs o Function specific EPLDs o Military qualified EPLDs o Programmable logic development systems o Programmable logic software o Software warranty o Programming hardware adapters For detailed descriptions of the Altera products listed here refer to the individual data sheets in this data book and to the Micro Channel Adapter Handbook Page 17 ...

Page 28: ...24 28 EP610T P L S C 15 15 83 3 90 90 16 4 16 24 28 EP610T P L S C 20 20 62 5 90 90 16 4 16 24 28 EP610T P L S C 25 25 47 6 90 90 16 4 16 24 28 EP630 P L S C 15 15 83 3 90 0 15 16 4 16 24 28 EP630 P L S C 20 20 62 5 90 0 15 16 4 16 24 28 EP910 D P J L C 30 30 41 7 80 0 15 24 12 24 40 44 EP910 D P J L C I 35 35 37 0 80 0 15 24 12 24 40 44 EP910 D P J L C I M 40 40 32 3 80 0 15 24 12 24 40 44 EP910A...

Page 29: ... D P J L S C 17 17 83 3 155 150 32 8 16 28 EPM5032 D P J L S C I 20 20 71 4 155 150 32 8 16 28 EPM5032 D P J L S C I M 25 25 62 5 155 150 32 8 16 28 EPM5064 J L C 1 25 62 5 135 125 64 8 28 44 EPM5064 J L C I 2 30 50 0 135 125 64 8 28 44 EPM5064 J L C I M 35 40 0 135 125 64 8 28 44 EPM5128 J L G C 1 25 62 5 250 225 128 8 52 68 EPM5128 J L G C I 2 30 50 0 250 225 128 8 52 68 EPM5128 J L G C I M 35 4...

Page 30: ... ICC1 Macrocells Dedicated 1 0 Number 1 2 3 Grade ns MHz rnA rnA Registers Inputs of Pins Active Standby EPS464 J L Q C 20 20 71 4 125 120 64 4 32 44 EPS464 J L Q C 25 25 50 0 125 120 64 4 32 44 Table 4 SAM EPLDs EPLD Pkg Temp Speed f MAX ICC3 ICC1 Microcode Branch Stack Dedicated 1 0 Number 2 3 Grade MHz rnA rnA EPROM EPLD Inputs of Pins Active Standby EPS448 D P J L C 30 30 140 95 448 x 36 768 p...

Page 31: ... Qualified Classic EPLDs EPLD Pkg Assurance t P01 fMAX ICC3 ICC1 Macrocells Dedicated I O Number Altera 1 2 Level 3 ns MHz rnA rnA Registers Inputs of Pins Military Active Standby Drawing 4 EP310 0 8838 50 31 3 40 0 9 8 10 8 20 020 00179 8863501RA 0 OESC 50 31 3 40 0 9 8 10 8 20 EP320 0 8838 45 30 3 40 8 10 8 20 020 00209 EP600 0 8838 55 22 2 60 16 4 16 24 020 00194 EP600 J 8838X 55 22 2 60 16 4 1...

Page 32: ...re rated to military temperatures 55 C to 125 C Preliminary data is shown for some other parameters Consult individual device data sheets for complete information 2 Package configurations D Windowed ceramic dual in line package CerDIP J Windowed ceramic lead chip carrier GLCC G Windowed ceramic pin grid array PGA 3 Product assurance levels 883B Processed to MIL STD 883 current revision 883BX Proce...

Page 33: ...I design software allows the designer to quickly and efficiently enter compile and verify designs with 20 000 or more gates right on a standard PC HP Apollo workstation or Sun workstation When the design is complete itcan be programmed into one or more high performance Altera EPLDs and tested in system Table 8 shows the software and hardware development products available from Altera Programmable ...

Page 34: ...OS PLS ES PLS WS HP PLS WS SN MAX PLUS PLDS MAX PLS MAX A PLUS PLCAD SUPREME t PLS SUPREME t SAM PLUS PLDS SAM PLS SAM MCMap PLDS MCMAP PLS MCKIT MAX PLUS A PLUS SAM PLUS Design Entry PLDS ENCORE t t t t t EDIF Interface PLS EDIF IPage24 Data Sheet I Design Compilation Verification Altera Corporation I ...

Page 35: ... HPS t t t t PLS HPS t t t t PLS OS t t t t PLS ES 1 t PLS WS HP t t t t PLS WS SN t t t t MAX PLUS PLDS MAX t PLS MAX t A PLUS PLCAD SUPREME t PLS SUPREME t SAM PLUS PLDS SAM t PLS SAM t MCMap PLDS MCMAP t PLS MCKIT t MAX PLUS A PLUS SAM PLUS PLDS ENCORE I t t t EDIF Interface PLS EDIF t Note 1 PLS ES supports the single LAB EPM5016 and EPM5032 MAX 5000 EPLDs IAltera Corporation Page2s1 ...

Page 36: ...er Programming Unit MPU a bidirectional EDIF interface programming adapters and sample EPLDs PLDS HPS supports Altera s MAX 7000 MAX 5000 Classic and Synchronous Timing Generator STG EPLDs PLS HPS High Performance System that provides the complete MAX PLUS II software This software onlyversion ofPLDS HPS includes graphic waveform and text design entry with AHDL automated compilation design partiti...

Page 37: ...d macros full timing simulation delay prediction for speed critical paths timing analysis and a design archiver MAX PLUS is available in two configurations PLDS MAX Fully integrated programmable logic development system for working with MAX 5000 EPLDs It includes MAX PLUS design entry processing verification and programming software standard Altera programming hardware an assortment of programming...

Page 38: ...es SAMSIM an interactive functional simulator created specifically for verifying SAM designs SAM PLUS is available in two configurations PLDS SAM Programmable logic development system for working with SAM EPLDs It includes SAM PLUS and LogicMap II software standard Altera programming hardware one programming adapter and sample EPLDs PLS SAM Programmable logic development software for working with ...

Page 39: ...th MAX PLUS and MAX PLUS IT the designer can automatically generate symbols for custom functions which can be incorporated into other designs AHDL The Altera Hardware Description Language AHDL is a high level modular language used to createhierarchical logic designs AHDL supports state machines truth tables Booleanequations arithmetic operators group operations and macrofunctions With MAX PLUS IT ...

Page 40: ...that check designs for errors synthesize logic fit designs into EPLDs and test design logic Major features of design compilation and verification are o Timing Simulation o Functional Simulation o Timing Analysis o Waveform Editing o Design Partitioning o Multi EPLD Simulation Timing Simulation A timing simulator tests the logical operation and internal timing ofa logic design It allows a designer ...

Page 41: ...nd device assignments to optimize design placement on the EPLD Multi EPLD Simulation Multi EPLD simulation allows logic designs that are partitioned into multiple devices to be simulated together To satisfy the needs of workstation based designers Altera provides an interface to third party CAE tools from Mentor Graphics Valid Logic Viewlogic Synopsys and others EDIF interface software enables the...

Page 42: ... products provide software and documentation updates for all registered owners of Altera development systems The software warranty should be ordered with one of the following codes o o o o PLAESW HPS PLAESW MAX PLAESW SUP PLAESW WS for PLDS HPS PLS HPS PLS OS PLS ES for PLDS MAX PLS MAX for PLCAD SUPREME PLS SUPREME for PLS WS HP PLS WS SN Altera programming hardware can be purchased in the Altera...

Page 43: ...s the LP6 card interfaces with IBM AT or compatible computers MPU Serves as the base unit for programming all Altera EPLDs It can directly program EP320 and EP330 DIP EPLDs adapters are required to program all other EPLDs Adapters Table 10 shows the adapters available for Altera EPLDs Adapter names consist of the four letter prefix shown on the left plus the corresponding device number on the righ...

Page 44: ... sOle PLES5016 EPM5032 DIP PLED5032 DIP PLMD5032 2 J Iead PLEJ5032 sOle PLES5032 EPM5064 J Iead PLEJ5064 EPM5128 J Iead PLEJ5128 J Iead PLMJ5128 2 PGA PLEG5128 EPM5130 J Iead PLEJ5130 J Iead PLMJ5130 2 PGA PLEG5130 QFP PLEQ5130 EPM5192 J Iead PLEJ5192 J Iead PLMJ5192 2 PGA PLEG5192 EPS448 DIP PLED448 J Iead PLEJ448 EPS464 J Iead PLEJ464 J Iead PLMJ464 2 QFP PLEQ464 EPB2001 J Iead PLEJ2001 Notes to...

Page 45: ...l Device 39 EP610 EPLDs High Performance 16 Macrocell Devices 49 EP610 EPLD 59 EP610A EPLD 65 EP610T EPLD 69 EP630 EPLD 73 EP910 EPLDs High Performance 24 Macrocell Devices 77 EP910 EPLD 87 EP910A EPLD 91 EP910T EPLD 95 EP1810 EPLDs High Performance 48 Macrocell Devices 99 EP1810 EPLD 107 EP1810T EPLD 113 EP1830 EPLD 117 Altera Corporation Page3s1 ...

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Page 49: ...replacement for GAL 16V8 and most 20 pin PAL devices o Quiet outputs minimize output switching noise found in other high speed CMOS devices o Extensive third party software and programming support o MAX PLUS II and A PLUS software support includes schematic capture Boolean equation state machine and netlist design entry methods Altera Hardware Description Language AHDL waveform entry and an EDIF 2...

Page 50: ...machine truth table and netlist design entry methods MAX PLUS II also provides the Altera Hardware Description Language AHDL waveform design entry and an EOIF 2 0 0netlist interface After the design is entered the software automatically translates the input files into logic equations performs Boolean minimization and fits the design into the EPLO MAX PLUS IT automatically partitions larger designs...

Page 51: ...ion A An EP330 EPLD has ten dedicated data inputs and eight I O pins that can be configured for input output or bidirectional operation Figure 3 shows the EP330 macrocell Clock o 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 OE o If E 2 0 3 l e 4 a 5 6 7 3 5 SO 7 9 11 13 l 15 17 19 21 23 25 27 29 31 33 35 T 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 Altera Corporation r I 1 0 I O Architecture I...

Page 52: ...binatorial mode the output is not registered and the feedback signal comes directly from the I O pin The Output Enable OE product term determines whether an output signal will propagate to the output pin If the output of the OE product term is high output to the pin is enabled If the output is low the output buffer becomes a high impedance node and does not allow the output signal to reach the out...

Page 53: ... 7 E 0 1 2 3 4 5 6 7 E 0 1 2 3 4 5 6 7 E 0 1 2 3 4 5 6 7 E 0 1 2 3 4 5 6 7 o 1 2 3 4 5 6 7 8 9 10 11 121314151617 181920 21 22 23 24 25 26 2728 293031 32 33 34 35 Altera Corporation Clock r r_l t I I I t H r I i t I I I t H r I H I i t I I I r H r I H I i t I I I t H 1 ___H ___H ___H ___I P6 ___i t H H I O Architecture Control I O 19 19 I O Architecture Control I O 18 18 I O Architecture Control g...

Page 54: ...egister High D Register Low None Feedback D Register None D Register None D Register The switching waveforms for the EP330 EPLD are shown in Figure 6 Figure 6 EP330 Switching Waveforms tR and tF 2 ns Inputs are driven at 3 Vfor alogic high and 0 Vfor alogic low All timing characteristics are measured at 1 5 V Input or I O Combinatorial Output Combinatorial or Registered Output Valid Output Clock C...

Page 55: ...ultaneous transitions of multiple outputs should be avoided for accurate measurement Threshold tests must not be performed under AC conditions Large amplitude fast ground current transients normally occur as the device outputs discharge the load capacitances When these transients flow through the parasitic inductance between the device groundpin and the test system ground it can create significant...

Page 56: ...cial use 0 70 C TA Operating temperature For industrial use 40 85 C tR Input rise time See Note 2 20 ns tF Input fall time See Note 2 20 ns DC Operating Conditions See Notes 3 4 Symbol Parameter Conditions Min Typ Max Unit V IH High level input voltage 2 0 Vee 0 3 V V IL Low level input voltage 0 3 0 8 V VOH High level TTL output voltage 10H 12 mA DC 2 4 V VOL Low level output voltage 10L 24 mA DC...

Page 57: ...4 5 ns tC01 Clock to output delay 8 10 ns tCNT Minimum clock period 10 12 ns fCNT Internal maximum frequency See Note 5 100 83 3 MHz Votes to tables 1 Minimum DC input is 3 V During transitions inputs may undershoot to 2 0 V or overshoot to 7 0 V for periods less than 20 ns under no load conditions 2 For all clocks tR and tF 20 ns 3 Typical values are for TA 25 C and Vee 5 V 4 Operating conditions...

Page 58: ...C to 125 C Consult factory Figure 8 shows output drive characteristics for EP330 I O pins and typica1 supply current versus frequency for the EP330 EPLD Figure 8 EP330 Output Drive Characteristics and Icc vs Frequency 55 160 50 ci IOL 120 ci 5 c Vee 5 0 V 40 TA 25 C 5 s 80 Q 0 5 U Vee 5 0 V c 30 TA 25 C 5 0 9 40 9 5 10 KHz 1 MHz 100 MHz V0 Output Voltage V Maximum Frequency IPage 48 Altera Corpora...

Page 59: ...ltera s EP610 Erasable Programmable Logic Devices EPLDs can implement up to 600 equivalent gates of SSI and MSI logic functions in space saving windowed ceramic or one time programmable OTP plastic 24 pin 300 mil dual in line package CerDIP and PDIP and 28 pin J Iead JLCC and PLCC packages or OTP plastic 24 pin 300 mil small outline integrated circuit SOIC packages The EP610 EPLDs use sum of produ...

Page 60: ...n seconds at the designer s desktop to create customized working silicon In addition extensive third party support exists for designentry designprocessing and device programming The EP610 EPLD is pin function and JEDEC File compatible with the EP610A EP610T and EP630 EPLDs JEDEC Files generated for an EP610 EPLD can be used for programming these devices EP610 The EP610 EPLD combines high speed wit...

Page 61: ...10 product terms for the following functions 8product terms are dedicated to logic implementation 1 product term is used for Clear control of the internal register and 1 product term implements either Output Enable or an array Clock o 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 o a GI b I OE ClK Select OE ClK o 2 3 o 6 4 e c 5 6 7 CLEAR 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 ...

Page 62: ...ead packages 1 2 CLK1 C 2 3 INPUT C f Cc J 3 4 1 0 4 5 1 0 5 6 1 0 10 12 1 0 1 0 Architecture Control 11 13 INPUT C GC Page 52 Macrocell9 Macrocell10 Macrocell11 Macrocell16 40 40 Macrocell1 Macrocell2 Macrocell3 Macrocell8 Data Sheet I 1 022 26 1 021 25 1 020 24 1 015 18 INPUT14 17 CLK2 13 16 A tera Corporation ...

Page 63: ... over50 programmable I O configurations Each macrocell can be configured for combinatorial or registered output with programmable output polarity One offour register types D T JK and SR can be implemented in each macrocell without additional logic I O feedback selection can be programmed for registered or input feedback The I O architecture can also individually clock each internal register from a...

Page 64: ...enabled by the logic from the product term OE Array Product Term CLK Global Mode 1 AND Array Global Clock Data OE ClK Q Macrocell Output Buffer Macrocell I O Register The output is permanently enabledand the register is clocked by the product term which allows gated clocks to be generated in EP610 EPLDs OE Enabled CLK Array AND Array Global Clock Data OE ClK Macrocell Output Buffer Macrocell I O R...

Page 65: ...tate tpzx _______ Hi_9h_ I_m_pe_d_an_ce_T_ri_ S_ta_te___ ____________ tClR Global Clock Mode Input or 1 0 may change Input or 1 0 may change tc01 V r from register to output A Array Clock Mode tACH t ACl x lX X X _ X t AS U t AH 1 Valid Input Input or 1 0 may change Input or 1 0 may change Valid Output from register to output x Output configurations available with the EP610 EPLDs are shown in Figu...

Page 66: ...None None JK Flip Flop liD Selection OutputIPolarlty JK Register High JK Register Low None SR Flip Flop liD Selection OutputIPolarity SR Register High SR Register Low None Data Sheet I Feedback Pin None Pin None Pin Function Table Feedback 0 Qn Qn 1 o Register Pin None L L L o Register Pin None L H L o Register H L H Pin H H H Function Table Feedback T Q n Qn 1 T Register Pin None L L L T Register...

Page 67: ... of the OR gates feed the two primary register inputs This configuration has the following characteristics o The MAX PLUS II and A PLUS development systems optimize the allocation of product terms for each register input o One product term controls asynchronous Clear o The Invert Select EPROM bits control output polarity o The OE CLK Select multiplexer configures the mode of operation to Mode 0 or...

Page 68: ... programmed into the device If this feature is used a proprietary design implemented in the EPLD cannotbe copied or retrieved This feature provides a high levelofdesignsecurityby makingprogrammed data within EPROM cells invisible The Security Bit as well as all other program data is reset by erasing the EPLD EP610 EPLDs contain a programmable Turbo Bit set with the design software to control the a...

Page 69: ... PLUS software support includes schematic capture Boolean equation state machine and netlist design entry methods Altera Hardware Description Language AHDL waveform entry and EDIF 200 interface are available with MAX PLUS II Altera s EP610 Erasable Programmable Logic Device EPLD can implement up to 600 equivalent gates of SSI and MSI logic functions It is available in space saving windowed ceramic...

Page 70: ...e 40 85 C Te Case temperature For military use 55 125 C tR Input rise time See Note 3 100 50 ns tF Input fall time See Note 3 100 50 ns DC Operating Conditions See Notes 2 4 5 Symbol Parameter Conditions Speed Min Typ Max Unit Grade V IH High level input voltage 2 0 Vee 0 3 V V IL Low level input voltage 0 3 0 8 V VOH High level TTL output voltage IOH 4 rnA DC 2 4 V VOH High level CMOS output volt...

Page 71: ...elay 2 2 0 ns Global Clock Mode EP610 15 EP610 20 Non Turbo Adder Symbol Parameter Conditions Min Max Min Max See Note 9 Unit f MAX Maximum frequency See Note 11 83 3 62 5 0 MHz tsu Input setup time 9 11 20 ns tH Input hold time 0 0 0 ns tCH Clock high time 6 8 0 ns tCl Clock low time 6 8 0 ns tC01 Clock to output delay 11 13 0 ns tCNT Minimum clock period 12 16 0 ns fCNT Internal maximum frequenc...

Page 72: ...e 9 Unit fMAX Maximum frequency See Note 11 47 6 41 7 37 0 0 MHz tsu Input setup time 21 24 27 30 ns tH Input hold time 0 0 0 0 ns tCH Clock high time 10 11 12 0 ns tCl Clock low time 10 11 12 0 ns tC01 Clock to output delay 15 17 20 0 ns tCNT Minimum clock period 25 30 35 0 ns fCNT Internal maximum frequency See Note 7 40 0 33 3 28 6 0 MHz Array Clock Mode EP610 25 EP610 30 EP610 35 Non Turbo I A...

Page 73: ...asured with a device programmed as a 16 bit counter 8 Capacitance measured at 25 C Sample tested only Clock pin capacitance for dedicated clock inputs only For EP610 25 EP610 30 and EP610 35 EPLDs Pin 13 high voltage pin during programming has a maximum capacitance of 50 pF CIN COUT and CCLK 20 pF 9 See Turbo Bit earlier in this data sheet 10 Sample tested only for an output change of 500 mV 11 Th...

Page 74: ...cc vs Frequency EP610 15 and EP610 20 EPLDs 200 ci 150 IOL S Vee 5 0 V 1 TA 25 C 100 u 5 0 5 50 0 9 2 3 4 Va Output Voltage V All EP610 EPLDs 5 100 ci 10 S 13 1 0 9 0 1 IPage 64 Turbo Mode Vee 5 0 V TA 25 C Non Turbo Mode 1 KHz 10 KHz 100 KHz 1 MHz 10 MHz 80 MHz Maximum Frequency EP610 25 EP610 30 and EP610 35 EPLDs 80 ci 60 S Vee 5 0V 1 TA 25 C 40 u 5 0 5 20 0 9 Vo Output Voltage V A tera Corpora...

Page 75: ...ic capture Boolean equation state machine and netlist design entry methods Altera Hardware Description Language AHDL waveform entry and an EDIF 200 interface are available with MAX PLUS II Altera s EP610A Erasable Programmable Logic Device EPLD is a high speed version of the EP610 EPLD It offers enhanced performance and is available in reprogrammable plastic 24 pin 300 mil DIP 24 pin SOIC and 28 p...

Page 76: ... Operating temperature For industrial use 40 85 C Te Case temperature For military use 55 125 C tR Input rise time 25 ns tF Input fall time 25 ns DC Operating Conditions See Notes 2 3 Symbol Parameter Conditions Min Typ Max Unit V IH High level input voltage 2 0 Vee 0 3 V V IL Low level input voltage 0 3 0 8 V VOH High level TTL output voltage 10H 4 mA DC 2 4 V VOL Low level output voltage 10L 8 m...

Page 77: ... MAX Maximum frequency See Note 7 100 83 3 MHz tsu Input setup time 8 8 ns tH Input hold time 0 0 ns tCH Clock high time 5 6 ns tCL Clock low time 5 6 ns tC01 Clock to output delay 6 6 ns tCNT Minimum clock period 10 12 ns fCNT Internal maximum frequency See Note 4 100 83 3 MHz Array Clock Mode EP610A 10 EP610A 12 Symbol Parameter Conditions Min Max Min Max Unit fMAX Maximum frequency See Note 7 1...

Page 78: ...55 C to 125 C for military use 4 Measured with a device programmed as a 16 bit counter 5 Capacitance measured at 25 C Sample tested only Clock pin capacitance for dedicated clock inputs only Pin 13 high voltage pin during programming has a maximum capacitance of 50 pF 6 Sample tested only for an output change of 500 mY 7 The fMAX values represent the highest frequency for pipelined data Product Av...

Page 79: ...t includes schematic capture Boolean equation state machine and netlist design entry methods Altera Hardware Description Language AHDL waveform entry and an EDIF 2 0 0 interface are available with MAX PLUS II Altera s EP610T Erasable Programmable Logic Device EPLD is a low cost high performance version of the EP610 device This EPLD operates in a turbo mode that is optimized for high speed applicat...

Page 80: ...Input rise time See Note 2 100 ns tF Input fall time See Note 2 100 ns DC Operating Conditions See Notes 3 4 Symbol Parameter Conditions Min Typ Max Unit V IH High level input voltage 2 0 Vee 0 3 V VIL Low level input voltage 0 3 0 8 V V OH High level TTL output voltage 10H 4 mA DC 2 4 V VOH High level CMOS output voltage 10H 2 mA DC 3 84 V VOL Low level output voltage 10L 4 mA DC 0 45 V II Input ...

Page 81: ...AX Maximum frequency See Note 8 71 4 55 5 47 6 MHz t ASU Input setup time 6 8 8 ns tAH Input hold time 6 8 12 ns tACH Clock high time 7 9 10 ns tACl Clock low time 7 9 10 ns tAC01 Clock to output delay 15 20 27 ns tACNT Minimum clock period 14 18 25 ns f ACNT Internal maximum frequency See Note 5 71 4 55 5 40 0 MHz Ilotes to tables 1 The minimum DC input is 0 3 V During transitions the inputs may ...

Page 82: ...ical supply current versus frequency for the EP610T EPLD Figure 11 EP610T Output Drive Characteristics and Icc vs Frequency EP610 15T and EP610 20T EPLDs 200 ci 150 laL 5 Vee 5 0 V 1 100 TA 25 C J 5 Cl 5 50 0 9 2 3 4 Va Output Voltage V All EP610T EPLDs 5 100 ci 10 5 Q 1 0 o 2 0 1 IPage 72 Turbo Mode Vee 5 0 V TA 25 C 1 KHz 10 KHz 100 KHz 1 MHz 10 MHz 80 MHz Maximum Frequency EP610 25T EPLD 80 ci ...

Page 83: ...nd netlist design entry methods Altera Hardware Description Language AHDL waveform entry and an EDIF 2 0 0 interface are available with MAX PLUS II Altera s EP630 Erasable Programmable Logic Device EPLD is a fast low power version of the EP610 device The EP630 EPLD can implement a 16 bit counter at up to 83 MHz and typically consumes 5 rnA when operating at 1 MHz The EP630 EPLD is available in OTP...

Page 84: ...mmercial use 0 70 C TA Operating temperature For industrial use 40 85 C tR Input rise time See Note 2 40 ns tF Input fall time See Note 2 40 ns DC Operating Conditions See Notes 3 4 Symbol Parameter Conditions Min Typ Max Unit V IH High level input voltage 2 0 Vee 0 3 V V IL Low level input voltage 0 3 0 8 V VOH High level TTL output voltage 10H 4 mA DC 2 4 V VOH High level CMOS output voltage 10H...

Page 85: ...0 ns Global Clock Mode EP630 15 EP630 20 Non Turbo Adder Symbol Parameter Conditions Min Max Min Max See Note 8 Unit MAX Maximum frequency See Note 10 83 3 62 5 0 MHz tsu Input setup time 9 11 20 ns tH Input hold time 0 0 0 ns tCH Clock high time 6 8 0 ns tCl Clock low time 6 8 0 ns tC01 Clock to output delay 11 13 0 ns tCNT Minimum clock period 12 16 0 ns fCNT Internal maximum frequency See Note ...

Page 86: ...ested only Clock pin capacitance for dedicated clock inputs only 8 See Turbo Bit earlier in this data sheet 9 Sample tested only for an output change of 500 mV 10 The fMAX values represent the highest frequency for pipelined data Product Availability Operating Temperature Commercial Industrial Military 00 C to 700 C 400 C to 850 C 550 C to 1250 C Availability EP630 15 EP630 20 EP630 20 Consult fac...

Page 87: ... Devices EPLDs can implement up to 900 equivalent gates of SSI and MSI logic These EPLDs are available in windowed ceramic or one time programmable OTP plastic 40 pin dual in line packages CerDIP and PDIP and 44 pin J lead chip carriers JLCC and PLCC EP910 EPLDs use sum of products logic that consists of a programmable AND fixed OR structure They accommodate combinatorial and sequential logic func...

Page 88: ...grammed in seconds at the designer s desktop to create customized working silicon In addition extensive third party supportexists for designentry designprocessing and device programming The EP910 EPLD is pin function and JEDEC File compatible with the EP910A and EP910T EPLDs JEDEC Files generated for an EP910 EPLD can be used for programming these devices EP910 The EP910 EPLD combines high speed w...

Page 89: ...ear control of the internal register and 1 product term implements either Output Enable or an array Clock o 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 1 0 Architecture Control 110 I I I t 0I t 00 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ...

Page 90: ...19 21 PageBO Numbers in parentheses are for J eadpackages 72 Macrocell13 Macrocell1 Macrocell14 Macrocell2 Macrocell15 Macrocell3 Macrocefl16 Macrocefl4 Macrocell21 Macrocell9 Macrocell22 Macrocell10 Macrocell23 Macrocell11 Macrocell24 Macrocefl12 72 Data Sheet I 39 43 38 42 37 41 1 036 40 1 035 38 1 034 37 1 033 36 1 028 31 1 027 30 1 026 29 11025 28 Altera Corporation ...

Page 91: ...edicated Clock inputs which are not available in the AND array provide the signals used for global clocking of EP910 internal registers Each signal is positive edge triggered and has control over 12 registers CLKl controls macrocells 13 to 24 CLK2 controls macrocells 1 to 12 The programmable I 0 architecture allows each of the 24 internal registers to have a global or array Clock product term mode...

Page 92: ...K Q Macrocell Output Buffer Macrocell 1 0 Register In Mode 0 the tri state outputbuffer is controlledby a single product term If the output of the AND gate is high the output buffer is enabled If th output is low the output buffer has a high impedance value In this mode the macrocell flip flop is clocked by its global Clock input signal CLKl Ol CLK2 In the erased state the OE CLK Select multiplexe...

Page 93: ...hronous Clear Output __________________________ i ___________ Global Clock Mode CLK1 CLK2 Valid Input Input or I O may Change Input or I O may change Valid Output tc01 from register to output X Array Clock Mode tACH t ACL t ix X XL _ Jix x tA S J U t AH j Array Clock Input Valid Input Input or I O may change Input or I O may change Valid Output from register to output x Output configurations avail...

Page 94: ...ction OutputIPolarity JK Register High JK Register Low None SR Flip Flop 110 Selection Output Polarity SR Register High SR Register Low None Feedback Pin None Pin None Pin Feedback D Register Pin None D Register Pin None D Register Pin Feedback T Register Pin None T Register Pin None T Register Pin Feedback JK Register None JK Register None JK Register Feedback SR Register None SR Register None SR...

Page 95: ...tputs of the OR gates feed two primary register inputs This configuration has the following characteristics o The MAX PLUS II or A PLUS development system optimizes the allocation of product terms for each register input o One product term controls asynchronous Clear o The Invert Select EPROM bits control output polarity o The OE CLK Select multiplexer configures the operation mode to Mode 0 or Mo...

Page 96: ...rogrammed into the device If this feature is used a proprietary design implemented in the device cannot be copied or retrieved This feature provides a high level of design security by making programmed data within EPROM cells invisible The Security Bit as well as other program data is reset by erasing the EPLD EP910 EPLDs contain a programmable Turbo Bit set with design software to control the aut...

Page 97: ...ammable as D T JK or SR flip flops or for combinatorial operation o Extensive third party software and programming support o MAX PLUS II and A PLUS software support includes schematic capture Boolean equation state machine and netlist design entry methods Altera Hardware Description Language AHDL waveform entry and an EDIF 2 0 0 interface are available with MAX PLUS II Altera s EP910 Erasable Prog...

Page 98: ...TA Operating temperature For industrial use 40 85 C Te Case temperature For military use 55 125 C tR Input rise time See Note 3 100 50 ns tF Input fall time See Note 3 100 50 ns DC Operating Conditions See Notes 2 4 5 Symbol Parameter Conditions Min Typ Max Unit V IH High level input voltage 2 0 Vee 0 3 V V IL Low level input voltage 0 3 0 8 V V OH High level TTL output voltage IOH 4 rnA DC 2 4 V ...

Page 99: ... 0 30 EP91 0 35 EP91 0 40 Non Turbo Adder Symbol Parameter Conditions Min Max Min Max Min Max Note 9 Unit Maximum frequency See Note 11 41 7 37 0 32 3 0 MHz MAX SU Input setup time 24 27 31 30 ns H Input hold time 0 0 0 0 ns CH Clock high time 12 13 15 0 ns CL Clock low time 12 13 15 0 ns C01 Clock to output delay 18 21 24 0 ns CNT Minimum clock period 30 35 40 0 ns Internal maximum frequency See ...

Page 100: ...pF 9 See Turbo Bit earlier in this data sheet 10 Sample tested only for an output change of 500 mY 11 The fMAX values represent the highest frequency for pipelined data Product Availability Operating Temperature Commercial Industrial Military 0 C to 70 C 40 C to 85 C 55 C to 125 C Availability EP91 0 30 EP91 0 35 EP91 0 40 EP910 35 EP910 40 EP91 0 40 Note Only military temperature range devices ar...

Page 101: ...rd party software and programming support o MAX PLUS II and A PLUS software support includes schematic capture Boolean equation state machine and netlist design entry methods Altera Hardware Description Language AHDL waveform entry and an EDIF 2 0 0 interface are available with MAX PLUS II Altera s EP910A Erasable Programmable Logic Device EPLD is a pin compatible version of the EP910 EPLD It offe...

Page 102: ...erature For industrial use 40 85 C Tc Case temperature For military use 55 125 C tR Input rise time 25 ns tF Input fall time 25 ns DC Operating Conditions See Notes 2 3 Symbol Parameter Conditions Min Typ Max Unit V IH High level input voltage 2 0 Vee 0 3 V V IL Low level input voltage 0 3 0 8 V V OH High level TTL output voltage IOH 4 rnA DC 2 4 V VOL Low level output voltage IOL 4 rnA DC 0 5 V I...

Page 103: ...Maximum frequency See Note 8 83 3 62 5 MHz tsu Input setup time 10 15 ns tH Input hold time 0 0 ns tCH Clock high time 6 8 ns tCl Clock low time 6 8 ns tCOl Clock to output delay 8 15 ns tCNT Minimum clock period 14 25 ns fCNT Internal maximum frequency See Note 4 71 4 40 MHz Array Clock Mode EP910A 15 EP910A 25 Note 6 Symbol Parameter Conditions Min Max Min Max Unit fMAX Maximum frequency See Not...

Page 104: ...F 6 This version is under development Specifications are subject to change Consult factory for additional information 7 Sample tested only for an output change of 500 mY 8 The fMAX values represent the highest frequency for pipelined data Product Availability Operating Temperature Availability Commercial 0 C to 70 C EP910A 25 Industrial 40 C to 85 C Consult factory Military 55 C to 125 C Consult f...

Page 105: ...d o Extensive third party software and programming support o MAX PLUS II and A PLUS software support includes schematic capture Boolean equation state machine and netlist design entry methods Altera Hardware Description Language AHDL waveform entry and an EDIF 200 interface are available with MAX PLUS II Altera s EP910T Erasable Programmable Logic Device EPLD is a low cost high performance version...

Page 106: ...nput rise time See Note 2 100 ns tF Input fall time See Note 2 100 ns DC Operating Conditions See Notes 3 4 Symbol Parameter Conditions Min Typ Max Unit V IH High level input voltage 2 0 Vee 0 3 V V IL Low level input voltage 0 3 0 8 V VOH High level TTL output voltage IOH 4 mA DC 2 4 V V OH High level CMOS output voltage IOH 2 mA DC 3 84 V VOL Low level output voltage IOL 4 mA DC 0 45 V II Input ...

Page 107: ...nit fMAX Maximum frequency See Note 8 33 3 MHz t ASU Input setup time 10 ns tAH Input hold time 15 ns tACH Clock high time 15 ns tACL Clock low time 15 ns tAC01 Clock to output delay 33 ns tACNT Minimum clock period 30 ns fACNT Internal maximum frequency See Note 5 33 3 MHz Votes to tables 1 The minimum DC input is 0 3 V During transitions the inputs may undershoot to 2 0 V or overshoot to 7 0 V f...

Page 108: ...put drive characteristics for EP910T 110 pins and typical supply current versus frequency for the EP910T EPLD Figure 12 EP910T Output Drive Characteristics and Icc vs Frequency 60 ci 50 S 40 C 30 J c 20 J a 9 10 0 0 45 IPage 98 IOL 2 Vee 5 0 V TA 25 C 3 4 Vo Output Voltage V 100 000 Turbo Mode ci 10 S Vee 5 0 V Q TA 25 C U 1 0 0 9 0 1 5 1 KHz 10 KHz 100 KHz 1 MHz 10 MHz 40 MHz Maximum Frequency A ...

Page 109: ... replace 20 to 30 SSI and MSI packages These EPLDs are available in 68 pin windowed ceramic and one time programmable plastic J Iead aLCC and PLCC and windowed ceramic pin grid array PGA packages EP1810 EPLDs are designed as LSI replacements for traditional low power Schottky TTL logic circuits and low density Programmable Logic Devices PLDs These devices have the integration density to replace fi...

Page 110: ...ounters at up to 50 MHz and typically consumes less than 20 rnA when operating at 1 MHz It is available with maximum tpD values of 20 25 35 and 45 ns Both MIL STD 883B compliant and DESC approved parts are available EP1810T The EP1810T EPLD is a lower cost version of the EP1810 device This device operates in Turbo mode only The Turbo Bit in the EPLD is preset at the factory The E1810T EPLD is avai...

Page 111: ...sures maximum I O flexibility Figure 1 EP1810 Local Macrocell Global Bus local Bus OE ClK l o en E 2 31 t5 541 o a 51 I 6 I I 7 I CLEAR 1 1 1 I Global Dedicated Inputs 16 inputs I Quadrant A B C D Global Feedback 16 Macrocells I Quadrant local Feedback 12 Macrocells I O Architecture Control ClK I O Pin Each macrocell consists of a logic array a tri state I O buffer and a selectable register elemen...

Page 112: ...connected to the product terms An EPROM control cell is located at each intersectionofanAND arrayinput and aproduct term During programming selected connections are opened allowing any productterm tobe connected to a true or complement array input signal Each internal flip flop in EP1810 EPLDs can be clocked independently or in user defined groups Each internal register may select its clock source...

Page 113: ...nt D J 1 J INPUT J 1 J INPUT J 1 J INPUT 1 0 68 El 1 0 67 E2 1 066 01 1 065 02 1 0 64 Cl 1 0 63 C2 1 062 81 1 061 82 I O 60 A2 1 0 59 A3 1 0 58 83 1 0 57 M 56 84 55 A5 54 85 J J INPUT CLK4 53 A6 J 1 J INPUT CLK3 51 A7 J J INPUT J i J INPUT J 1 J INPUT 111 Global Macrocelis D Local Macrocelis 50 87 49 AS 48 88 1 0 47 A9 1 0 46 89 1 0 45 Al0 1 0 44 810 1 0 43 811 1 0 42 Cll 1 0 41 Cl0 1 0 40 011 1 0...

Page 114: ...racteristics Input Pin are measured at 1 5 V Logic Array Input Logic Array Output Output Pin Clock Pin Clock into Logic Array Clock from Logic Array Data from Logic Array Register Output to Logic Array Global Clock Pin Global Clock at Register Data from Logic Array Clock from Logic Array Data from Logic Array Output Pin IPage 104 i tlO tpD2 tlO tIN X i tIN l X tLAO t tCLR Array Clock Mode tR i tAC...

Page 115: ...d generic testing is unique to EPLDs The EPLDs also contain on board test circuitry that allows verification of functions and AC specifications for one time programmable packages AC test measurements are performed under the conditions shown in Figure 6 Figure 6 EP1810 AC Test Conditions Power supply transients can affect AC measurements Simultaneous transitions of multiple outputs should be avoide...

Page 116: ...ng the EPLD All EP18I0 EPLDs contain a Turbo Bit set with the design software to control the automatic power down feature that enables the low standby power mode When the Turbo Bit is programmed Turbo On the low standby power mode ICCl is disabled making the circuit less sensitive to Vcc noise transients from the non turbo mode power up power down cycle All AC values are tested with the Turbo Bit ...

Page 117: ...esign entry methods Altera Hardware Description Language AHDL waveform entry and an EDIF 200 interface are available with MAX PLUS II General Description The EP1810 Erasable Programmable Logic Device EPLD offers LSI density TTL equivalent speed and low power consumption It is available in 68 pin windowed ceramic and OTP plastic J Iead chip carrier and windowed ceramic PGA packages See Figure 7 Fig...

Page 118: ...l use 40 85 C Te Case temperature For military use 55 125 C tR Input rise time See Note 3 50 ns tF Input fall time See Note 3 50 ns DC Operating Conditions See Notes 2 4 5 Symbol Parameter Conditions Speed Min Typ Max Unit Grade V IH High level input voltage 2 0 Vee 0 3 V V IL Low level input voltage D 3 U H V VOH High level TTL output voltage IOH 4 mA DC 2 4 V VOH High level CMOS output voltage I...

Page 119: ...w time 8 10 0 ns tASU Array clock setup time 8 10 25 ns tAH Array clock hold time 8 10 0 ns t AC01 Array clock to output delay C1 35 pF 20 25 25 ns tCNT Minimum global clock period 20 25 0 ns tCNT Maximum internal frequency See Note 7 50 40 0 MHz tMAX Maximum clock frequency See Note 10 62 5 50 0 MHz Internal Timing Parameters EP1810 20 EP1810 25 Non Turbo Adder Symbol Parameter Conditions Min Max...

Page 120: ...uency See Note 7 28 6 22 2 0 MHz f MAX Maximum clock frequency See Note 10 40 33 3 0 MHz Internal Timing Parameters EP1810 35 EP1810 45 Non Turbo Adder Symbol Parameter Conditions Min Max Min Max See Note 9 Unit tIN Input pad and buffer delay 7 7 0 ns tlO I O input pad and buffer delay 5 5 0 ns tLAD Logic array delay 19 27 30 ns too Output buffer and pad delay C1 35 pF 9 11 0 ns tzx Output buffer ...

Page 121: ...his data sheet 10 The fMAX values represent the highest frequency for pipelined data 11 Sample tested only for an output change of 500 mV 12 DCIAC specifications for EP181O 40 industrial are available by calling Altera s Marketing Department at 408 984 2800 13 Only military temperature range devices are listed above MIL STD 883 compliant product specifications are provided in Military Product Draw...

Page 122: ... Frequency EP181 0 20 and EP1810 25 EPLDs 200 ci F 150 S E 100 Q S a S o 50 r f _ _ 0 45 1 2 3 4 V0 Output Voltage V All EP181 0 EPLDs 100 Turbo Mode ci F 10 S 0 I _r n l j j oJ V U 1 0 TA 250 C 0 2 5 Non Turbo Mode 0 1 10 KHz 100 KHz 1 MHz 10 MHz 60 MHz Maximum Frequency IPage 112 EP181 0 35 and EP181 0 45 EPLDs 80 ci F 60 S E 40 u S a S o 2 Vee 5 0 V TA 25 0 C 3 4 Vo Output Voltage V 5 Altera Co...

Page 123: ...e Description Language AHDL waveform entry and an EDIF 2 0 0 interface are available with MAX PLUS II Altera s EP1810T Erasable Programmable Logic Device EPLD is a low cost high performance version of the EP1810 device This EPLD operates in a turbo mode that is optimized for high speed applications The Turbo Bit in the device is preset at the factory The EP1810T EPLD is available in OTP plastic 68...

Page 124: ... tF Input fall time See Note 2 50 ns DC Operating Conditions See Notes 3 4 Symbol Parameter Conditions Speed Min Typ Max Unit Grade VIH High level input voltage 2 0 Vee 0 3 V VIL Low level input voltage 0 3 0 8 V VOH High level TTL output voltage IOH 4 mA DC 2 4 V VOH High level CMOS output voltage IOH 2 mA DC 3 84 V VOL Low level output voltage IOL 4 mA DC UAb i II Input leakage current VI Vec or...

Page 125: ...AD Logic array delay 9 12 19 ns taD Output buffer and pad delay C1 35 pF 6 6 9 ns tzx Output buffer enable delay 6 6 9 ns txz Output buffer disable delay C1 5 pF See Note 8 6 6 9 ns tsu Register setup time 8 10 10 ns tH Register hold time 8 10 15 ns tiC Array clock delay 9 12 19 ns tiCS Global clock delay 4 5 4 ns tFD Feedback delay 3 3 6 ns tCLR Register clear time 9 12 24 ns Notes to tables 1 Th...

Page 126: ...supply current versus frequency for the EP1810T EPLD Figure 10 EP1810T Output Drive Characteristics and Icc vs Frequency EP1810 20T and EP1810 25T EPLDs 200 ci 150 IOL S Vee 5 0 V C 100 TA 25 C s S 0 S 50 0 9 0 45 1 2 3 4 V0 Output Voltage V All EP181 OT EPLDs 5 _ 100 r Turbo Mode ci 10 r S Q Vee 5 0 V n 1 0 r TA 25 C 0 2 0 1 r I 10 KHz 100 KHz 1 MHz 10MHz 60 MHz Maximum Frequency IPage 116 EP1810...

Page 127: ...ncludes schematic capture Boolean equation state machine and netlist design entry methods Altera Hardware Description Language AHDL waveform entry and an EDIF 2 0 0 interface are available with MAX PLUS II Altera s EP1830 Erasable Programmable Logic Device EPLD is a fast low power version of the EP1810 device The EP1830 can implement four 12 bit counters at up to 50 MHz and typically consumes 20 r...

Page 128: ...ercial use 0 70 C TA Operating temperature For industrial use 40 85 C tR Input rise time See Note 2 50 ns tF Input fall time See Note 2 50 ns DC Operating Conditions See Notes 3 4 Symbol Parameter Conditions Min Typ Max Unit V IH High level input voltage 2 0 Vee 0 3 V V IL Low level input voltage 0 3 0 8 V VOH High level TTL output voltage IOH 4 mA DC 2 4 V vOH High ievei CiviOS output voitage iOH...

Page 129: ...10 0 ns tASU Array clock setup time 8 10 25 ns tAH Array clock hold time 8 10 0 ns tAC01 Array clock to output delay C1 35 pF 20 25 25 ns tCNT Minimum global clock period 20 25 0 ns fCNT Internal maximum frequency See Note 6 50 40 0 MHz f MAX Maximum frequency See Note 9 62 5 50 0 MHz Internal Timing Parameters EP1830 20 EP1830 25 Non Turbo Adder Symbol Parameter Conditions Min Max Min Max See Not...

Page 130: ...nly Clock pin capacitance for dedicated clock inputs only 8 See Turbo Bit earlier in this data sheet 9 The fMAX values represent the highest frequency for pipelined data 10 Sample tested only for an output change of 500 mY Product Availability Operating Temperature Availability Commercial 0 C to 70 C EP1830 20 EP1830 25 EP1830 30 Industrial 40 C to 85 C EP1830 25 Military 55 C to 125 C Consult fac...

Page 131: ...s The Complete Industry Standard Programmable Logic Family 123 EPM5016 to EPM5192 EPLDs High Speed High Density MAX 5000 Devices 125 EPM5016 EPLD 137 EPM5032 EPLD 143 EPM5064 EPLD 149 EPM5128 EPLD 155 EPM5130 EPLD 161 EPM5192 EPLD 169 1 Altera Corporation Page 1211 ...

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Page 133: ...IAltera Corporation Page 123 I ...

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Page 135: ... up to 100 MHz pipelined data rates of 100 MHz and high complexity designs with true system clock rates up to 66 MHz o Available in a wide variety of packages including DIP SOIC J Iead PGA and QFP formats in windowed ceramic and plastic one time programmable versions o MAX PLUS and MAX PLUS II PC and workstation based development tools compile large designs in minutes o An industry standard EDIF i...

Page 136: ...term expansion on any data or control path o MAX PLUS MAX PLUS II Design Tools Design entry via unified hierarchical schematic capture Altera Hardware Description Language AHDL and waveform design entry waveform entry in MAX PLU5 II only Fast automatic design processing with logic synthesis Automatic design partitioning into multiple EPLDs MAX PLU5 II only Automatic device fitting no hand editing ...

Page 137: ...ns over a wide range oflogic densities Migration from one type of device to another is easy For example the EPM5128 and EPM5130 EPLDs have the same logic capacity but have packages optimized to handle different I O requirements Over the entire family a wide range of packaging options for both through hole and surface mount applications is available Plastic one time programmable OTP packages are av...

Page 138: ...grated into MAX 5000 EPLDs The outputs of the macrocells feed the decoupled I O block which consists of a group of programmable tri state buffers and I O pins In the EPM5064 EPM5128 EPM5130 and EPM5192 EPLDs multiple LABs are connected by a Programmable Interconnect Array PIA 1 1 0 Pins I gl IQlI I I IQl I I I I I I I ___________________ i The MAX 5000 macrocell shown in Figure 3 consists of a pro...

Page 139: ...flop The Clock product term allows each register to have an independent Clock and supports positive and negative edge triggered operation Macrocells that drive an output pin may use the Output Enable product term to control the active high tri state buffer in the I O control block These secondary product terms allow 7400 series TTL functions to be emulated exactly The MAX 5000 macrocell configurab...

Page 140: ...ter and product term intensive designs for MAX 5000 EPLDs Figure 4 Expander Product Terms to Macrocell Array and Expander Product Term Array Expander product terms are unallocated logic that can be used and shared by all macrocells in an LAB Sharing allows efficient integration of complex combinatorial functions L L 1 t 1 0 Control Block IPage 130 Macrocell and 1 0 Feedbacks L 1 L I u u 8 to 20 Pr...

Page 141: ...sity MAX 5000 devices EPM5064 EPM5128 EPM5130 and EPM5192 use a Programmable Interconnect Array PIA to route signalsbetween the various LABs The PIA routes only the signals required for implementing logic in an LAB and is fed by all macrocell feedbacks and all I O pin feedbacks Unlike channel routing in masked or programmable gate arrays where routing delays are variable and path dependent the PIA...

Page 142: ...y t CS tzx r 0 Pin IQI ilfO Clock r Delay Delay t C t O I Feedback l Delay I tFD I The timing models shown in Figure 6 can be used together with the internal timing parameters for a particular EPLD to derive timing information External timing parameters are derived from a sum ofinternal parameters and represent pin to pin timing delays Figure 7 shows the internal timing waveforms for these devices...

Page 143: ...Input Logic Array Output Output Pin Clock Pin Clock into Logic Array Clock from Logic Array Data from Logic Array Register Output to local LAB Logic Array Register Output to another LAB Global Clock Pin Global Clock at Register Data from Logic Array Clock from Logic Array Data from Logic Array Output Pin i tEXP i x ______ tCOMB i i 1 too i _____________________________________ __ x Array Clock Mod...

Page 144: ...3 ns VCC to Test System C1 includes JIG capacitance Test programs can be used and then erased during early stages of the production flow This facility to use application independent general purpose tests called generic testing is unique among user configurable logic devices EPLDs also contain on board logic test circuitry to allow verification of function and AC specifications of devices in window...

Page 145: ... details about the MAX PLUS and MAX PLUS II development systems are available in the PLDS MAX PLS MAX PLS WS HP PLS WS SN and PLDS HPS PLS HPS PLS OS PLS ES data sheets in this data book MAX 5000 EPLDs can be programmed on an IBM PS 2 PC AT or compatible computer with an Altera Logic Programmer card the Master Programming Unit MPU and an appropriate device adapter These items are included in the c...

Page 146: ...Notes ...

Page 147: ... Available in 20 pin windowed ceramic DIP package or plastic one time programmable OTP DIP J Iead PLCC and 300 mil SOIC packages The Altera EPMS016 EPLD is a Multiple Array MatriX MAX SOOO family CMOS EPLD that is optimized for speed It can integrate multiple SSI and MSI TTL and 74HC devices In addition it can replace any 20 pin PAL or PLA device with logic left over for further integration See Fi...

Page 148: ...4 5 ci S Q u l _0 180 150 120 Vee 5 0 V Room Temp 90 60 30 100 Hz 1 KHz 10 KHz 100 KHz 1 MHz 10 MHz 100 MHz Va Output Voltage V Maximum Frequency The EPM5016 EPLD contains 16 macrocells see Figure 11 The expander product term array for the EPM5016 EPLD contains 32 expanders The l 0 control block contains 8 bidirectionall O pins that can be configured for dedicated input dedicated output or bidirec...

Page 149: ...4 MACROCELL6 MACROCELL8 MACROCELL 10 MACROCELL 12 MACROCELL 14 MACROCELL 16 I N T E R C 0 N N E C T I INPUT 1 6 INPUT CLK 2 7 INPUT I INPUT 9 14 10 15 MACROCELL3 MACROCELL5 MACROCELL 7 I O Control MACROCELL9 Block MACROCELL 11 MACROCELL 13 MACROCELL 15 Expander Product Term Array 32 Altera Corporation EPM5016 EPLD 1 1 03 8 1 0 4 9 I O 7 12 I O 8 13 I O 13 18 I O 14 19 I O 17 2 I O 18 3 Page 1391 ...

Page 150: ...t voltage 0 Vee V TA Operating temperature For commercial use 0 70 C TA Operating temperature For industrial use 40 85 C tR Input rise time 100 ns tF Input fall time 100 ns DC Operating Conditions See Notes 2 3 4 Symbol Parameter Conditions Min Typ Max Unit VIH High level input voltage 2 0 Vee 0 3 V V IL Low level input voltage 0 3 0 8 V VOH High level TTL output voltage IOH mA DC 2 4 I v VOL Low ...

Page 151: ... 3 62 5 MHz t ACNT Minimum array clock period 10 12 16 ns fACNT Max internal array clock frequency See Note 5 100 83 3 62 5 MHz f MAX Maximum clock frequency See Note 7 100 83 3 62 5 MHz Internal Timing Parameters See Note 8 EPM5016 15 EPM5016 17 EPM5016 20 Symbol Parameter Conditions Min Max Min Max Min Max Unit tiN Input pad and buffer delay 4 5 5 ns tlO I O input pad and buffer delay 4 5 5 ns t...

Page 152: ... Vee 5 V 10 TA 40 C to 85 C for industrial use 5 Measured with a device programmed as a 16 bit counter 6 This parameter is measured with a positive edge triggered clock at the register For negative edge clocking the tACH and tACL parameters must be swapped 7 The fMAX values represent the highest frequency for pipelined data 8 For information on internal timing parameters refer to Application Brief...

Page 153: ...OTP 300 mil SOIC packages The Altera EPMS032 EPLD is a Multiple Array MatriX MAX SOOO family CMOS EPLD optimized for speed It can integrate multiple SSI and MSI TTL and 74HC devices In addition it can replace multiple 20 pin PAL or PLA devices with logic left over for further integration See Figure 12 Figure 12 EPM5032 Package Pin Out Diagrams Package outlines not drawn to scale INPUT INPUT 0 INPU...

Page 154: ...Temp 3 4 5 ci s Q U 9 240 200 160 Vee 5 0 V Room Temp 120 80 40 100 Hz 1 KHz 10 KHz 100 KHz 1 MHz 10 MHz 100 MHz Vo Output Voltage V Maximum Frequency The EPM5032 EPLD contains 32 macrocells see Figure 14 The EPM5032 expander product term array contains 64 expanders The I O control block contains 16bidirectional1 a pins that canbe configured for dedicated input dedicated output or bidirectional op...

Page 155: ...12 N MACROCELL 11 MACROCELL 14 N MACROCELL 13 E MACROCELL 16 C MACROCELL 15 MACROCELL 18 T MACROCELL 17 MACROCELL 20 MACROCELL 19 MACROCELL 22 MACROCELL 21 MACROCELL 24 MACROCELL 23 MACROCELL 26 MACROCELL 25 MACROCELL 28 MACROCELL 27 MACROCELL 30 MACROCELL 29 MACROCELL 32 MACROCELL 31 T Expander Product Term Array 64 INPUT 1 8 c J INPUT CLK 2 9 c J INPUT 13 20 INPUT 14 21 f I O f J Control Block f...

Page 156: ...g temperature For commercial use 0 70 C TA Operating temperature For industrial use 40 85 C Tc Case temperature For military use 55 125 C tR Input rise time 100 ns tF Input fall time 100 ns DC Operating Conditions See Notes 2 3 4 Symbol Parameter Conditions Min Typ Max Unit High lI vAI inrllt voltFl JA 2 0 Vee 0 3 V In VIL Low level input voltage 0 3 0 8 V VOH High level TIL output voltage 10H 4 m...

Page 157: ...0 MHz t ACNT Minimum array clock period 13 14 16 20 ns ACNT Max internal array clock frequency See Note 5 76 9 71 4 62 5 50 MHz MAX Maximum clock frequency See Note 7 83 3 83 3 71 4 62 5 MHz Internal Timing Parameters See Note 8 EPM5032 15 EPM5032 17 EPM5032 20 EPM5032 25 Symbol Parameter Conditions Min Max Min Max Min Max Min Max Unit tIN Input pad and buffer delay 4 5 5 7 ns t O I O input pad an...

Page 158: ... positive edge triggered clock at the register For negative edge clocking the tACH and tACL parameters must be swapped 7 The fMAX values represent the highest frequency for pipelined data 8 For information on internal timing parameters refer to Application Brief75 Product Availability Operating Temperature Availability Commercial 0 C to 70 C EPM5032 15 EPM5032 17 EPM5032 20 EPM5032 25 Industrial 4...

Page 159: ...ic or plastic one time programmable packages for volume production The Altera EPMS064 EPLD is a user configurable high performance Multiple Array MatriX MAX SOOO family EPLD that serves as a high density replacement for 7400 series SSI and MSI TTL and CMOS logic In addition it can integrate multiple 20 and 24 pin low density PLDs For example the EPMS064 EPLD can integrate the logic contained in ov...

Page 160: ... V Maximum Frequency The EPM5064 consists of 64 macrocells equally divided into 4 Logic Array Blocks LABs that each contain 16 macrocells see Figure 17 Each LAB also contains 32 expander product terms The flexibility of the LABs allows easy integration of any common PLD The EPM5064 EPLD has 8 dedicated input pins one of which can be used as a global system dock th t provides enhanced dock to OUtpl...

Page 161: ...ELL 19 MACROCELL 20 MACROCELL 21 MACROCELL 22 MACROCELL 23 MACROCELL 24 MACROCELLS 25 to 32 Dedicated Inputs Global Clock r v Programmable Interconnect Arra PIA 1 EPM5064 EPLD I INPUT 35 INPUT CLK 34 INPUT rI INPUT LABD MACROCELL 56 MACROCELL 55 MACROCELL 54 MACROCELL 53 MACROCELL 52 MACROCELL 51 MACROCELL 50 MACROCELL 49 MACROCELLS 57 to 64 1 LABC MACROCELL 38 MACROCELL 37 MACROCELL 36 MACROCELL ...

Page 162: ...erating temperature For commercial use 0 70 C TA Operating temperature For industrial use 40 85 C Te Case temperature For military use 55 125 C tR Input rise time 100 ns tF Input fall time 100 ns DC Operating Conditions See Notes 2 3 4 Symbol Parameter Conditions Min Typ Max Unit v HiQh level input voltaQe 2 0 Vee 0 3 V V IL Low level input voltage 0 3 0 8 V VOH High level TTL output voltage IOH 4...

Page 163: ...um array clock period 20 25 30 ns f ACNT Max internal array clock frequency See Note 5 50 40 33 3 MHz f MAX Maximum clock frequency See Note 7 62 5 50 40 MHz Internal Timing Parameters See Note 8 EPM5064 1 EPM5064 2 EPM5064 Symbol Parameter Conditions Min Max Min Max Min Max Unit tIN Input pad and buffer delay 5 7 9 ns t O I O input pad and buffer delay 6 6 9 ns tExP Expander array delay 12 14 20 ...

Page 164: ... is measured with a positive edge triggered clock at the register For negative edge clocking the tACH and tACL parameters must be swapped 7 The fMAX values represent the highest frequency for pipelined data 8 For information on internal timing parameters refer to Application Brief75 Product Availability Operating Temperature Availability Commercial 0 C to 70 C EPM5064 1 EPM5064 2 EPM5064 Industria...

Page 165: ...nfigurable high performance Multiple Array MatriX MAX 5000 family EPLD that provides a high density replacement for 7400 series 55I and M5I TTL and CM05 logic For example a 74161 counter uses only3 of the EPM5128 EPLD The EPM5128 EPLD can replace over 60 TTL M5I and 55I components and integrate multiple 20 and 24 pin low density PLDs Figure 18 shows the J lead and PGA package diagrams for the EPM5...

Page 166: ...1 KHz 10 KHz 100 KHz 1 MHz 10 MHz 50 MHz Vo Output Voltage V Maximum Frequency The EPM5128 EPLD consists of 128 macrocells equally divided into 8 Logic Array Blocks LABs that each contain 16 macrocells see Figure 20 Each LAB also contains 32 expander product terms The EPM5128 EPLD has 8 dedicated input pins one of which may be used as a global synchronous system clock The EPM5128 device contains 5...

Page 167: ...OCELL 53 MACROCELL 54 MACROCELL 55 MACROCELL 56 MACROCELLS 571064 C 1 Dedicated Inputs Global Clock l k Programmable Interconnect Arra PIA r v EPM5128 EPLD I INPUT A7 68 INPUT A8 66 INPUT L6 36 c J INPUT K6 35 l LABH MACROCELL 120 i o MACROCELL 119 MACROCELL 118 MACROCELL 117 I MACROCELL 116 r MACROCELL 115 MACROCELL 114 MACROCELL 113 Q MACROCELLS 121 to 128 LABG MACROCELL 101 MACROCELL 100 MACROC...

Page 168: ...ting temperature For commercial use 0 70 C TA Operating temperature For industrial use 40 85 C Te Case temperature For military use 55 125 C tR Input rise time 100 ns tF Input fall time 100 ns DC Operating Conditions See Notes 2 3 4 Symbol Parameter Conditions Min Typ Max Unit V1H High level input voltage 2 0 Vee 0 3 V V IL Low level input voltage 0 3 0 8 V VOH High level TTL output voltage 10H 4 ...

Page 169: ...m array clock period 20 25 30 ns f ACNT Max internal array clock frequency See Note 5 50 40 33 3 MHz f MAX Maximum clock frequency See Note 7 62 5 50 40 MHz Internal Timing Parameters See Note 8 EPM5128 1 EPM5128 2 EPM5128 Symbol Parameter Conditions Min Max Min Max Min Max Unit tIN Input pad and buffer delay 5 7 9 ns tlO I O input pad and buffer delay 6 6 9 ns tEXP Expander array delay 12 14 20 n...

Page 170: ...re Availability Commercial 0 C to 70 C EPM5128 1 EPM5128 2 EPM5128 Industrial 40 C to 85 C EPM5128 Military 55 C to 125 C EPM5128 Note Only military temperature range EPLDs are listed above MIL STD 883 compliant product specifications are provided in Military Product Drawings MPDs available by calling Altera Marketing at 408 984 2800 These MPDs should be used to prepare Source Control Drawings SCD...

Page 171: ...indowed ceramic PCA and windowed ceramic and one time programmable OTP plastic QFP packages o Programmable I O architecture that allows up to 68 inputs or 48 outputs in windowed ceramic and plastic OTP J Iead packages The EPM5130 EPLD see Figure 21 is a user configurable high performance Multiple Array Matrix MAX 5000 family EPLD that is optimized for pin intensive designs It provides a high densi...

Page 172: ...0 Room Temp 5 Room Temp Q g 200 IOH 0 2 100 2 3 4 5 100 Hz 1 KHz 10 KHz 100 KHz 1 MHz 10 MHz 50 MHz V0 Output Voltage V Maximum Frequency The EPM5l30 EPLD consists of 128 macrocells equally divided into 8 Logic Array Blocks LABs each containing 16 macrocells and 32 expander product terms see Figure 23 Expander product terms can be used and shared by all macrocells in the device to ensure efficient...

Page 173: ...0 MACROCELL 51 MACROCELL 52 MACROCELL 53 I MACROCELL 54 MACROCELL 55 MACROCELL 56 MACROCELLS 571064 r INPUT 36 N4 59 INPUT 37 M5 60 INPUT 38 N5 61 INPUT 41 N6 64 INPUT 42 M7 65 INPUT 43 L7 66 INPUT 44 N7 67 c J INPUT 47 L8 70 c J INPUT 48 N9 71 c J INPUT 49 M9 72 Dedicated Inputs n Global Clock LABH MACROCELL 120 MACROCELL 119 MACROCELL 118 MACROCELL 117 f i MACROCELL 116 MACROCELL 115 7 MACROCELL...

Page 174: ...ting temperature For commercial use 0 70 C TA Operating temperature For industrial use 40 85 C Te Case temperature For military use 55 125 C tR Input rise time 100 ns tF Input fall time 100 ns DC Operating Conditions See Notes 2 3 4 Symbol Parameter Conditions Min Typ Max Unit V IH High level input voltage 2 0 Vee 0 3 V V IL Low level input voltage 0 3 0 8 V VOH High level TTL output voltage IOH 4...

Page 175: ...mum array clock period 20 25 30 ns fACNT Max internal array clock frequency See Note 5 50 40 33 3 MHz fMAX Maximum clock frequency See Note 7 62 5 50 40 MHz Internal Timing Parameters See Note 8 EPM5130 1 EPM5130 2 EPM5130 Symbol Parameter Conditions Min Max Min Max Min Max Unit tIN Input pad and buffer delay 5 7 9 ns tlO I O input pad and buffer delay 6 6 9 ns tEXP Expander array delay 12 14 20 n...

Page 176: ...for industrial use Vcc 5 V 10 Tc 55 C to 125 C for military use 5 Measured with a device programmed as a 16 bit counter in each LAB 6 This parameter is measured with a positive edge triggered clock at the register For negative edge clocking the tACH and tACL parameters must be swapped 7 The fMAX values represent the highest frequency for pipelined data 8 For information on internal timing paramete...

Page 177: ...0 58 I O 83 I O 9 INPUT 34 I O 59 INPUT 84 I O 10 INPUT 35 1 0 60 INPUT 85 I O 11 INPUT 36 I O 61 INPUT 86 I O 12 GND 37 GND 62 GND 87 GND 13 GND 38 GND 63 GND 88 GND 14 INPUT 39 I O 64 INPUT 89 I O 15 INPUT 40 1 0 65 INPUT 90 I O 16 INPUT elK 41 I O 66 INPUT 91 I O 17 INPUT 42 I O 67 INPUT 92 I O 18 vee 43 vee 68 vee 93 vee 19 vee 44 vee 69 vee 94 vee 20 INPUT 45 I O 70 INPUT 95 I O 21 INPUT 46 I...

Page 178: ...A8 INPUT C13 I O H12 GNO M9 INPUT A9 INPUT 01 1 0 H13 1 0 M10 1 0 A10 INPUT 02 1 0 J1 1 0 M11 1 0 A11 1 0 012 1 0 J2 1 0 M12 1 0 A12 1 0 013 1 0 J12 1 0 M13 1 0 A13 1 0 E1 1 0 J13 I O N1 I O B1 I O E2 I O K1 1 0 N2 I O B2 1 0 E12 I O K2 I O N3 I O B3 I O E13 I O K12 1 0 N4 INPUT 84 1 0 F1 1 0 K13 I O N5 INPUT B5 INPUT F2 GNO l1 1 0 N6 INPUT 86 VCC F3 GNO l2 I O N7 INPUT B7 INPUT F11 I O l6 GNO N8 ...

Page 179: ...ral Description Altera s EPMS192 EPLD is a user configurable high performance Multiple Array MatriX MAX SOOO family EPLD that provides high density replacement for 7400 series SSI and MSI TTL and CMOS logic Package pin out diagrams for the EPMS192 EPLD are shown in Figure 24 Figure 24 EPM5192 Package Pin Out Diagrams See Table 5 in this data sheet for QFP pin outs and Table 6 for PGA pin outs Pack...

Page 180: ... s Room Temp Q t5 200 IOH 100 2 3 4 5 V0 Output Voltage V 1 KHz 10 KHz 100 KHz 1 MHz 10 MHz 50 MHz Maximum Frequency The EPM5192 EPLD consists of 192 macrocells equally divided into 12 Logic Array Blocks LABs that each contain 16 macrocells and 32 expander pluduct lerms see figure 26 Becausc cuch Ll B is very compact high performance is maintained and device resources are used efficiently The EPM5...

Page 181: ...84 MACROCELL 85 MACROCELL 86 MACROCELL 87 MACROCELL 88 MACROCELLS 89 TO 96 Dedicated Inputs Global Clock Y F f Y r k Programmable Interconnect Arra PIA f Y 1 F V EPM5192 EPLD I INPUT 90 C6 84 INPUT 89 C7 83 INPUT 42 L7 44 INPUT 41 J7 43 LAB L MACROCELL 184 00 MACROCELL 183 MACROCELL 182 MACROCELL 181 MACROCELL 180 MACROCELL 179 MACROCELL 178 MACROCELL 177 MACROCELLS 185T0192 J LABK MACROCELL 164 0...

Page 182: ...erating temperature For commercial use 0 70 DC TA Operating temperature For industrial use 40 85 DC Te Case temperature For military use 55 125 DC tR Input rise time 100 ns tF Input fall time 100 ns DC Operating Conditions See Notes 2 3 4 Symbol Parameter Conditions Min Typ Max Unit V H Hiqh Ievel input voltage 2 0 Vee 0 3 V V L Low level input voltage 0 3 0 8 V VOH High level TIL output voltage I...

Page 183: ...m array clock period 20 25 30 ns f ACNT Max internal array clock frequency See Note 5 50 40 33 3 MHz f MAX Maximum clock frequency See Note 7 62 5 50 40 MHz Internal Timing Parameters See Note 8 EPM5192 1 EPM5192 2 EPM5192 Symbol Parameter Conditions Min Max Min Max Min Max Unit tIN Input pad and buffer delay 5 7 9 ns tlO I O input pad and buffer delay 6 6 9 ns tEXP Expander array delay 12 14 20 n...

Page 184: ...o 85 C for industrial use Vee 5 V 10 Tc 55 C to 125 C for military use 5 Measured with a device programmed as a 16 bit counter in each LAB 6 This parameter is measured with a positive edge triggered clock at the register For negative edge clocking the tACH and tACL parameters must be swapped 7 The fMAX values represent the highest frequency for pipelined data 8 For information on internal timing p...

Page 185: ...83 I O 9 I O 34 I O 59 I O 84 I O 10 I O 35 I O 60 I O 85 I O 11 I O 36 I O 61 I O 86 I O 12 GND 37 GND 62 GND 87 GND 13 GND 38 GND 63 GND 88 GND 14 I O 39 INPUT 64 I O 89 INPUT 15 I O 40 INPUT 65 I O 90 INPUT 16 I O 41 INPUT 66 I O 91 INPUT ClK 17 I O 42 INPUT 67 I O 92 INPUT 18 NC 43 VCC 68 NC 93 VCC 19 VCC 44 NC 69 VCC 94 NC 20 I O 45 I O 70 I O 95 I O 21 I O 46 I O 71 I O 96 I O 22 I O 47 I O ...

Page 186: ... A6 INPUT CLK C7 INPUT G3 I O K7 VCC A7 GNO C10 I O G9 I O K8 I O A8 I O C11 I O G10 GNO K9 I O A9 I O 01 I O G11 GNO K10 I O A10 I O 02 I O H1 I O K11 I O A11 I O 010 I O H2 I O L1 I O B1 I O 011 I O H10 I O L2 I O B2 I O E1 GNO H11 I O L3 I O B3 I O E2 GNO J1 I O L4 I O B4 I O E3 I O J2 I O L5 GNO B5 VCC E9 I O J5 I O L6 I O B6 I O E10 VCC J6 INPUT L7 INPUT B7 GNO E11 I O J7 INPUT L8 I O B8 I O ...

Page 187: ...Contents ISeptember 1991 Section 4 MAX 7000 EPLDs MAX 7000 EPLD Overview High Performance High Pin Count Devices 179 IAltera Corporation Page 1771 ...

Page 188: ......

Page 189: ...r I O intensive data path applications and 32 bit microprocessor support logic o Full software support for PC and workstation platforms including HP Apollo and Sun with Altera s MAX PLUS II software Hierarchical schematic capture with over 300 TTL and custom macrofunctions Altera Hardware Description Language AHDL for Boolean equation state machine and truth table design entry Waveform design entr...

Page 190: ..._ C lY Y l hl l uvvt a t l l l LU llL lV5 l L lU l lL 1 ly UVU lu V l Altera s MAX PLUS II development software fully exploits the density and flexibility of the MAX 7000 family MAX PLUS II Windows 3 0 based development software is a fully integrated package for designing logic with Altera s Classic MAX 5000 MAX 7000 and STG EPLDs The complete MAX PLUSII system provides anintuitive graphical inter...

Page 191: ...nt enhancements that deliver even more speed density and design flexibility The MAX 7000 architecture includes the following five basic elements o Logic array blocks o Macrocells o Logic expanders shared and parallel o Enhanced programmable interconnect array o I O control blocks Figure 2 MAX 7000 Block Diagram Enhanced macrocell provides efficient placement of logic for optimum speed and density ...

Page 192: ...hin that LAB Each LAB is fed by inputs from the PIA providing sufficient fan in for the 16 macrocells to implement a wide range of typical logic functions Ifmore inputs are needed for example in very wide data paths several LABs can be used in parallel Figure 3 Logic Array Block LAB Macrocells Macrocells within the LAB provide both sequential and combinatorial logic capability thus ensuring the mo...

Page 193: ...e logic array delay and minimizing control function delays The Clock Enable function allows flip flops to be controlled by the logic array even when they are clocked from the fast global Clock This feature facilitates the implementation of high speed synchronous designs The Clock Enable function also allows each macrocell register to be clocked individually Logic Expanders Whereas most logic can b...

Page 194: ...uct terms in the borrowing macrocell The ability to allocate additional product terms to any macrocell means that logic can be synthesized with the fewest logic resources at the fastest possible speed Programmable Interconnect Array The MAX 7000 enhanced PIA is a programmable wiring path between LABs that allows any signal source to reach any destination on the device Although it is fed by all mac...

Page 195: ...rs or even days to route typical MAX 7000 designs can be automatically routed in minutes Furthermore incremental additive delays between various points frequently up to 50 ns can cause debilitating skew and glitch problems in field programmable gate arrays FPGAs This unpredictable timing requires additional iterations of the design MAX 7000 EPLDs provide a single uniform delaybetween any signal so...

Page 196: ...Notes ...

Page 197: ...91 Section 5 STG SAM EPLDs STG SAM EPLDs Synchronous State Machine Waveform Generation Devices 189 EPS464 STG EPLD Synchronous Timing Generator 191 EPS448 SAM EPLD Stand Alone Microsequencer 205 IAltera Corporation Page 1871 ...

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Page 199: ...IAltera Corporation Page 1891 ...

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Page 201: ...s Complex state machines Multiple product term JK flip flops for waveform generation Phase comparator and clock oscillator functions o Programmable architecture that implements NTSC PAL and SECAM synchronization standards for TV and video applications o Available in 44 pin windowed ceramic and one time programmable OTP plastic J lead chip carrier and plastic QFP packages o MAX PLUSIIsoftware suppo...

Page 202: ...f the 64 internal flip flops can be programmed for D T JK or SR operation JK and SR flip flops are well suited for pattern generation applications since simple set and reset operations can be used to define the transitions of output waveforms Logic designs for the EPS464 EPLD are created with Altera s MAX PLUS II development system using any combination of graphic text and waveform design entry to...

Page 203: ...55 MACROCELL 23 MACROCELL 56 MACROCELL 24 r MACROCELL 57 MACROCELL 25 MACROCELL 58 MACROCELL 26 r MACROCELL 59 MACROCELL 27 r MACROCELL 60 MACROCELL 28 MACROCELL 61 MACROCELL 29 MACROCELL 62 MACROCELL 30 MACROCELL 63 MACROCELL 31 1 0 42 1 0 43 1 0 44 1 0 1 1 0 2 1 0 3 1 0 11 5 1 0 12 6 1 0 13 7 1 0 14 8 1 0 16 10 1 0 17 11 1 0 18 12 1 0 19 13 1 0 20 14 1 0 21 15 1 0 41 35 1 0 40 34 1 0 39 33 1 0 3...

Page 204: ... the fmIr Ll1p1 lt OF g ltei thp Clock Clear or Preset controls on the register the Output Enable controls on the I O pins or up to four expander product terms The product term select matrix can also connect Vee or GND to the control resources to permanently enable or disable logic functions The macrocell s register control functions Clock Clear and Preset can be driven from product terms or from ...

Page 205: ... switching noise offering quiet and reliable operation The EPS464 EPLD contains a programmable Security Bit that controls access to the data programmed into the device If this feature is used a proprietary design implemented in the device cannotbe copied or retrieved This feature provides a high level ofdesign security since data programmed in an EPROM cell is invisible The Security Bit that contr...

Page 206: ...gic Array Output Output Pin Clock Pin Clock into Logic Array Clock from Logic Array Data from Logic Array Register Output to Local LAB Logic Array Global Clock Pin Global Clock at Register Data from Logic Array Clock from Logic Array Data from Logic Array Output Pin 1 tExp 1 __________________ _ x Array Clock Mode tR 1 tAcH 1 tAcL 1 I V i l V J tF l l i _____ tLAc 1 V 1 1 x tRO __i 1 tFo l 1_ hR t...

Page 207: ...t measurements are performed under the conditions shown in Figure 6 Figure 6 AC Test Conditions Power supply transients can affectAC measurements Simultaneous transitions ofmultiple outputs should be avoided for accurate measurement Threshold tests must notbe performed underAC conditions Large amplitude fast ground current transients normally occuras the device outputs discharge the load capacitan...

Page 208: ...aining the NTSC macrofunction can be edited to fit a particular application or incorporated as a module within a larger design Four macrocells are used to implement a state machine that divides the pattern generation into distinct sections Each phase in the NTSC signal is represented by a different state The counters and state machine registers are decoded and connected to internal synchronous JK ...

Page 209: ...464 EPLD Synchronous Timing Generator I Figure 7 CCO Application Oscillator j _ _ _ 1 14 3 MHz 1 l __ C_S_Y_NC __ CP BLK Driver 3 58 SC 3 58 SC 90 I A tera Corporation Analog Block Video Out CCD Image Sensor Page 1991 ...

Page 210: ...ee V Vo Output voltage 0 Vee V TA Operating temperature For commercial use 0 70 C tR Input rise time 100 ns tF Input fall time 100 ns DC Operating Conditions See Notes 2 3 Symbol Parameter Conditions Min Typ Max Unit V IH High level input voltage 2 0 Vee 0 3 V VIL Low level input voltage 0 3 0 8 V VOH High level TTL output voltage 10H 4 mA DC 2 4 V VOL Low level output voltage 10L 4mADC 0 4 V i l ...

Page 211: ...CNT Max internal global clock frequency See Note 4 66 7 50 MHz tACNT Minimum array clock period 15 20 ns t ACNT Max internal array clock frequency See Note 4 66 7 50 MHz tMAX Maximum clock frequency See Note 5 71 4 50 MHz Internal Timing Parameters EPS464 20 EPS464 25 Symbol Parameter Conditions Min Max Min Max Unit tIN Input pad and buffer delay 5 6 ns tlO I O input pad and buffer delay 5 6 ns t ...

Page 212: ... the highest frequency for pipelined data Product Availability Operating Temperature Availability Commercial 0 C to 70 C EPS464 20 EPS464 25 Industrial 40 C to 85 C Consult factory Military 55 C to 125 C Consult factory Figure 8 shows the output drive characteristics for EPS464 I O pins and typical supply current vs frequency for the EPS464 EPLD Figure 8 EPS464 Output Drive Characteristics and Icc...

Page 213: ...ion Pin Function 1 I O 12 I O 23 I O 34 I O 2 I O 13 I O 24 GND 35 I O 3 I O 14 I O 25 I O 36 GND 4 GND 15 I O 26 I O 37 INPUT GCLK 5 I O 16 GND 27 I O 38 INPUT GPREn 6 I O 17 VCC 28 I O 39 INPUT GCLRn 7 I O 18 I O 29 VCC 40 INPUT GOEn 8 I O 19 I O 30 I O 41 VCC 9 VCC 20 I O 31 I O 42 I O 10 I O 21 I O 32 I O 43 I O 11 I O 22 I O 33 I O 44 I O Altera Corporation Page 203 ...

Page 214: ...Notes ...

Page 215: ... plastic J lead chip carriers OLCC and PLCC o Clock frequencies up to 30 MHz o High level support with SAM PLUS design tools includes Altera State Machine Input Language ASMILE Assembly Language ASM SAM Design Processor SDP and SAMSIM functional simulator The EPS448 EPLD is a function specific user configurable Stand Alone Microsequencer SAM It is available in a 28 pin windowed ceramic and OTP pla...

Page 216: ...ncluded PLS SAM is a software only package for existing Altera systems Ideal EPS448 applications include programmable sequence generators i e state machines bus and memorycontrol functions graphics and DSP algorithm controllers and other high performance control logic EPS448 devices can be cascaded horizontally for greater output capabilities and vertically for deeper microcode memory See Applicat...

Page 217: ...rs the high level Assembly Language ASM design entry format This language consists of powerful instructions Le opcodes that easily implement conditional branches subroutine calls multi level FOR NEXT loops and dispatch functions i e branching to an externally specified address For more information see Instruction Set later in this data sheet As shown in Figure 2 the EPS448 EPLD consists of microco...

Page 218: ...PROM and Pipeline Register The microcode EPROM is organized into 448 36 bit words each of which can be viewed as a single state location Each of the 36 bits is divided into the following categories F field 16 bits Q field 8 bits D field 8 bits OP field 3 bits E field 1 bit consists of user defined outputs at device pins provides the next state address is a general purpose field used either as a co...

Page 219: ...ounter the stack and the eight input pins The branch control logic is divided into two segments the address multiplexer and the branch select logic See Figure 4 Figure 4 Branch Control Logic Zero Flag Opcode from Counter 3 Q Field Next State Address 8 D Field 8 8 Top of Stack 8 Inputs 10 to 17 8 The address multiplexer provides the next state address to the microcode memory The next state address ...

Page 220: ...r regardless of the results of cond2 and condl If none of the conditions are met then microword 201 0 is clocked into the pipeline register The three conditional expressions are user defined They may contain any logical equation that is based on the inputs and can be reduced to four product terms as shown in the following example I1 12 I4 I3 14 IS I6 I7 10 12 I4 15 A unique set of 12 product terms...

Page 221: ...r from the counter Thus subroutines nested loops and other iterative structures maybe implemented efficiently The logic levels on the 8 dedicated input pins may also be pushed onto the stack to allow external address specification in a dispatch function or to externally load the counter See Figure 7 Figure 7 Stack from Dedicated Input 8 Pins D field or Counter to Counter or Microcode Memory The pu...

Page 222: ...is output enable capability allows EPS448 EPLDs tobevertically cascaded to increase the number of states The nRESET pin acts as a master reset for the EPS448 EPLD causing it to empty the stack clear the counter and load the microword at address 0 into the pipeline register The nRESET signal is useful for system reset or for synchronizing several EPS448 devices that are cascaded vertically or horiz...

Page 223: ... Clock Inputs Control N Outputs Clock N Inputs Control Outputs 2N The instruction set used to enter designs for the EPS448 EPLD consists of a compact assortment of powerful commands that allows efficient implementation of multiway branching subroutines nested FOR NEXT loops and dispatch functions These instructions are used only with Assembly Language ASM design entry Each command in the instructi...

Page 224: ...ruction 45 onto the stack and causes the next instruction to come from address 73 The RETURN instruction at address 75 returns the execution to address 45 The CALL command is typically used to call a subroutine RETURN This cc mm rLd causes the address of the next instruction to cO e fro _ the top of stackand pops thatvalue off the stack In this example the instruction at address 44 calls the subro...

Page 225: ...defaults to the next instruction in the ASM file In this example the instruction at address 44 is DECNZ GOTO labelA where labelA is located at address 73 The counter is decremented if it is not zero and the next instruction comes from address 73 DECNZ is typically used to conditionally decrement the counter PUSHLOADC constant GOTO labelA This instruction pushes the current value of the counter ont...

Page 226: ...fied variable To do so in this example address 73 would have a POPC instruction ANDPUSHI constant GOTO labelA This command pushes the eight inputs 17 to 10 onto the stack It is identical to the PUSHI GOTO labelA command except that the inputs are first bit wise ANDed with a constant to allow the masking of irrelevant inputs If the GOTO instruction is not included labelA defaults to the next instru...

Page 227: ...one Decrement PUSHLOADC Push CREG to stack and 10adCREG labelA CREG Constant POPC Pop stack to CREG labelA Pop Stack PUSH Push constant to stack labelA Push Hold PUSHI Push inputs to stack labelA Inputs Hold ANDPUSHI Push masked inputs to stack labelA Inputs ANDed Hold Constant POPXORC XOR stack with constant and send labelA Pop StackXoR result to CREG Constant Multiway Branching Multiway branchin...

Page 228: ...nteed through complete testing of each programmable EPROM bit and all internal logic elements thus ensuring 100 programming yield AC test measurements are performed under the conditions shown in Figure 11 Figure 11 EPS448 AC Test Conditions Power supply transients can affect AC measurements Simultaneous transitions of multiple outputs should be avoided for accurate measurement Threshold tests must...

Page 229: ...gure 13 shows EPS448 timing and reset timing waveforms Figure 13 EPS448 Switching Waveforms IfnRESET is held low for more than three clock edges then the outputs associated with the boot address 00 Hex will remain at the pins until the third clock after nRESET goes high IAltera Corporation Timing Waveforms _ tevc_ tF _tel _ teH J i_ t i i R Clock _ I i_tsu 1 i_ tH Input 10 to 17 X lid Input j X tt...

Page 230: ... Vo Output voltage 0 Vee V TA Operating temperature For commercial use 0 70 C TA Operating temperature For industrial use 40 85 C Te Case temperature For military use 55 125 C tR Input rise time 500 100 ns tF Input fall time 500 100 ns DC Operating Conditions See Notes 2 3 4 Symbol Parameter Conditions Min Typ Max Unit V IH High level input voltage 2 0 Vee 0 3 V V IL Low level input voltage 0 3 0 ...

Page 231: ...y undershoot to 2 0 V or overshoot to 7 0 V for periods less than 20 ns under no load conditions 2 Numbers in parentheses are for military and industrial temperature versions 3 Operating conditions Vee 5 V 5 TA 0 C to 70 C for commercial use Vee 5 V 10 TA 40 C to 85 C for industrial use Vee 5 V 10 Tc 55 C to 125 C for military use 4 Typical values are for TA 25 C Vee 5 V 5 For 1 0 VI 3 8 the nRESE...

Page 232: ...Notes ...

Page 233: ...Contents ISeptember 1991 Section 6 Micro Channel EPLDs Micro Channel EPLDs Altera User Configurable Micro Channel Interface 225 IAltera Corporation Page 223 I ...

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Page 235: ...OSbits o 8 prograJIlmable chip select outputs eUmirtatethe need for extra address decoder PLDsand gluelogic lCs o 24 Micro Qhannel address inputs support full address decoding from the Micro Channel bus o 24 mA current drive outputs eliminate extra bufferICs o Channel check interrupt support enables the board to use bus Non Maskable Interrupts for fast CPUinterrupt response o Optional28 pinEl B200...

Page 236: ......

Page 237: ...tember 1991 ection 7 MPLDs MPLDs Mask Programmed Logic Devices 229 MP1810 MPLD 235 MPM5032 MPLD 239 MPM5064 MPLD 243 MPM5128 MPLD 247 MPM5130 MPLD 251 MPM5192 MPLD 255 MPS464 MPLD 259 Altera Corporation Page 227 I ...

Page 238: ......

Page 239: ... Conversion process handled by Altera o Fast turn around to reduce time to market o Test vectors generated by Altera o Low power o N to 1 option combines multiple EPLDs into a single MPLD The Altera Mask Programmed Logic Devices MPLDs provide a masked alternative to EPLD designs By using a generic CMOS process and removing all EPROM cells Altera passes considerable savings on to customers who anti...

Page 240: ...PLUS II format The SNF reflects the final synthesis placement and routing of the original EPLD design The conversion process pays special attention to the wide fan in of product terms and the wide fan out of registers commonly found in EPLD applications An MPLD is guaranteed to meet the worst case timing parameters of the corresponding EPLD as specified in the EPLD data sheet Provided that the des...

Page 241: ...and timing analysis can be completed on the top level design The N to l option combines a multi EPLD design into a single MPLD that is function and timing compatible with the original multi EPLD solution The package and pin out are determined by the application s requirements A wide range of package options is available One of the principal objectives of Altera s EPLD to MPLD conversion program is...

Page 242: ...Conversion Design Flow Customer IPage232 Submit Design Packet Altera Final Design Sign Off Prototype Sign Off Data Sheet I Evaluation Review Conversion 5 weeks 6 weeks for N to 1 MPLDs Prototype Evaluation Production 10 to 12 weeks Altera Corporation I ...

Page 243: ...neration ATVG fault grading timing analysis place and route post route timing analysis design validation and the manufacture of the prototypes The entire conversion from final design sign off to prototype delivery takes less than 5 weeks 6 weeks for N to l conversion Production quantities are delivered 10 to 12 weeks D after the customer returns the Prototype Sign OffForm The two most importantdes...

Page 244: ...Notes ...

Page 245: ... carrier PLCC package Altera s MP1810 MPLD provides a high volume replacement for EP1810jEP1800 designs It is pin function and timing compatible with existing EP1810 jEP1800 designs MP1810 designs are created with Altera s MAX PLUS II or A PLUS development system and prototyped with EP1810 EPLDs The source files are then converted to produce the MPLD The MP1810 MPLD is available in a 68 pin PLCC p...

Page 246: ...Input rise time 50 ns tF Input fall time 50 ns DC Operating Conditions See Notes 2 3 Symbol Parameter Conditions Min Typ Max Unit V IH High level input voltage 2 0 Vee 0 3 V V IL Low level input voltage 0 3 0 8 V VOH High level TIL output voltage IOH 4 mA DC 2 4 V VOH High level CMOS output voltage IOH 2 mA DC 3 84 V VOL Low level output voltage IOL 4 mA DC 0 45 V II Input leakage current VI V ee ...

Page 247: ...ns tAH Array clock hold time 10 15 ns tAC01 Array clock to output delay C1 35 pF 25 35 ns tCNT Minimum global clock period 25 35 ns fCNT Maximum internal frequency See Note 4 40 28 6 MHz f MAX Maximum clock frequency See Note 5 50 40 MHz lJotes to tables 1 Minimum DC input is 0 3 V During transitions the inputs may undershoot to 2 0 V or overshoot to 7 0 V for periods shorter than 20 ns under no l...

Page 248: ... I Figure 4 shows typical supply current versus frequency for MP1810 MPLDs Figure 4 MP1810 Icc vs Frequency 25 20 c i Vee 5 0 V 15 Room Temp s CD U 10 2 5 o 10 20 30 40 50 Maximum Frequency MHz IPage238 A tera Corporation I ...

Page 249: ...ynthesis and full timing simulation Available in plastic 28 pin dual in line PDIP and J Iead chip carrier PLCC packages Altera s MPM5032 MPLD provides a high volume replacement for EPM5032 designs Itis pin function and timing compatible with existing EPM5032 designs MPM5032 designs are created withAltera s MAX PLUS or MAX PLUS II development system and prototyped with EPM5032 EPLDs The source file...

Page 250: ... voltage 0 Vee V TA Operating temperature For commercial use 0 70 C tR Input rise time 100 ns tF Input fall time 100 ns DC Operating Conditions See Notes 2 3 Symbol Parameter Conditions Min Typ Max Unit V IH High level input voltage 2 0 Vee 0 3 V V IL Low level input voltage 0 3 0 8 V VOH High level TTL output voltage 10H 4 mA DC 2 4 V VOL Low level output voltage IOJ 8 mA DC 0 45 V II Input leaka...

Page 251: ...nternal global clock frequency See Note 4 62 5 50 MHz tACNT Minimum array clock period 16 20 ns fACNT Max internal array clock frequency See Note 4 62 5 50 MHz fMAX Maximum clock frequency See Note 7 71 4 62 5 MHz Totes to tables L Minimum DC input is 0 3 V During transitions the inputs may undershoot to 2 0 V or overshoot to 7 0 V for periods shorter than 20 ns under no load conditions Typical va...

Page 252: ...ta Sheet Figure 6 shows typical supply current versus frequency for MPM5032 MPLDs Figure 6 MPM5032 Icc vs Frequency 28 24 ci 20 Vee 5 0 V 16 Room Temp E Q 12 U 8 4 o 10 20 30 40 50 60 70 Maximum Frequency MHz Altera Corporation ...

Page 253: ...ic J lead chip carrier package PLCC Altera s MPM5064 MPLD provides a high volume replacement for EPM5064 designs Itis pin function and timing compatible with existing EPM5064 designs MPM5064 designs are created with Altera s MAX PLUS or MAX PLUS II development system and prototyped with EPM5064 EPLDs The source files are then converted to produce the MPLD The MPM5064 MPLD is available in a 44 pin ...

Page 254: ...put voltage 0 Vee V TA Operating temperature For commercial use 0 70 C tR Input rise time 100 ns tF Input fall time 100 ns DC Operating Conditions See Notes 2 3 Symbol Parameter Conditions Min Typ Max Unit V H High level input voltage 2 0 Vee 0 3 V V L Low level input voltage 0 3 O S V VOH High level TTL output voltage IOH 4 mA DC 2 4 V VOL Low level output voltage 10L SmADC 0 45 V I Input leakage...

Page 255: ...0 25 30 ns fCNT Max internal global clock frequency See Note 4 50 40 33 3 MHz tACNT Minimum array clock period 20 25 30 ns f ACNT Max internal array clock frequency See Note 4 50 40 33 3 MHz f MAX Maximum clock frequency See Note 7 62 5 50 40 MHz otes to tables Minimum DC input is 0 3 V During transitions the inputs may undershoot to 2 0 V or overshoot to 7 0 V for periods shorter than 20 ns under...

Page 256: ...Data Sheet I Figure 8 shows typical supply current versus frequency for MPM5064 MPLDs Figure 8 MPM5064 Icc vs Frequency 45 ci 30 Vee 5 0 V Room Temp E Q t5 u 15 9 o 10 20 30 40 50 60 Maximum Frequency MHz Altera Corporation I ...

Page 257: ...rovides a high volume replacement for EPM5128 designs Itis pin function and timing compatible with existing EPM5128 designs MPM5128 designs are created with Altera s MAX PLUS or MAX PLUS II development system and prototyped with EPM5128 EPLDs The source files are then converted to produce the MPLD The MPM5128 MPLD is available in a 68 pin PLCC package See Figure 9 This data sheet provides minimum ...

Page 258: ...ut voltage 0 Vee V TA Operating temperature For commercial use 0 70 C tR Input rise time 100 ns tF Input fall time 100 ns DC Operating Conditions See Notes 2 3 Symbol Parameter Conditions Min Typ Max Unit V H High level input voltage 2 0 Vee 0 3 V V L Low level input voltage 0 3 O B V VOH High level TTL output voltage IOH 4 rnA DC 2 4 V VOL Low level output voltage IOL BmADC 0 45 V I Input leakage...

Page 259: ... 30 ns fCNT Max internal global clock frequency See Note 4 50 40 33 3 MHz tACNT Minimum array clock period 20 25 30 ns f ACNT Max internal array clock frequency See Note 4 50 40 33 3 MHz f MAX Maximum clock frequency See Note 7 62 5 50 40 MHz Votes to tables 1 Minimum DC input is 0 3 V During transitions the inputs may undershoot to 2 0 V or overshoot to 7 0 V for periods shorter than 20 ns under ...

Page 260: ...Data Sheet I Figure 10 shows typical supply current versus frequency for MPM5128 MPLDs Figure 10 MPM5128 Icc vs Frequency 90 ci F 60 Vee 5 0 V Room Temp g D 13 30 9 o 10 20 30 40 50 60 Maximum Frequency MHz Altera Corporation ...

Page 261: ... and timing compatible withexisting EPM5l30 designs MPM5l30 designs are created with Altera s MAX PLUS or MAX PLUS II development system and prototyped with EPM5l30 EPLDs The source files are then converted to produce the MPLD The MPM5l30 MPLD is available in 100 pinQFPand PCA packages See Figure 11 Figure 11 MPM5130 Package Pin Out Diagrams See Table 1in this data sheet for OFP pin outs Package o...

Page 262: ... 135 C T J Junction temperature Under bias 150 C Recommended Operating Conditions Symbol Parameter Conditions Min Max Unit vee Supply voltage 4 75 5 25 V VI Input voltage 0 Vee V Vo Output voltage 0 Vee V TA Operating temperature For commercial use 0 70 C tR Input rise time 100 ns tF Input fall time 100 ns DC Operating Conditions See Notes 2 3 Q _ I Parameter Co ditio s Min Typ Max Unit JIIiUVI V1...

Page 263: ...tACl Array clock low time 9 11 14 ns tCNT Minimum global clock period 20 25 30 ns fCNT Max internal global clock frequency See Note 4 50 40 33 3 MHz tACNT Minimum array clock period 20 25 30 ns fACNT Max internal array clock frequency See Note 4 50 40 33 3 MHz f MAX Maximum clock frequency See Note 7 62 5 50 40 MHz Notes to tables 1 Minimum DC input is 0 3 V During transitions the inputs may under...

Page 264: ...GND 83 1 0 4 1 0 24 1 0 44 vee 64 INPUT 84 1 0 5 1 0 25 1 0 45 1 0 65 INPUT 85 1 0 6 1 0 26 I O 46 1 0 66 INPUT 86 1 0 7 1 0 27 1 0 47 1 0 67 INPUT 87 GND 8 1 0 28 1 0 48 1 0 68 vee 88 GND 9 INPUT 29 1 0 49 1 0 69 vee 89 1 0 10 INPUT 30 1 0 50 1 0 70 INPUT 90 1 0 11 INPUT 31 1 0 51 1 0 71 INPUT 91 1 0 12 GND 32 1 0 52 1 0 72 INPUT 92 1 0 13 GND 33 1 0 53 1 0 73 1 0 93 vee 14 INPUT 34 1 0 54 1 0 74...

Page 265: ...ing compatible with existing EPM5l92 designs MPM5l92 designs are created with Altera s MAX PLUS or MAX PLUS II development system and prototyped with EPM5l92 EPLDs The source files are then converted to produce the MPLD The MPM5l92 is available in 84 pin PLCC and 100 pin QFP packages See Figure 13 This data sheet provides minimum and maximum AC and DC parametric values for the MPM5l92 MPLD For add...

Page 266: ...ut voltage 0 Vee V TA Operating temperature For commercial use 0 70 C tR Input rise time 100 ns tF Input fall time 100 ns DC Operating Conditions See Notes 2 3 Symbol Parameter Conditions Min Typ Max Unit V H High level input voltage 2 0 Vee 0 3 V V L Low level input voltage 0 3 0 8 V VOH High level TTL output voltage IOH 4 rnA DC 2 4 V VOL Low level output voltage IOL 8 rnA DC 0 45 V _ I Input le...

Page 267: ... 40 33 3 MHz tACNT Minimum array clock period 20 25 30 ns f ACNT Max internal array clock frequency See Note 4 50 40 33 3 MHz f MAX Maximum clock frequency See Note 7 62 5 50 40 MHz Notes to tables 1 Minimum DC input is 0 3 V During transitions the inputs may undershoot to 2 0 V or overshoot to 7 0 V for periods shorter than 20 ns under no load conditions 2 Typical values are for TA 25 C and Vcc 5...

Page 268: ...O 85 I O 6 I O 26 I O 46 I O 66 I O 86 I O 7 I O 27 I O 47 I O 67 I O 87 GND 8 I O 28 NC 48 I O 68 NC 88 GND 9 I 1 1 An Lie 69 lCC 89 PUT IV c v Tv 10 I O 30 NC 50 I O 70 I O 90 INPUT 11 I O 31 I O 51 I O 71 I O 91 INPUT ClK 12 GND 32 I O 52 NC 72 I O 92 INPUT 13 GND 33 I O 53 NC 73 I O 93 VCC 14 I O 34 I O 54 NC 74 I O 94 NC 15 I O 35 I O 55 I O 75 I O 95 I O 16 I O 36 I O 56 I O 76 I O 96 I O 17...

Page 269: ...tion and synthesis and full timing simulation o Available in 44 pin plastic J lead chip carrier PLCC package Altera s MPS464 MPLD provides a high volume replacement for EPS464 designs It is pin function and timing compatible with existing EPS464 designs MPS464 designs are created with Altera s MAX PLUS II development system and prototyped with EPS464 EPLDs The source files are then converted to pr...

Page 270: ...er bias 65 125 C Recommended Operating Conditions Symbol Parameter Conditions Min Max Unit vec Supply voltage 4 75 5 25 V VI Input voltage 0 Vee V Vo Output voltage 0 vce V TA Operating temperature For commercial use 0 70 C tR Input rise time 100 ns tF Input fall time 100 ns DC Operating Conditions See Notes 2 3 Symbol Parameter Conditions Min Typ Max Unit V IH High level input voltage 2 0 Vee 0 3...

Page 271: ...elay 20 25 ns tACH Array clock high time 7 10 ns t ACl Array clock low time 7 10 ns tCNT Minimum global clock period 15 20 ns fCNT Max internal global clock frequency See Note 4 66 7 50 MHz tACNT Minimum array clock period 15 20 ns f ACNT Max internal array clock frequency See Note 4 66 7 50 MHz f MAX Maximum clock frequency See Note 6 71 4 50 MHz rvotes to tables 1 Minimum DC input is 0 3 V Durin...

Page 272: ...ta Sheet Figure 16 shows typical supply current versus frequency for MPS464 MPLDs Figure 16 MPS464 Icc vs Frequency 50 40 ci Vee 5 0 V 30 Room Temp s Q t5 20 9 10 o 10 20 30 40 50 60 70 Maximum Frequency MHz Altera Corporation ...

Page 273: ...Contents ISeptember 1991 Section 8 Operating Requirements Operating Requirements for EPLDs 265 IAltera Corporation Page 263 I ...

Page 274: ......

Page 275: ...nconnected reserved Specific requirements are given in the EPLD pin out in the Report File utilization report for a design Each set of Vee and GND pins must be connected directly at the device with power supply decoupling capacitors of at least 0 21lF connected between them For effective decoupling each Vee pin must be separately decoupled to GND directly at the device Decoupling capacitors should...

Page 276: ...0 EP910A EP1810 EPS448 45 minutes EPM5016 EPM5032 EPM5064 EPM5128 1 hour EPM5130 EPM5192 EPB2001 EPS464 Altera EPLDs may be damaged by long term exposure to high intensity UV light Altera EPLDs may be erased and reprogrammed as often as necessary if the recommended erasure exposure levels are used EPLD input 1 0 and clockpins havebeen designed to resist the electrostatic discharge uSD duliLUgC und...

Page 277: ... SAM PLUS Programmable Logic Development System 315 PLS EDIF Bidirectional EDIF Netlist Interface to MAX PLUS Software 319 PLS WS HP MAX PLUS II Programmable Logic Development Software for HP Apollo Workstations 331 PLS WS SN MAX PLUS II Programmable Logic Development Software for Sun Workstations 341 Software Utility Programs 355 PL ASAP Altera Stand Alone Programmer 357 PL MPU EPLD Master Progra...

Page 278: ......

Page 279: ...fers hierarchical graphic text and waveform design entry Graphic Editor for schematic designs Text Editor for high level text descriptions Waveform Editor for design entry and editing viewing simulation inputs and results o The Altera Hardware Description Language AHDL supports state machines Boolean equations truth tables and arithmetic and relational operations o Applications run concurrently al...

Page 280: ... machines Figure 1 shows a block diagram of MAX PLUS II The PLDS HPS Development System includes MAX PLUS II software all hardware required to program Classic MAX 5000 MAX 7000 and STG EPLDs and sample devices PLS HPS PLS OS and PLS ES are software only packages See Package Contents later in this data sheet for more information MAX PLUS II supports three hierarchical design entry methods 1 schemat...

Page 281: ...splays timing results in the Waveform Editor With the Waveform Editor the user can enter modify and group input vectors view simulation errors and compare simulation runs MAX PLUS II system integration is superb The Compiler reports any design errors to the Message Processor which automatically highlights the source of an error in the Graphic Text or Waveform Editor MAX PLUS II is fully integrated...

Page 282: ...ow can display simulation results while the Text Editor shows an AHDL description At the same time the user can open two windows of the Graphic Editor that display different levels of a design s hierarchy or different areas of the same design file If one design is displayed in two windows of an editor any edits made in one window are automatically reflected in the other Graphic Symbol Editors The ...

Page 283: ...in Figure 3 AHDL is a high level modular language used to create logic designs for Altera EPLDs It provides design entry for state machines truth tables and Boolean equations The language syntax supports arithmetic and relational operations such as addition subtraction equality and magnitude comparisons Standard Boolean functions e g AND OR NAND NOR XOR and XNOR are also included Since AHDL suppor...

Page 284: ... analyzer that allows the designer to create simulation inputs and view simulation results Designs that generate timing signals are best described with waveforms Thc Compilcr s advanced vavefarm synthesis algorithms a1 t0m ti l1y generate logic from user defined input and output waveforms Registered and combinatorial logic as well as state machines can be described with waveforms The Compiler dete...

Page 285: ...les and MAX PLUS II then opens the appropriate editor to display the design This context sensitive feature makes it easy to move around the design hierarchy The Windows Clipboard is a temporary storage location that allows users to pass design information between editors Text from a Text Editor file can be copied into the Graphic Symbol and Waveform Editors or to another Text Editor file Schematic...

Page 286: ... 7410 7411 7420 7421 _ T TT 1 1 _1 _ _ ____ 1 T T TT7 fl fl __Ll J _L__C _ IVIAA l LU 11 nas a VUllL liL UIUlleLLlUlldl 1 Llll v V H L l lC L l llL 1 J U providing a convenient bridge to popular CAE schematic capture and simulation tools Any CAE software package that produces EDIF 2 0 0 netlists can export designs to MAX PLUS II with Library Mapping Files LMF that convert third party CAE functions...

Page 287: ... the Message Processor which can then locate them in the appropriate design file A successfully extracted design is built into a database and passed to the Logic Synthesizer The Logic Synthesizer module translates and optimizes the user defined logic for the target architecture The design is first minimized with SALSA Speedy Altera Logic SimplificationAlgorithm which removes any unused logic withi...

Page 288: ...tes a netlist from the compiled design if the user desires simulation or timing analysis data The EDIF Netlist Extractor optionally writes an EDIF 200 netlist that contains all post synthesis function and delayinformationfor the completed design so that it canbe integrated into a workstation environment Detailed specifications and test cases of Altera s EDIF output as well as simulation libraries ...

Page 289: ...st File 5NF extracted from a compiled design to perform timing simulation with O l ns resolution The user can specify commands either interactively or in a batch file to perform a variety of tasks such as halting the simulation when user defined conditions are met or forcing flip flops high or low If flip flop setup or hold times have been violated the Message Processor notifies the user of where ...

Page 290: ...verify examine blank check and test Classic MAX 5000 MAX 7000 and STG EPLDs The programming hardware includes an add on card for IBM PC AT PS 2 or compatibles that drives the Altera Master Programming Unit MPU For MAX 7000 EPLDs and selected high pin count devices the MPU supports functional testing so that vectors developed during simulation can be applied to the EPLD at programming time to verif...

Page 291: ...tion PLS OS The Open System is targeted for the user who already has third party CAE software for schematic capture and simulation It includes o Text Editor o AHDL o Bidirectional EDIF interface o Compiler support for all Altera Classic MAX 5000 MAX 7000 and STGEPLDs o Partitioner o Hierarchy Display and Message Processor o Programmer o Documentation PLS ES The Entry System is designed for the use...

Page 292: ...ace o 1 2 Mbyte 5 1 4 inch or 1 44 Mbyte 3 1 2 inch floppy disk drive o 2 or 3 button mouse compatible with Microsoft Windows 3 0 o Full length 8 bit slot for programming card o Parallel port Recommended System Configuration o 33 MHz 386 or 486 based IBM PC AT computer or compatible o 8 Mbytes of memory o DOS version 3 3 or higher o Microsoft Windows version 3 0 or higher o 12 ms seek time hard dr...

Page 293: ... AHDL for state machines Booleanequations truth tables arithmetic and relational operations Delay prediction and timing analysis for graphic and text designs o Logic synthesis and minimization for quick and efficient processing o Compiles a 100 utilized EPM5128 in only 10 minutes o Automatic error location for schematics and AHDL text files o Interactive Simulator with probe assignments for intern...

Page 294: ...upports hierarchical entry of both Graphic Design Files GDF with thE MAX PLUS Graphic Editor and Text Design Files TDF in the Altere Hardware Description Language AHDL with the MAX PLUSTextEditor The Graphic Editor offers advanced features such as multiple hierarch levels symbol editing and an extensive library of 7400 series TTl macrofunctions and basic SSI gates AHDL designs can be mixed into an...

Page 295: ...erification and programming MAX PLUS offers both graphic and text design entry methods GDFs are entered with the MAX PLUS Graphic Editor Boolean equations state machines and truth tables are entered in the Altera Hardware Description Language AHDL with the MAX PLUS Text Editor The ability to freely mix graphic and text files at all levels of the design hierarchy and to use a top down or bottom up ...

Page 296: ...acrotunctions that are optimized for MAX 5000 architecture In addition the designer can create custom functions that can be used in any MAX PLUS design Tag and drag editing is used to move individual symbols or entire areas Lines remain connected with orthogonal rubberbanding Designs are printed on an Epson FX compatible printer HP7475A 7485B and 7495A plotters or a Houston Instruments 695 compati...

Page 297: ...ETURNS CO 5UD DESI9N IS tseradd DEVICE IS EPM5032 SUBDESION tseradd datainx datalny c1oel cl ar oin oout VARIABLE CArry i LL11 NODE t uI1add INPUT INPUT INPUT OUTPUT r Input eri 1 hlt to be added X v 1ld on rising edge c10ck r clear should h A_ _rt d h or r ir t hlt are c10ckad In r X oontains the ourrent values Yo oarry in carry out serial su X h01d current CArry st tu X X in tanca oi macrot unct...

Page 298: ...add_cmp DEVICE IS EPM5128 2 FUNCTION 74161 LDN A B C D ENT ENP CLRN CLK RETURNS QA QB QC QD RCO SUBDESIGN add_cmp a 7 0 inputs for adder comparator VARIABLE b 7 0 cmpen clock reset INPUT result 7 0 elapse 3 0 equal less_than grtr_than done OUTPUTj timer register 7 0 flag 74161 timer is 74161 counter DFF register is an octal FF NODE BEGIN 9 j 11 rlrrl1mlllrlj p rpgister result register register clr...

Page 299: ...OMP 7485 74518 74684 74686 74688 Code Converter 74184 74185 Counter 4COUNT 8COUNT 16CUD8LR GRAY4 UNICNT 7493 74160 74161 74162 74163 74190 74191 74192 74193 74393 Decoder 7442 7443 7444 7445 7446 7447 7448 7449 74138 74139 74154 74155 74156 Encoder 74147 74148 Frequency Divider FREQDIV 7456 7457 Latch INPLTCH NANDLTCH NORLTCH 7475 7477 74116 74259 74279 74373 Multiplier MULT2 MULT4 MULT24 74261 Mu...

Page 300: ...Hierarchy Interconnect File HIF that describes the hierarchy of the total design This information is used by the Database Builder which flattens the hierarchical design examines design logic and checks for schematic boundary connectivity and syntax errors The Logic Synthesizer module translates and optimizes the user defined logic for the MAX 5000 architecture The design is first minimized with SA...

Page 301: ...nder product terms in an EPM5128 take only 10 minutes to compile on a 20 MHz 386 based PC The MAX PLUS II Simulator Timing Analyzer and Waveform Editor allow the designer to test the logic of a compiled project Simulator The Simulator uses the Simulator Netlist File SNF extracted from the compiled design to perform timing simulation with O l ns resolution Simulator commands are provided to halt th...

Page 302: ...y blocks of v v aveforrr1s For exallLple all or pu rt of u waveform can be compressed to simulate an increase in clock frequency The Waveform Editor can also compare and highlight the differences between two different simulations A user can simulate a deSign observe and edit the results and then resimulate the design the Waveform Editor can then show the results superimposed on each other to highl...

Page 303: ...ese reports can be highlighted in a GDF The MTA calculates timing delays between multiple source and destination nodes and creates a connection matrix that gives the shortest and longest delay paths between all specified source and destination nodes Figure 7 The MTA also displays the detailed paths and delays between specified sources and destinations Figure 7 Timing Analysis Matrix MAX PLUS Timin...

Page 304: ...how the high level description has been synthesized and placed into the MAX 5000 architecture SNF2GDF uses the SNF s delay and connection information to create a series of schematics that are fully annotated with propagation delay and setup and hold time information at each logic gate regardless of whether the original design was created in a schematic with AHDL or with another design entry method...

Page 305: ...Data Sheet PLDS MAX PLS MAX I Figure 8 Original Schematic File H LI tLASHENA _ 7 Figure 9 Schematic Converted and Annotated with SNF2GDF TURN 2N21 Altera Corporation Page29s1 ...

Page 306: ... o Programming card LP6 for IBM PC AT or compatible LP5 for IBM PS 2 Model 50 or higher or compatible o Programming adapters PLED5016 PLED5032 PLEJ5064 PLEJ5128 o Sample EPLDs PLS MAX The complete MAX PLUS software includes o Graphic Symbol and Text Editors o AHDL o MAX PLUS TTL MacroFunction Library o Compiler support for all Altera MAX 5000 EPLDs o Simulator o Waveform Editor o Timing Analyzer M...

Page 307: ...t mouse or 2 button Microsoft compatible serial port or bus mouse plus a serial port for a serial port mouse o Full length 8 bit slot for programming card o Parallel port Recommended System Configuration o 33 MHz 386 or 486 based IBM PC AT PS 2 Model 70 or higher or compatible computer o DOS version 3 3 or higher o 640 Kbytes of memory o 2 Mbytes of expanded memory with LIM 3 2 compatible driver o...

Page 308: ...Notes ...

Page 309: ...rt for user defined macrofunctions with ADLIB software o Fast and efficient design processing to ensure rapid design cycles Elimination of unused gates Automatic pin and part assignments SALSA logic minimization Device Fitter to optimize Classic EPLD resources o Functional simulation for quick design verification Easy definition of inputs with state tables vector patterns or predefined patterns St...

Page 310: ...rd JEDEC File JED for EPLD programming The ADP implements logic minimization automatic EPLD selection architecture optimization and fitting The ADP also produces documentation that shows minimized logic and EPLD utilization A PLUS also includes a Functional Simulator FSIM to verify designs and LogicMap II software to program EPLDs A PLUS runs on an IBM PC AT PS 2 or compatible computer and offers ...

Page 311: ...ltera Design Librarian ADLIB which allows custom development of new macrofunction elements Table 1 Partial List ofA PLUS Macrofunctions Type Macrofunctions Adder 7480 7482 7483 74183 8FADD Comparator 7485 74158 74518 8MCOMP Converter 74184 74185 Counter 7493 74160 74161 74162 74163 74190 74191 74393 74160T 74161T 74162T 74163T 74190T 74191T 74192T 74193T 8COUNT 4COUNT 16CUDSLR UNICNT2 GRAY4 Decode...

Page 312: ...h LogiCaps l 1li II3II SId i 1e iI 2 I 71185 I V CD 7 I II 0 Line n 1e1 e Boolean Equation Entry The ADF syntax supports Boolean equation design entry and features free form entry of all syntactical elements Boolean equations need not be entered with a minimized sum of products form because the ADP automatically minimizes the equations before generating the JEDEC File JED for programming An ADF is...

Page 313: ... The Altera Design Processor ADP consists of a series of modules that automatically transforms the design into a JEDEC File JED used to program the EPLD First the Flattener module flattens the high level macrofunctions to low level gate primitives Next the ADP analyzes the complete logic circuit and removes unused gates and flip flops This MacroMunching feature enables the designer to freely use m...

Page 314: ... the Fitter generates a Utilization Report RPT that documents macrocell and pin assignments input and output pin names and buried registers as well as any unused resources At the end of design processing the Assembler module generates an industry standard JEOEC programming file The Functional Simulator FSIM is a convenient and easy to use tool for testing design logic before it is committed to sil...

Page 315: ... read the contents of a Classic device and use this information to program additional EPLDs Data I O and several other third party manufacturers also provide programming support for Altera EPLDs PLeAD SUPREME The complete A PLUS development system includes both hardware and software o LogiCaps schematic capture o Boolean equation netlist state machine and truth table design entry o Altera Design P...

Page 316: ...tible computer o DOS version 3 1 or higher o 640 Kbytes of memory o 20 Mbytes free disk space o VGA or EGA graphics display o 1 2 Mbyte 5 1 4 inch or 1 44 Mbyte 3 1 2 inch floppy disk drive o 3 button serial port mouse or 2 button Microsoft compatible serial port or bus mouse plus a serial port for a serial port mouse o Full length 8 bit slot for programming card o Parallel port Recommended System...

Page 317: ...al simulator with Virtual Logic Analyzer VLA user interface o Disassembler to examine assembly code during simulation o Full support for horizontal cascading of multiple EPS448 EPLDs o Device programming with LogicMap II software and Altera programming hardware o Runs on IBM PC AT PS 2 and compatible computers SAM PLUS provides a complete software solution for implementing state machine and microc...

Page 318: ...n either the Altera State Machine Input Language ASMILE or the Altera Assembly Language ASM A standard text editor is used to create the input file with either method If ASMILE is used the State Machine File 5MF is processed by a converter to produce an ASM file The various modules of the SDP then process the ASM file The SDP produces three outputs a JEDEC File used to simulate and program the EPS...

Page 319: ...ny standard text editor to create a file describing a state machine The State Machine File to Assembly Language File SMF2ASM Converter translates the SMF into an equivalent ASM file before sending it to the SDP ASMILE provides a simple yet comprehensive means of converting a conceptual state diagram into a simple text description Figure 2 shows the state diagram for a 68020 bus arbiter Each circle...

Page 320: ...ITER CLOCK CLK The state table defines the outputs for each state STATES GRANT TRISTATE SO 0 0 S1 1 1 S2 1 1 S3 1 1 S4 1 1 S5 0 1 S6 0 1 Transition specifications SO IF REQUEST ACK THEN S1 IF ACK THEN S5 SO S1 S2 S2 IF REQUEST ACK ACK THEN S6 S2 IMPLIED ELSE S3 IF REQUEST THEN S6 IF REQUEST ACK THEN S2 S3 S4 S3 S5 IF REQUEST ACK THEN SO IF REQUEST THEN S4 S5 S6 S5 END Direct ASM design entry is al...

Page 321: ...S6 Figure 4 Assembly Language File DESIGNER NAME COMPANY NAME 9 1 91 68020 Bus Arbitration Controller for EPS448 SAM EPLD PART EPS448 INPUTS REQUEST ACK OUTPUTS GRANT TRISTATE MACROS GOTOSO 00 JUMP SO GOTOSl 11 JUMP Sl GOTOS2 11 JUMP S2 GOTOS3 11 JUMP S3 GOTOS4 11 JUMP S4 GOTOS5 01 JUMP S5 GOTOS6 01 JUMP S6 PROGRAM BUSARBITER CLK OD GOTOSOj SO IF REQUEST ACK THEN GOTOSlj ELSEIF ACK THEN GOTOS5j EL...

Page 322: ...lyzer VLA displays the input and outputwaveforms interactively providing multiple zoom levels split screens and differential time displays see Figure 5 The internal state of the EPS448 EPLD including the stack and counter can be examined and modified An online disassembler can convert the actual object code back into the original ASM source code Figure 5 Virtual Logic Analyzer 1 1 REQUEST AC GRANT...

Page 323: ... system includes both hardware and software o Altera State Machine Language ASMILE o Assembly Language ASM o SAM Design Processor SDP o Functional Simulator SAMSIM o Disassembler o Virtual Logic Analyzer VLA o LogicMap II programming software o Documentation o Master Programming Unit MPU o Programming card LP6 for IBM PC AT or compatible LPS for IBM PS 2 Model SO or higher or compatible o Programm...

Page 324: ...h or 1 44 Mbyte 3 1 2 inch floppy disk drive o Full length 8 bit slot for programming card o Parallel port Recommended System Configuration o 20 MHz or higher 386 based PC AT computer PS 2 Model 70 or higher or compatible computer o DOS version 3 3 or higher o 640 Kbytes of memory o 20 Mbytes free disk space o VGA graphics display o 1 2 Mbyte 5 1 4 inch or 1 44 Mbyte 3 1 2 inch floppy disk drive o...

Page 325: ...amming Unit MPU Programming adapters PLED5016 PLEJ5128 PLED5032 PLED610 PLEJ5064 PLED910 Sample EPLDs for evaluation PLEJ1810 PLED448 PLDS ENCORE supports design entry logic optimization design verification and design programming for all Classic MAX 5000 and SAM EPLDs MAX 5000 Multiple Array MatriX EPLD designs are implemented with PLS MAX MAX PLUS Programmable Logic Software Designs can be entere...

Page 326: ...nctional Simulator and LogicMap II software The PLDS ENCORE Development System includes all necessar hardware a Logic Programmer card Master Programming Unit and c range of programming adapters to program Classic MAX 5000 anc SAM EPLDs at the designer s desktop Individual PLDS ENCORE components can be purchased separately However PLDS ENCORE provides a full range ofEPLD logic developmenl support a...

Page 327: ...e 3 1 2 inch floppy disk drive o 3 button serial port mouse or 2 button Microsoft compatible serial port or bus mouse plus a serial port for a serial port mouse o Full length 8 bit slot for programming card o Parallel port Recommended System Configuration o 33 MHz 386 or 486 based IBM PC AT PS 2 Model 70 or higher or compatible computer o DOS version 3 3 or higher o 640 Kbytes of memory o 2 Mbytes...

Page 328: ...Notes ...

Page 329: ... TTL functions from Mentor Graphics Valid Logic and Viewlogic CAE tools to equivalent MAX PLUS functions o Altera EDIF netlist writer produces post synthesis logic and delay information used during device or board level simulation with popular CAE tools o PLS EDIF runs on IBM PC AT PS 2 or compatible computers The Altera PLS EDIF toolkit is a bidirectional EDIF netlist interface between PC or work...

Page 330: ... third party programming hardware EDIF netlists can be exported from MAX PLUS with the Altera EDIT Netlist Writer SNF2EDF Converter This EDIF Netlist Writer generate an EDIF output file from a compiled MAX PLUS design The EDIF filE contains the post synthesis information used byCAE simulators to perform device or board level simulation PLS EDIF provides an open environment that allows designers to...

Page 331: ... of platforms and software packages For example a third party workstation CAE schematic converted with the EDIF Netlist Reader may be combined with an Altera Hardware Description Language AHDL state machine in MAX PLUS Designers can choose the entry methods and platforms that best meet their needs LMFs are used with the Altera EDIF Netlist Reader to convert functions of third party CAE tools to eq...

Page 332: ...00 higher o EDIFNET Mentor Graphics EDIF netlist writer version 7 0_2 5 0 higher Table 1 lists the Mentor Graphics basic functions that are mapped tc MAX PLUS compatible functions Table 1 Mentor Graphics Library Mapping File Basic Functions Mentor Graphics Function MAX PLUS Compatible Function AND AND 2 3 4 5 6 BUF SCLK DELAY MCELL DFF DFF2 INV NOT JKFF JKFF2 LATCH MLATCH NAND NAND 2 3 4 5 6 9 NOR...

Page 333: ...twriter version 1 1 SUN4 P1 or higher Table 2 lists the Valid Logic basic functions that are mapped to MAX PLUS compatible functions Table 2 Valid Logic Library Mapping File BasiC Functions Valid Logic Function MAX PLUS Compatible Function INV EXP LSOO NAN02 LS02 NOR2 LS04 NOT LS08 AN02 LS10 NAN03 LS11 AN03 LS20 NAND4 LS21 AN04 LS27 NOR3 LS28 NOR2 LS30 NAN08 LS32 OR2 LS37 NAN02 LS40 NAN04 LS74 OFF...

Page 334: ...iewlogic Library Mapping File BUlLT IN Functions Viewlogic Function MAX PLUS Compatible Function AND AND 2 3 4 8 ANDNOR22 2A2NOR2 BUF SOFT DAND DAND 2 3 4 8 DELAY MCELL DOR DOR 2 3 4 8 DXOR DXOR 2 3 4 8 JKFFRE JKFFRE MUX41 MUX41 NAND NAND 2 3 4 8 NOR NOR 2 3 4 8 NOT NOT OR OR 2 3 4 8 TRIAND TAND 2 3 4 8 TRIBUF TRIBUF TRINAND TNAND 2 3 4 8 TRINOR TNOR 2 3 4 8 TRINOT TRINOT TRIOR TOR 2 3 4 8 UBDEC38...

Page 335: ...4LS10 LS10 74LS10 7411 74LS11 LS11 74LS11 7420 74LS20 LS20 74LS20 7421 74LS21 LS21 74LS21 7427 74LS27 LS27 74LS27 7428 74LS28 LS28 74LS28 7430 74LS30 LS30 74LS30 7432 74LS32 LS32 74LS32 7437 74LS37 LS37 74LS37 7440 74LS40 LS40 74LS40 7442 74LS42 LS42 74LS42 7451 74LS51 LS51 74LS51 7454 74LS54 LS54 74LS54 7455 74LS55 LS55 74LS55 7473 74LS73A LS73 74LS73A 7474 74LS74A LS74 74LS74A 7475 74LS75 LS75 7...

Page 336: ...74163 74LS163A LS163 74LS163A 74164 74LS164 LS164 74LS164 74165 74LS165 LS165 74LS165 74166 74LS166 LS166 74LS166 74168 74LS168A 74169 74LS169A LS169 74LS169 74173 74LS173A LS173 74LS173A 74174 74LS174 LS174 74LS174 74175 74LS175 LS175 74LS175 74181 74LS181 LS181 74LS181 74183 74LS183 LS183 74LS183 74190 74LS190 LS190 74LS190 74191 74LS191 LS191 74LS191 74192 74LS192 LS192 74LS192 74193 74LS193 LS...

Page 337: ...366 74LS366A LS366 74LS366A 74367 74LS367A LS367 74LS367A 74368 74LS368A LS368 74LS368A 74373 74LS373 LS373 74LS373 74374 74LS374 LS374 74LS374 74377 74LS377 LS377 74LS377 74379 74LS379 LS379 74LS379 74381 74LS381 LS381 74LS381 74390 74LS390 LS390 74LS390 74393 74LS393 LS393 74LS393 Note Contact Altera Applications for the most up to date list of mappings Designers can map their commonly used thir...

Page 338: ...gn an equivalent circuit with the MAX PLUS Graphic Editor ANDZ C T I 1 _ _ 1 ANDZ NOR3 i ANDZ Step 3 Map the third party function to the MAX PLUS function in an LMF User Library Mapping File BEGIN FUNCTION ALTR_A05 A_IN B_IN C_IN REWRNS Z_OUT FUNCTION A05 A B C RETURNS Z END Data Sheet IPage 328 Altera Corporation ...

Page 339: ...or changes the EDIF level or keyword level See Figure 4 Figure 4 Altera EDIFNetlist Writer MAX PLUS Compiler Optional Command EDC File MAX PLUS CFG Configuration File The EDIF output file may have one of two formats The first format expresses all delays with special EDIF property constructs The second expresses combinatorial delays with port delay constructs and registered delays with path delay c...

Page 340: ...ystems libraries Sample files o Documentation PLS EDIF IBM PC AT PS 2 or compatible o IBM PC AT PS 2 Model 50 or higher or compatible computer o DOS version 3 1 or higher o 640 Kbytes of memory o 1 Mbyte of expanded memory with version 3 2 or higher of Lotus Intel Microsoft LIM Expanded Memory Specification o VGA or EGA display o 20 Mbyte free disk space o 1 2 Mbyte 5 1 4 inch or l 44 Mbyte 3 1 2 ...

Page 341: ...ltiple EPLDs o Generates post synthesis timing simulation data for use with Logic Automation s SmartModels and MentorGraphics QuickSim simulator o Produces EPLD programming files for use with an Altera PC based programmer PL ASAP or third party programming hardware The Altera PLS WS HP package brings the MAX PLUS II development software to HP Apollo Series 3000 3500 4000 4500 and HP400 workstation...

Page 342: ...gn Files td created in AHDL can be used separately or mixed with NETED schemati designs NETED schematics are converted into EDIF 2 0 0 netlist files with th Mentor Graphics EDIFNET netlist writer The MAX PLUS II Compile automatically processes these EDIF Input Files edf when the design h compiled see Figure 2 In addition symbols from the Mentor Graphic generic and LSTTL libraries can be mapped to ...

Page 343: ...R XOR2 XOR Note Contact Altera Applications for the most up to date list of mappings Table 2 Mentor Graphics Library Mapping File Macrofunctions Part 1of3 Mentor Graphics 74LSTTL Function MAX PLUS II TTL Macrofunction 74LSOO 7400 74LS02 7402 74LS04 7404 74LS08 7408 74LS10 7410 74LS11 7411 74LS20 7420 74LS21 7421 74LS27 7427 74LS28 7428 74LS30 7430 74LS32 7432 74LS37 7437 74LS40 7440 74LS42 7442 74...

Page 344: ...96 7496 74LS107A 74107 74LS109A 74109 74LS112A 74112 74LS113A 74113 74LS114A 74114 74LS133 74133 74LS138 74138 74LS139A 74139 74LS147 74147 74LS148 74148 74LS151 74151 74LS153 74153 74LS154 74154 74LS155A 74155 74LS156 74156 74LS157 74157 74LS158 74158 74LS160A 74160 74LS161A 74161 74LS162A 74162 74LS163A 74163 74LS164 74164 74LS165 74165 74LS166 74166 74LS168A 74168 74LS169A 74169 74LS173A 74173 ...

Page 345: ... 74LS241 74241 74LS244 74244 74LS251 74251 74LS253 74253 74LS257 74257 74LS258A 74258 74LS260 74260 74LS273 74273 74LS279 74279 74LS280 74280 74LS283 74283 74LS290 74290 74LS293 74293 74LS299 74299 74LS348 74348 74LS353 74353 74LS365A 74365 74LS366A 74366 74LS367A 74367 74LS368A 74368 74LS373 74373 74LS374 74374 74LS377 74377 74LS379 74379 74LS381 74381 74LS390 74390 74LS393 74393 Note Contact Alt...

Page 346: ...o thE MAX PLUS II function in an LMF Figure 3 Creating an LMFMapping Step 1 Select a Mentor Graphics function for mapping A I B J J z I c Step 2 Design an equivalent circuit in AHDL if no equivalent function exists in the MAX PLUS II TTL MacroFunction Library TITLE ALTR_AOS DESIGN IS ALTR_A05 SUBDESIGN ALTR_A05 A_IN B_IN C_IN INPUT Z_OUT OUTPUT VARIABLE Xl X2 X3 NODE BEGIN Lj_UU l xl xL X3 Xl A_IN...

Page 347: ...cluding AND OR NAND NOR XOR and XNOR TITLE Timed Add and Compare Function DESIGN IS add_cmp DEVICE IS EPM5128 2 FUNCTION 74161 LDN A B C D ENT ENP CLRN CLK RETURNS QA QB QC QD RCO SUBDESIGN add_cmp VARIABLE BEGIN a 7 0 b 7 0 cmpen clock reset result 7 0 elapse 3 0 equal less_than grtr_than done inputs for adder comparator INPUT OUTPUT timer register 7 0 flag 74161 timer is 74161 counter DFF regist...

Page 348: ...ther options specify the degree of detail of the Report File rpt that shows how EPLDs have been utilized and the target EPLD family for the design The first module of the Compiler the Compiler Netlist Extractor extracts the netlist used to define the design from the EDIF Input Files ed and AHDL Text Design Files tdf At this time design rules are checked for any errors Iferrors are found they are d...

Page 349: ...information This SNF is used by the EDIF Netlist Extractor to create EDIF Output Files edo The EDIF Netlist Extractor optionally writes an EDIF 2 0 0 netlist that contains all post synthesis function and delay informationfor the completed design so that it can be integrated into the workstation environment An EDIF Output File is created for each device used in the design An Altera provided or user...

Page 350: ...upports MAX 5000 EPLDs is available now MAX PLUS II software that supports Classic MAX 5000 MAX 7000 and STG EPLDs will be available in February 1992 o HP Apollo Series 3000 3500 4000 4500 or HP400 workstation with 20 Mbytes of free disk space o Domain OS SR 10 1 or 10 3 operating system o Quarter inch cartridge QIC 24 9 track 60 Mbyte tape drive o Schematic capture and EDIF conversion software Me...

Page 351: ...th the Valid Logic RapidSIM or Viewlogic Viewsim chip and board level simulators or with Logic Automation s SmartModels o Produces EPLD programming files for use with an Altera PC based programmer PL ASAP or third party programming hardware The Altera PLS WS SN package brings the MAX PLUS II development software to Sun Microsystems SPARCstations see Figure 1 PLS WS SN includes Altera Hardware Desc...

Page 352: ...dGED by Valid Logic or with Viewdraw by Viewlogic see Figure 2 Hierarchical Text Design Files tdf are created in AHDL and can be used separately or mixed with schematic designs Valid Logic EDIF ValidGED schematics are converted into EDIF 200 netlist files with the Valid Logic WEDIFNET netlist writer The MAX PLUS II Compiler automatically processes these EDIF Input Files ed when the design is Figur...

Page 353: ... AND3 LS20 NAN04 LS21 AND4 LS27 NOR3 LS28 NOR2 LS30 NAN08 LS32 OR2 LS37 NAN02 LS40 NAN04 LS74 DFF2 LS86 XOR LS126 TRI LS386 XOR Note Contact Altera Applications for the most up to date list of mappings Viewlogic EDIF Viewdraw schematics are converted into EDIF 2 0 0 netlist files with Viewlogic s EDIFNETO netlist writer The MAX PLUS II Compiler automatically processes these EDIF Input Files edf wh...

Page 354: ...DOR 2 3 4 8 DXOR DXOR 2 3 4 8 JKFFRE JKFFRE MUX41 MUX41 NAND NAND 2 3 4 8 NOR NOR 2 3 4 8 NOT NOT OR OR 2 3 4 8 TRIAND TAND 2 3 4 8 TRIBUF TRIBUF TRINAND TNAND 2 3 4 8 TRINOR TNOR 2 3 4 8 TRINOT TRINOT TRIOR TOR 2 3 4 8 UBDEC38 DEC38 UDFDL UDFDL UJKFF UJKFF XNOR2 XNOR XNOR XNOR 3 4 8 XOR2 XOR XOR XOR 3 4 8 Note Contact AHera Applications for the most up to date list of mappings IPage344 Altera Cor...

Page 355: ...0 LS32 74LS32 7432 LS37 74LS37 7437 LS40 74LS40 7440 LS42 74LS42 7442 LS51 74LS51 7451 LS54 74LS54 7454 LS55 74LS55 7455 LS73 74LS73A 7473 LS74 74LS74A 7474 LS75 74LS75 7475 LS76 74LS76A 7476 74LS77 7477 LS78 74LS78A 7478 LS83 74LS83A 7483 LS85 74LS85 7485 LS86 74LS86 7486 LS90 74LS90 7490 LS91 74LS91 7491 LS92 74LS92 7492 LS93 74LS93 7493 LS95 74LS95B 7495 LS96 74LS96 7496 LS107 74LS107A 74107 LS...

Page 356: ...2 LS163 74LS163A 74163 LS164 74LS164 74164 LS165 74LS165 74165 LS166 74LS166 74166 LS169 74LS169 74169 LS173 74LS173A 74173 LS174 74LS174 74174 LS175 74LS175 74175 LS181 74LS181 74181 LS183 74LS183 74183 LS190 74LS190 74190 LS191 74LS191 74191 LS192 74LS192 74192 LS193 74LS193 74193 LS194A 74LS194A 74194 LS195 74LS195A 74195 LS196 74LS196A 74196 LS197 74LS197 74197 LS240 74LS240 74240 LS241 74LS24...

Page 357: ...LS377 74LS377 74377 LS379 74LS379 74379 LS381 74LS381 74381 LS390 74LS390 74390 LS393 74LS393 74393 Note Contact Altera Applications for the most up to date list of mappings Designers can add to the Altera provided LMFs or create a new LMF To create a new mapping between a Valid Logic or Viewlogic symbol and a MAX PLUS II primitive or macrofunction the designerfollows the process shown in Figure 3...

Page 358: ...p the Valid Logic or Viewlogic function to the AHDL function in an LMF LIBRARY user_lib User Library Mapping File BEGIN FUNCTION ALTR_AOS A_IN B_IN C_IN RETURNS Z_OUT FUNCTION AOS A B C RETURNS Z END AHDL is a high level modular language used to create logic designs fm Altera EPLDs AHDL files can be created with any standard text editor AHDL supports state machines truth tables and Boolean equatio...

Page 359: ...TLE Timed Add and Compare function DESIGN IS add_cmp DEVICE IS EPM5128 2 FUNCTION 74161 LDN A B C D ENT ENP CLRN CLK RETURNS QA QB QC QD RCO SUBDESIGN add_cmp VARIABLE BEGIN a 7 0 b 7 0 cmpen clock reset result 7 0 elapse 3 0 equal less_than grtr_than done inputs for adder comparator INPUT OUTPUT timer register 7 0 flag 74161 timer is 74161 counter DFF register is an octal FF NODE set up accumulat...

Page 360: ...r the Compiler Netlist Extractor extracts the netlist used to define the design from the EDIF Input Files edf and AHOT Text Design Files tdf At this time design rules are checked for any errors Iferrors are found they are displayed by the Message Processor A successfully extracted design is built into a database and passed to the Logic Synthesizer The Logic Synthesizer module translates and optimi...

Page 361: ... Output Files The EDIF Netlist Extractor optionally writes an EDIF 2 a a netlist that contains allpost synthesis function and delay informationfor the completed design so that it can be integrated into the workstation environment An EDIF Output File edo is created for each device used in the design An Altera provided or user created Output Mapping File om can be used to map MAX PLUS II functions t...

Page 362: ...Sheet in this data book for more information about the Altera Stand Alone Programmer o Quarter inch cartridge tape QIC 24 9 track containing al1 PLS WSjSN programs and files MAX PLUS II Compiler includes Altera EDIF Netlist Reader and Writer MAX PLUS II TTL MacroFunction Library Library Mapping File for mapping Valid Logic functions to MAX PLUS II functions Library Mapping File for mapping Viewlog...

Page 363: ...piler compiler version 1 4 or higher Valid WEDIFNET EDIF netlist writer version 1 1 or higher o EDIF conversion simulation software Valid REDIFNET EDIF netlist reader version 1 1 or higher Valid RapidSIM version 1 1 or higher Logic Automation SmartModels for Classic or MAX 5000 EPLDs optional Viewlogic Users o Schematic capture EDIF conversion software Viewlogic Viewdraw graphics editor version 3 ...

Page 364: ...Notes ...

Page 365: ...rs with DOS version 3 1 or higher EAU002 The PAL2EPLD utility converts 20 pin PAL designs into EP320 or EP330 designs It directly converts PAL JEDEC Files into EP320 EP330 JEDEC Files EAU003 The EP310 to EP320 EP330 JEDEC File Converter automatically converts EP310 JEDEC Files to EP320 EP330 compatible JEDEC Files EAU004 An Altera customer has written an interface program between LogiCaps and Hous...

Page 366: ...e LogiCaps schematic drawing The same pin assignments are then retained even if additional changes are made to the circuit design EAU012 The LEF2ABEL utility translates a Logic Equation File LEF generated by the Altera Design Processor ADP to ABEL format A PLU users may thus take advantage of the ADP s SALSA Minimizer to generatE an optimized ABEL input file EAU013 The PAL2ADF utility converts PAL...

Page 367: ...on separate from their design station or who require a hardware extension to existing Altera systems It includes only the materials required for EPLD programming software tools for design entry processing and verification are sold separately PL ASAP includes the software controlled LP5 or LP6 Logic Programmer card The LP6 interfaces with IBM PC AT or compatible computers the LP5 interfaces with IB...

Page 368: ...eated witt the Waveform Editor applied to the EPLD and the resulting EPLD outpub canbe viewed within the Waveform Editor However functional testing h supported onlywith adapters with the prefix PLM See the PLED J G S C PLMD J G S Q Programming Adapters Data Sheet in this data book fOJ more information o Software controlled Logic Programmer interface card o Master Programming Unit MPU o Device prog...

Page 369: ...ce for functional testing and verification o START programming button makes programming successive EPLDs easy and efficient o Indicator LED shows when unit is active o Included in the price of PLDS HPS PLDS ENCORE PLDS MAX PLDS SAM PLCAD SUPREME PLDS MCMAP and PL ASAP packages The Altera Master Programming Unit MPU is a hardware module that programs all Altera EPLDs The MPU directly supports the 2...

Page 370: ...ted only with adapters with the prefix PLM See the PLED J G S Q PLMD J G S Q Programming Adapters Data Sheet in this data book for more information The MPU includes a 45 inch ribbon cable terminated with a 25 pin D type connector that interfaces with an Altera Logic Programmer card Programming or functional test information is transmitted from the programming card installed in any full expansion s...

Page 371: ... by the MPU All adapters with the PLM prefix allow functional test vectors to be applied to and read from EPLDs Test vectors can be created with the MAX PLUS II Waveform Editor and applied to the EPLD The resulting EPLD outputs can be viewed in the Waveform Editor Each adapter contains a zero insertion force dual in line package DIP J Iead JLCC and PLCC pin grid array PGA small outline IC SOIC or ...

Page 372: ...A PLEG1810 EPM5016 DIP PLED5016 J Iead PLEJ5016 sOle PLES5016 EPM5032 DIP PLED5032 DIP PLMD5032 1 J Iead PLEJ5032 sOle PLES5032 EPM5064 J Iead PLEJ5064 EPM5128 J Iead PLEJ5128 J Iead PLMJ5128 1 PGA PLEG5128 EPM5130 J Iead PLEJ5130 J Iead PLMJ5130 1 PGA PLEG5130 QFP PLEQ5130 EPM5192 J Iead PLEJ5192 J Iead PLMJ5192 1 PGA PLEG5192 EPS448 DIP PLED448 J Iead PLEJ448 EPS464 J Iead PLEJ464 J Iead PLMJ464...

Page 373: ...SW WS are software warranty and customer support products that provide access to the latestEPLD developmentinformation The Extended SoftwareWarranty ensures that customers receive all new software and documentation when development software is upgraded to provide new features and to support new EPLDs Customer support services include a telephone hotline to Altera Applications Engineers for assista...

Page 374: ...Notes ...

Page 375: ...ls and works closely with many third party vendors to ensure high quality support for EPLDs Tables 1 through 4 provide an overview of third party design entry tools logic compilers simulators and device programmers Current support at the time of printing is shown contact Altera s Applications Department at 1 800 800 EPLD for the most up to date information Page36s1 ...

Page 376: ...DASH Schematic Classic EPM5016 EPM5032 Dazix ACE Schematic MAX 5000 1 ISDATAGmbH LOG iC Text Classic EPM5016 EPM5032 Logical Devices Inc CUPL Text Classic MacCUPL Text Classic Mentor Graphics Corp NETED Schematic Classic 1 MAX 5000 1 Minc Inc PLDesigner Text Classic PGADesigner Text MAX 5000 1 OrCAD Systems Corp SDTIV Schematic Classic MAX 5000 1 PLD Text Classic Racal Redac Visula Schematic Class...

Page 377: ...s Inc CUPL Classic MacCUPL Classic Mentor Graphics Corp AutoLogic Classic MAX 5000 PLDSynthesis Classic Minc Inc PLDesigner Classic PGADesigner MAX 5000 2 OrCAD Systems Corp PLD Classic Racal Redac System Expert Classic 2 MAX 5000 2 Synopsys Inc Design Compiler Classic 2 MAX 5000 2 Valid Logic Systems Inc SystemPLD Classic SystemPGA MAX 5000 2 Notes 1 This compiler directly supports the EPM5016 an...

Page 378: ...a I O Corp ABEL 4 Classic EPM5016 EPM5032 ISDATAGmbH LOG iC Classic Logic Automation Inc SmartModel Classic MAX 5000 2 Logical Devices Inc CUPL Classic MacCUPL Classic Mentor Graphics Corp QuickSim MAX 5000 1 2 Minc Inc PLDesigner Classic PGADesigner MAX 5000 2 OrCAD Systems Corp VSTIV Classic Racal Redac CADAT Classic Valid Logic Systems Inc RapidSim Classic 2 MAX 5000 2 Viewlogic Systems Inc Vie...

Page 379: ...UniSite 40 Classic MAX 5000 SAM STG Digelec Inc UP 803 Classic DigiPack Classic Logical Devices Inc ALLPRO Classic Japan Macnics Corp PROMAC P3 Classic SMSGmbH SPRINT Expert Classic MAX 5000 Stag Microsystems Ltd ZL30 ZL30A Classic PPZ Classic SYSTEM3000 MAX 5000 Sunrise Electronics Inc T 10 Classic Note The companies listed above as well as several other manufacturers are continually developing s...

Page 380: ...stems Inc BYTEKCorp Cadence Design Systems Inc Capilano Computing Systems Ltd Data I O Corp Digelec Inc ISDATAGmbH Logic Automation Inc Logical Devices Inc OrCAD Systems Corp Mentor Graphics Corp Minc Inc Japan Macnics Corp Quadtree Software Corp_ Racal Redac SMSGmbH Stag Microsystems Ltd Sunrise Electronics Inc Valid Logic Systems Inc Viewlogic Systems Inc Telephone Number 619 554 1000 603 891 19...

Page 381: ...ents September 1991 ection 10 Military Products Military Products 373 Source Control Drawings for Military Qualified EPLDs 377 Total Dose Radiation Hardness of Altera EPLDs 379 Altera Corporation Page 371 I ...

Page 382: ......

Page 383: ...ailable on request from Altera Marketing An MPD is prepared inaccordance with the appropriate military specification format and should be used for preparing Source Control Drawings SCDs Refer to Source Control Drawings in this data book for a description of SCD generation Table 1 Classic Military Temperature Range EPLDs EPLD Package 1 t PD1 ns EP320 D 45 EP610 D J 35 EP910 D J 40 EP1810 J G 45 Tab...

Page 384: ... EP610JM8838X J 35 02D 00522 EP900DM8838 D 60 02D 00521 EP900JM8838 J 60 02D 00521 EP910DM8838 D 40 02D 00935 EP910JM8838 J 40 02D 00935 EP1800GM8838 G 75 02D 00509 EP1800JM8838 J 75 02D 00509 EP1810GM8838 G 45 02D 00782 EP1810JM8838 J 45 02D 00782 Table 5 MAX5000 MIL STD 883B Qualified EPLDs EPLD Package 1 t PD1 ns Altera Military Drawing EPM5032DM8838 D 25 02D 00828 EPM5032JM8838 J 25 02D 00828 ...

Page 385: ...6 7 1 Package configurations 0 J G J 1 t PD1 ns 50 55 55 35 35 60 60 75 45 45 1 t PD1 ns 25 25 35 35 D Windowed ceramic dual in line package CerDIP J Windowed ceramic J Iead chip carrier GLCC G Windowed ceramic pin grid array PGA Military Products I DESC Order Number 8863501RA 8686401 LA 8686401 XX 8947601 LX 8947601 XX 8854801QA 8854801 XX 8854902YC 8946901YC 8946901 XX DESC Order Number 90611XXL...

Page 386: ...Notes ...

Page 387: ...ation in Altera s commercial data book is not acceptable Altera s MPDs contain information on the scope reference documents MIL STD 883B requirements quality assurance provisions and preparation of delivery for EPLDs Characteristics of device screening such as bum in testing AC DC electrical properties timing waveforms and package dimensions are also detailed in MPDs These specifications may diffe...

Page 388: ...Notes ...

Page 389: ...orst case provide total dose tolerance far in excess of 10 krad Si The experiments were conducted with a Cobalt 60 isotope source with a dose rate of 750 krad Si per minute 10 Test units were powered up with Vee 5 0 V and all other pins connected to ground both during and after the irradiation until measurements were made All conditions of temperature control dose rate and electrical bias conforme...

Page 390: ...radiation Tests for the MAX 5000 EPLDs were performed at radiation hardness tc 6 5 krad Si under worst case Vcc For the MAX 5000 EPLDs the EPM5032DC was used for evaluation The tests were conducted with a Cobalt 60 isotope source with a dose rate ol 117 rad SI s All irradiation was performed at room temperature 250 C 3 while device under test DUT Vcc was set to 5 5 V Nine input pinf were pulled to...

Page 391: ...ese test devices such as the Programmable Interconnect Array PIA are included Programmed cell margin fell linearly with increasing total radiation dose Therefore to maximize radiation hardness it is important to program an adequate cell margin into the EPLD before irradiation Designers are advised to use Altera approved programming systems that provide optimized cell programming Page 381 I ...

Page 392: ...Notes ...

Page 393: ...formation Electronic Bulletin Board Service 385 Ordering Information 387 EPLD Package Outlines 391 Thermal Resistance OC W 405 Selecting Sockets for J Lead Packages 407 Sales Offices Distributors Representatives 413 Utera Corporation Page 383 I ...

Page 394: ......

Page 395: ...on Binary o Ymodem lK Xmodem o Kermit After the BBS connection has been established the user can choose between graphic for EGA or VGA displays or non graphic display mode The user is then prompted for his or her name a new user can also choose a password Each name and password are recorded for future log ons A series of screens appears automatically the Altera News screen the Personal Mail screen...

Page 396: ...tible with the MAX PLUS and MAX PLUS II software Thi utility can also produce an Altera Design File ADF that is compatiblE with A PLUS software JEDSUM The JEDSUM utility calculates the EPROM data checksum filE transmission checksum and the number of programmed architecture bib contained in an EPLD JEDEC File ABEL2MAX The ABEL2MAX utility converts TT2 files generated b Data I O s ABEL software vers...

Page 397: ... in line package CerDIP One time programmable plastiC dual in line package PDIP Windowed ceramic J Iead chip carrier JLCC One time programmable plastic J Iead chip carrier PLCC i Windowed ceramic pin grid array PGA One time programmable plastiC small outline integrated circuit SOIC I Windowed ceramic quad flat pack WQFP t One time programmable plastiC quad flat pack PQFP xamples C Commercial tempe...

Page 398: ...ment Systems Software Software Packages Altera EPLDs Supported Platform Ordering Code PCIWindows 3 0 PLDS HPS t t t t t t t PC DOS Workstation Notes PLS HPS t t t t t t PLS OS t t t t t t PLS ES t 2 t PLDS ENCORE t t t t t PLDS MAX PLS MAX PLCAD SUPREME PLS SUPREME PLDS SAivi PLS SAM PLDS MCMAP PLS MCKIT PLS EDIF PLS WS HP t t t t PLS WS SN 1 Developmentsystems are available withprogramming hardwa...

Page 399: ...ramming Hardware Adapters The LP6 Logic Programmercard interfaces with ffiM PC AT or compatible computers It should be ordered by the following code o PLP6 The Master Programming Unit MPU can directly program EP320 and EP330 DIP EPLDs adapters are required to program all other EPLDs The MPU should be ordered by the following code o PL MPU PL ASAP includes programming software a Logic Programmer ca...

Page 400: ...5016 sOle PLES5016 EPM5032 DIP PLED5032 DIP PLMD5032 2 J Iead PLEJ5032 sOle PLES5032 EPM5064 J Iead PLEJ5064 EPM5128 J Iead PLEJ5128 J Iead PLMJ5128 2 PGA PLEG5128 EPM5130 J Iead PLEJ5130 J Iead PLMJ5130 2 PGA PLEG5130 QFP PLEQ5130 EPM5192 J Iead PLEJ5192 J Iead PLMJ5192 2 PGA PLEG5192 EPS448 DIP PLED448 J Iead PLEJ448 EPS464 J Iead PLEJ464 J Iead PLMJ464 2 QFP PLEQ464 EPB2001 J Iead PLEJ2001 Note...

Page 401: ...Solder plate 60 40 Ceramic pin grid array G Alloy 42 Gold over nickel plate Plastic small outline IC S Copper Solder plate 60 40 Ceramic quad flat pack W Alloy 42 Matte tin plate Plastic quad flat pack Q Copper Solder plate 60 40 Package outlines are listed here in ascending size order The dimensions shown are nominal with a tolerance of 0 020 in 0 51 mm unless otherwise indicated Maximum lead cop...

Page 402: ...n Plastic J Lead Chip Carrier PLCC 048 See 045 x 45 Pin 1 1 r j 2 1 1 De ail 048 _ JL imml4 J1__ 050 042 t I t BSe 032 026 t 330 290 355 _I l I 025 Min 390 _ 20 Pin Plastic Small Outline IC SOIC Pin 1 037 104 _I 180 165 _ _ 5 Typ 093 044 tn nHnnnrtn nH 1 II t t ng _ _ _I 004 IPage392 013 020 050 Typ 012 _ 120 090 010 008 Data Sheet 012 I I 1_ 310 I M DetailB 045 R 025 Altera Corporation ...

Page 403: ...050 EPLD Package Outlines I 320 290 I I 15J 1 1BE _ 1 0 395 365 24 Pin Plastic Dual In Line Package PDIP 055 045 11 II n1 1 1 240 170 140 020 125 L __ _t Seating 145t 1 P f f Plane 020_ Min 24 Pin Plastic Small Outline IC SOIC I 1 11 t 100 BSC 020 016 135 125 037 t 104 419 325 295 012 i I 310 394 5 01 1ro 10 Typ vt iJ I 00 80 Typ I 016 050 r 044 I rumnm urr rmrll 1 n II t Plane _ _ 004 A tera Corp...

Page 404: ...020 065 esc 125 016 050 320 I I 012 008 15 1 I 0 395 365 28 Pin Plastic Dual In Line Package PDIP 055 045 11 11 Plnl 11 1 345 170 140 t 020 145t Typ m L __ _ Seating t t Plane 020_ Min I 1 11 t 100 esc 020 016 135 125 325 295 012 I I 1_ 310 2B Pin Piasiic Smaii Ouiiine iC SOiCj IPage394 013 020 050 Typ 012 394 419 013x45 10 Typ t iJj I 0 8 Typ _ l_t 016 050 Altera Corporation I ...

Page 405: ...ing 020 00194 Pin 1 045 45 Window r II 495 465 ffi H _ jj I I 485 8 Pin Plastic J Lead Chip Carrier PLCC iT Pin1 ff t 456 jl 450 495 485 Altera Corporation 010 008 Detail B 300 1 020 Min Detail B 020 R Min See Detail B 032 ft p 026 t 190 155 050 030 120 090 1J I iI 048 __ 042 t I t 050 I t Bse 430 032 026 I I I __I 180 165 390 025 Min 120 090 page39s1 ...

Page 406: ...0 035 ll llSeating 015 t Im II t Plane I 1 11 100 020 065 BSC 016 050 125 40 Pin Plastic Dual In Line Package PDIP 055 045 11 Min Il O O r o Pin 1 I I 2 070 _ _ _ _ _ _ _ __ 2 058 175 165 020 Data Sheet 600 1 _ 620 _1 01 001 15 1 I 0 680 640 1 _ 605 _1 595 I 547 537 155t Typ 145L __ _t Seating t t Plane J 020 Min IPage 396 I 1 11 t 100 020 130 BSC 016 120 l 012 I 640 008 I 610 Altera Corporation ...

Page 407: ...1 1 695 656 685 650 l Pinl o 656 650 695 685 Altera Corporation I w EPLD Package Outlines I For military qualified product see case outline J 11 in Appendix Cof MIL M 38510 500 Ref 1 3 010 006 arl 020 R Min 050 BSC 1 190 155 Detail B 010 032 I 026 I 050 BSC 020 R Min _I 180 165 Detail B See Detail B 050 030 _ 120 090 025 Min 120 090 Page 397 ...

Page 408: ...ta Sheet I 1 8 20 _ _ T 60 T 13 Detail B 68 Pin Ceramic J Lead Chip Carrier JLCC For military qualifiedproduct see case outline C J2 in Appendix CofMIL M 38510 See Detail Pin 1 w r Windo _ B 995 965 985 930 I I 800 94Cl Ref 88Cl I 021 017 t 965 1 930 995 985 050 010 030 006 050 BSC 120 rl _I 090 190 155 020RMin Detail B IPage 398 Altera Corporation I ...

Page 409: ...ail e 050 esc 020 R Min EPLD Package Outlines I 026 I I _I 180 165 930 890 025 Min 130 090 For military qualified product see case outline in A tera Military Product Drawing 020 00205 1120 1 080 610 600 l J Altera Corporation I V v Window 1 010 0 990 140 i 115 095 1 075 610 600 _1 070 Dia Typ 008 Ref 1 1 055 045 175 1 _ 185 020 016 050 Dia Page 399 I ...

Page 410: ...eramic J Lead Chip Carrier JLCC 045 W w Indo 1 165 1 130 200 tJ 180 t 1 165 1 1 130 1 200 1 180 IPage 400 1 000 Ref 010 006 1 I Detail B 11 050 BSC 020 R Min Data Sheet I See Detail I B 1 140 1 080 050 030 120 090 Altera Corporation ...

Page 411: ...5 1 4 Pin Ceramic Pin Grid Array PGA 1 120 1 080 I 715 705 o Altera Corporation L K H 010 008 020 MO 0050 _II_ I BSC DetailB 1 010 0 990 020 R Min G F ffl ffi D C 070 Dia Typ EPLD Package Outlines I 026 _II 025 I Min _ 120 I 090 180 165 140 I 115 095 075 1 1 1 715 705 _I 055 1 045 008 Ref Page 401 I ...

Page 412: ..._ 1_ 185 175 II OO5R Ejj H G 715 705 020 016 1 O Pin Ceramic Quad Flat Pack WQFP 17 40 F E D C B Pin1 1 7 0 0 1 F I I I 23 40 19 40 23 00 19 00 IPage 402 13 40 1 1 13 00 65 t BSC Window _ I 070 Dia Typ 2 75 2 15 1 50 1 00 See Detail B 008 Ref 2 2 0 25 __ 1 8 0 15 0 8 t_ _ _ __ 0 78 T f l T 0 38 0 60 0 20 Detail B A tera Corporation I ...

Page 413: ...1 O Pin Plastic Quad Flat Pack PQFP 23 40 20 20 23 00 19 80 17 40 17 00 1 13 40 1 I 13 00 Altera Corporation t 30 65 t Bse EPLD Package Outlines I See Detail B _ r _t_ 0 93 T_ t 0 67 Detail B 0 51 0 25 Page 403 I ...

Page 414: ...Notes ...

Page 415: ...ber of Pins Package 8JA 0 C W 8JC 0 C W EP330 20 PDIP 68 19 SOIC 88 17 EP610 24 CerDIP 60 10 PDIP 55 18 SOIC 77 17 EP610 28 JLCC 90 12 PLCC 74 13 EP630 24 PDIP 50 17 SOIC 77 17 EP630 28 PLCC 65 13 EP910 40 CerDIP 40 12 PDIP 49 23 EP910 44 JLCC 67 5 PLCC 58 10 EP1810 68 JLCC 47 12 PLCC 44 13 PGA 38 6 EP1830 68 PLCC 39 10 Note 1 The formula for determining 8Jx is 8Jx TJ TA PD where TJ die junction t...

Page 416: ...LCC C F C F PGA 32 2 EPM5130 100 WQFP C F C F PQFP C F C F PGA 26 4 EPM5192 84 JLCC 30 4 PLCC C F C F PGA 27 2 Notes 1 The formula for determining 9Jx is 9Jx TJ TA jPD where TJ die junction temperature TA ambient temperature and PD power being dissipated in the device causing a temperature rise at the die junction TJ is determined by characterizingthe relationship between the torward blased voitag...

Page 417: ...ace mount assembly places unique demands on the development and manufacturing processes by requiring different CAD symbols for PC board layout different test and reliability procedures for buried vias within PC boards and a different soldering process for production vapor phase vs wave solder Bonding EPLDs to a PC board also removes the possibility of convenient erasure and reprogramming which are...

Page 418: ...t that prevents a device from being forced too far into a socket and having its pins bent Altera has tested several production sockets for use with 44 68 and 84 pin windowed ceramic J lead EPLDs Each socket underwent three tests o The change in the gap between the comer pins of each device was measured before and after each of 10 insertions o Each pin of the socket was wired in series and tested f...

Page 419: ...ce has a LCS 68 2 downward component Has a retainer clip option 3MfTextool Corporation Moderate pin deformation Contact force is lateral 2 0068 06234 070 038 077 Has a retainer clip option AMP Inc Moderate pin deformation Contact force has a 821574 1 downward component No retainer clip option Table 3 Summary of84 Pin Production Socket Analysis Vendor and Part Number Comments Augat Inc Least pin de...

Page 420: ...PS448L EP910J EP910AJ EPM5064J EPS464J 44 685 695 EP910 EP910A EPM5064L EPS464L 44 685 695 EP1810J EPM5128J 68 985 995 EP1810L EP1830L EPM5128L 68 985 995 EPB2001J EPM5192J 84 1180 1200 EPB2001 L EPM5192L 84 1185 1195 Note 1 J Windowed ceramic J Iead chip carrier GLCC L One time programmable plastic J Iead chip carrier PLCC Wire wrap applications require a through hole mount compatible with the J ...

Page 421: ...poration 714 261 5300 3MfTextooI Corporation Test and Burn In Sockets 800 225 5373 AMP Inc 800 552 6752 Advanced Interconnections 401 823 5200 Corporation Dai Ichi Seiko Co Ltd 011 81 0482 53 3131 Japan Emulation Technology Inc 408 982 0660 Advanced Interconnections Carrier Boards and 401 823 5200 Corporation Wire Wrap Adapters Emulation Technology Inc 408 982 0660 Information in this application ...

Page 422: ...Notes ...

Page 423: ...ay San Jose CA 95134 2020 USA TEL 408 984 2800 TLX 888496 FAX 408 248 7097 BELGIUM EUROPEAN HEADQUARTERS Altera Europe 25 Avenue de Beaulieu B 1160 Bruxelles Belgium TEL 32 2 660 20 77 TLX 886 27087901 AVVALB FAX 32 2 660 52 25 Sales Offices Distributors Representatives MASSACHUSETTS Altera Corporation 945 Concord Street Framingham MA 01701 TEL 508 626 0181 FAX 508 879 0698 NEW JERSEY Altera Corpo...

Page 424: ...oad Carrollton TX 75006 214 387 3601 CALIFORNIA Exis Inc 11223 Welty Lane Auburn CA 95603 916 885 3062 Exis Inc 2841 Junction Ave Suite 202 San Jose CA 95134 408 456 1650 QuadRep Southern Inc 28720 Roadside Drive Suite 227 Agoura CA 91301 818 597 0222 UNITED KINGDOM Altera UK 5 Tower Court Horns Lane Princes Risborough Bucks HP17 OAJ U K TEL 44 844275 285 TLX 851 94016389 TIME G FAX 44 844275 599 ...

Page 425: ... KS 66215 913 888 0022 KENTUCKY Electro Reps Inc 7240 Shadeland Station Suite 275 Indianapolis IN 46256 317 842 7202 LOUISIANA Technical Marketing Inc 2901 Wilcrest Drive Suite 139 Houston TX 77042 713 783 4497 MAINE Technology Sales Inc 332 Second Avenue Waltham MA 02154 617 890 5700 MARYLAND Robert Electronic Sales 5525 Twin Knolls Road Suite 325 Columbia MD 21045 301 995 1900 MASSACHUSETTS Tech...

Page 426: ...ns Corporation 4812 Frederick Road Suite 101 Dayton OH 45414 513 278 0714 The Lyons Corporation 4615 W Streetsboro Road Richfield OH 44286 216 659 9224 OHIO continued The Lyons Corporation 248 N State Street Westerville OH 43081 614 895 1447 OKLAHOMA Technical Marketing Inc 3320 Wiley Post Road Carrollton TX 75006 214 387 3601 OREGON Westerberg Associates Inc 7165 SW Fir Loop Portland OR 97223 503...

Page 427: ...BEC Kaytronics 5800 Thimens Boulevard Ville St Laurent Quebec H4S 1S5 Canada 514 745 5800 ARGENTINA VEL S R L Virrey Cevallos 143 1077 Buenos Aires Argentina TEL 54 1 45 714017163 TLX 390 18605 VEL AR FAX 54 1 440 1533 WASHINGTON Westerberg Associates Inc 12505 NE Bel Red Road Suite 112 Bellevue WA 98005 206 453 8881 WEST VIRGINIA Robert Electronic Sales 5525 Twin Knolls Road Suite 325 Columbia MD...

Page 428: ...bs AG Stahlgruberring 12 8000 Munchen 82 Germany TEL 49 89 42001 0 TLX 841 522561 ELEC D FAX 49 89 42001 209 HONG KONG ATI Industries Co Ltd A19 10 F Proficient Industrial Center 6 Wang Kwun Aoad Kowloon Hong Kong TEL 852 795 7421 FAX 852 795 7839 INDIA Sritech Information Technology P Ltd 744 51 2nd Floor Chintal Plaza 33rd Cross 10th Main 4th Block Jayanagar Bangalore 560 011 India TEL 91 812 64...

Page 429: ...X 46 87039845 SWITZERLAND EljapexAG HardstraBe 72 5430 Wettingen Switzerland TEL 41 56 27 57 77 FAX 41 56261486 Sales Offices Distributors Representatives 1 SWITZERLAND continued Stolz AG TafernstraBe 15 5405 Baden Dattwil Switzerland TEL 41 56 84 90 00 TLX 845 825088 SAG CH FAX 41 568491 74 TAIWAN Galaxy Far East Corp 8F 6 390 Sec 1 Fu Hsing South Road Taipei Taiwan R O C TEL 886 2 705 7266 TLX 7...

Page 430: ...Notes ...

Page 431: ...Contents September 1991 Section 12 Subject Index Subject Index 421 Altera Corporation Page 421 I ...

Page 432: ......

Page 433: ...ne Input Language ASMILE 309 Apollo workstations see HP Apollo workstations ASM see Altera Assembly Language ASMILE see Altera State Machine Input Language assembly language design entry 30 213 310 BBS see electronic bulletin board service Boolean equation entry see also Altera Hardware Description Language 30 302 branch control logic 209 bulletin board service see electronic bulletin board servic...

Page 434: ...42 343 graphic schematic capture 29 272 285 301 microcode 30 213 310 netlist 31 276 319 332 342 343 state machine truth table see also Altera Hardware Description Language 29 273 287 302 309 table 30 third party support 365 waveform 29 274 design files Altera Design File ADF 302 EDIF Input File EDF 319 332 342 343 Graphic Design File GDF 284 State Machine File SMF 273 Text Design File TDF 273 284 ...

Page 435: ...7 selection guide 23 software warranty 32 363 389 Stand Alone Programmer PL ASAP 32 357 third party support 365 utility programs 355 devices see EPLDs device verification see testing distributors 414 417 EDIF support EDIF interface PC based 31 276 319 MAX PLUS workstation based 31 319 MAX PLUS II workstation based 31 332 342 343 electronic bulletin board service 355 385 electrostatic discharge 15 ...

Page 436: ...3 FSIM see functional simulation A PLUS functional simulation A PLUS FSIM 304 MAX PLUS II 279 SAM PLUS SAMSIM 312 functional testing MAX PLUS II see testing generic testing see testing Graphic Editor MAX PLUS 285 MAX PLUS II 272 Hierarchy Display MAX PLUS 285 MAX PLUSII 275 HPI Apollo workstations MAX PLUS II Compiler Mentor Graphics EDIF interface see also EDIF support 332 I O architecture EP330 ...

Page 437: ...A PLUS 301 MAX PLUS 289 MAX PLUS II 275 Master Programming Unit MPU 33 357 359 389 MAX 5000 EPLDs EPM5016 19 137 EPM5032 19 143 EPM5064 19 149 EPM5128 19 155 EPM5130 19 161 EPM5192 19 169 introduction 125 military 22 373 374 375 overview 123 selection guide 19 thermal resistance 405 total dose radiation hardness 379 MAX 7000 EPLDs 179 MAX PLUS design entry 285 design processing 289 design verifica...

Page 438: ...U see Master Programming Unit MTA see Timing Analyzer multiway branching SAM EPLDs 217 N to l option 229 231 netlist design entry EDIF 31 276 319 332 342 343 noise precautions for EPLDs 16 265 operating requirements for EPLDs 265 ordering information 387 package outlines for EPLDs 391 partitioning 278 339 351 PL ASAP 32 357 PL MPU 33 357 359 389 PLAESW HPS 32 363 389 PLAESW MAX 32 363 389 PLAESW S...

Page 439: ...es 413 SAM Design Processor SDP 308 312 SAM EPLDs EPS448 20 205 military 374 overview 189 selection guide 20 SAM PLUS design entry 309 design processing 312 EPLD programming 312 functional simulation 312 overview 307 SAMSIM Functional Simulator 312 SCD see Source Control Drawings schematic capture design entry LogiCaps A PLUS 301 MAX PLUS Graphic Editor 285 MAX PLUS II Graphic Editor 272 overview ...

Page 440: ... 343 switching waveforms EP330 44 EP610 EP610A EP610T EP630 55 EP910 EP910A EP910T 83 EP1810 EP1810T EP1830 104 EPS448 SAM 219 EPS464 STG 196 MAX 5000 EPLDs 133 Symbol Editor MAX PLUS 285 MAX PLUSII 272 Synchronous Timing Generator see STG EPLDs system noise 16 265 table design entry MCMap 30 testing design for testability 230 functional testing design verification 280 358 360 361 functional testi...

Page 441: ...Viewlogic EDIF interface PC based 276 324 MAX PLUS II Compiler EDIF interface Sun workstation based 343 Virtual Logic Analyzer VLA see also Waveform Editor A PLUS 304 SAM PLUS 312 warranty see software warranty waveform design entry 274 Waveform Editor see also Virtual Logic Analyzer MAX PLUS 291 MAX PLUS II 274 waveforms see switching waveforms Windows 3 0 Operating System 23 269 workstation supp...

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Page 443: ......

Page 444: ... Jose CA 95134 2020 Telephone 408 984 2800 Altera Europe 25 Ave de Beaulieu B 1160 Bruxelles Belgium Telephone 32 2 660 20 77 Altera Japan K K Ichikawa Gakugeidai Bldg Second Floor 12 8 Takaban 3 Chome Meguro Ku Tokyo 152 Telephone 03 3716 2241 ...

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