Altera Arria II GX FPGA User Manual Download Page 42

A–2

Chapter :

Preparing Design Files for Flash Programming

Arria II GX FPGA Development Kit, 6G Edition User Guide

July 2010

Altera Corporation

c

Altera recommends that you do not overwrite the factory hardware and factory 
software images unless you are an expert with the Altera tools. If you unintentionally 
overwrite the factory hardware or factory software image, refer to 

“Restoring the 

Flash Device to the Factory Settings” on page A–4

.

Preparing Design Files for Flash Programming

You can obtain designs containing prepared 

.flash

 files from the 

Arria II GX FPGA 

Development Kit, 6G Edition 

page of the Altera website or create 

.flash

 files from 

your own custom design. 

The Nios II EDS 

sof2flash

 command line utility converts your Quartus II-compiled 

.sof

 into the 

.flash

 format necessary for the flash device. Similarly, the Nios II EDS 

elf2flash

 command line utility converts your compiled and linked Executable and 

Linking Format File (

.elf

) software design to 

.flash

. After your design files are in the 

.flash

 format, use the Board Update Portal or the Nios II EDS 

nios2-flash-

programmer

 utility to write the 

.flash

 files to the user hardware 1 and user software 

locations of the flash memory.

f

For more information about Nios II EDS software tools and practices, refer to the 

Embedded Software Development

 page of the Altera website.

Creating Flash Files Using the Nios II EDS

If you have an FPGA design developed using the Quartus II software, and software 
developed using the Nios II EDS, follow these instructions:

1. On the Windows Start menu, click 

All Programs

 > 

Altera

 > 

Nios II EDS

 > 

Nios II 

Command Shell

.

2. In the Nios II command shell, navigate to the directory where your design files 

reside and type the following Nios II EDS commands:

For Quartus II 

.sof

 files:

sof2flash --input=<yourfile>_hw.sof --output=<yourfile>_hw.flash --offset=0x00AC0000 
--pfl --optionbit=0x00018000 --programmingmode=PS

r

For Nios II 

.elf

 files:

elf2flash --base=0x08000000 --end=0x0BFFFFFF --reset=0x0A020000 
--input=<yourfile>_sw.elf --output=<yourfile>_sw.flash 
--boot=$SOPC_KIT_NIOS2/components/altera_nios2/

boot_loader_sources/boot_loader_cfi.srec

r

The resulting 

.flash

 files are ready for flash device programming. If your design uses 

additional files such as image data or files used by the runtime program, you must 
first convert the files to 

.flash

 format and concatenate them into one 

.flash

 file before 

using the Board Update Portal to upload them.

1

The Board Update Portal standard 

.flash

 format conventionally uses either 

<

filename

>

_hw.flash

 for hardware design files or <

filename

>

_sw.flash

 for software 

design files.

Summary of Contents for Arria II GX FPGA

Page 1: ...101 Innovation Drive San Jose CA 95134 www altera com UG 01084 1 0 User Guide Arria II GX FPGA Development Kit 6G Edition Subscribe Arria II GX FPGA Development Kit 6G Edition User Guide...

Page 2: ...ted under numerous U S and foreign patents and pending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance wit...

Page 3: ...Arria II GX FPGA Development Kit 6G Edition 3 2 Installing the USB Blaster Driver 3 3 Chapter 4 Development Board Setup Introduction 4 1 Setting Up the Board 4 1 Factory Default Switch Settings 4 2 Ch...

Page 4: ...rformance Indicators 6 15 The Power Monitor 6 16 General Information 6 17 Power Information 6 18 Power Graph 6 18 Graph Settings 6 18 Reset 6 18 Calculating Power 6 18 Configuring the FPGA Using the Q...

Page 5: ...ent HSMCs provided by Altera partners supporting protocols such as Serial RapidIO 10 Gigabit Ethernet SONET Common Public Radio Interface CPRI Open Base Station Architecture Initiative OBSAI and other...

Page 6: ...Software The Quartus II software including the SOPC Builder system development tool provides a comprehensive environment for system on a programmable chip SOPC design The Quartus II software integrate...

Page 7: ...r Altera FPGA designs Arria II GX FPGA Development Kit 6G Edition Installer The license free Arria II GX FPGA Development Kit 6G Edition installer includes all the documentation and design examples fo...

Page 8: ...1 4 Chapter 1 About This Kit Kit Features Arria II GX FPGA Development Kit 6G Edition User Guide July 2010 Altera Corporation...

Page 9: ...ontact Altera before you proceed Inspect the Board To inspect the board perform the following steps 1 Place the board on an anti static surface and inspect it to ensure that it has not been damaged du...

Page 10: ...s refer to the Arria II GX FPGA Development Kit 6G Edition page For additional daughter cards available for purchase refer to the Development Board Daughtercards page For the Arria II GX device docume...

Page 11: ...llowing steps 1 Run the Quartus II Subscription Edition Software installer you acquired in Software on page 1 2 2 Follow the on screen instructions to complete the installation process f If you have d...

Page 12: ...oduct for a specific user you on specific computers The Manage Computers and Manage Users pages allow you to add users and computers not already present in the licensing system 1 To license the Quartu...

Page 13: ...ilable on the Altera website On the Altera Programming Cable Driver Information page of the Altera website locate the table entry for your configuration and click the link to access the instructions F...

Page 14: ...3 4 Chapter 3 Software Installation Installing the USB Blaster Driver Arria II GX FPGA Development Kit 6G Edition User Guide July 2010 Altera Corporation...

Page 15: ...the DC power jack J4 on the FPGA board and plug the cord into a power outlet c Use only the supplied power supply Power regulation circuitry on the board can be damaged by power supplies with greater...

Page 16: ...DIP Switch ON 0 OFF 1 4 3 2 1 SW3 ON PCIe MODE DIP Switch installed installed installed not installed J9 JTAG Control Jumpers Table 4 1 SW3 Dip Switch Settings Switch Board Label Function Default Pos...

Page 17: ...itch 5 has the following options When on reserved When off reserved Off 6 USB DISn Switch 6 has the following options When on reserved When off reserved Off 7 CLK EN Switch 7 has the following options...

Page 18: ...ns 5 6 HSMB DIS This jumper has the following options Installing the shunt removes HSMC port B from the JTAG chain Removing the shunt includes HSMC port B in the JTAG chain Installed J9 pins 7 8 PCIe...

Page 19: ...cycle the board The source code for the Board Update Portal design resides in the install dir kits arriaIIGX_2agx260_fpga examples directory If the Board Update Portal is corrupted or deleted from the...

Page 20: ...a design over the network into the user portion of flash memory on your board perform the following steps 1 Perform the steps in Connecting to the Board Update Portal Web Page to access the Board Upda...

Page 21: ...ers observe performance and measure power usage The application is also useful as a reference for designing systems To install the application follow the steps in Installing the Arria II GX FPGA Devel...

Page 22: ...e application The Configure menu identifies the appropriate design to download to the FPGA for each tab After successful FPGA configuration the appropriate tab appears and allows you to exercise the r...

Page 23: ...Arria II GX FPGA Development Board 6G Edition Reference Manual 5 Turn the power to the board on The board loads the design stored in the user hardware 1 portion of flash memory into the FPGA If your b...

Page 24: ...the FPGA with a test system design perform the following steps 1 On the Configure menu click the configure command that corresponds to the functionality you wish to test 2 In the dialog box that appe...

Page 25: ...PSR Read Write Determines which of the up to eight 0 7 pages of flash memory to use for FPGA reconfiguration The flash memory ships with pages 0 and 1 preconfigured Page Select Override PSO Read Writ...

Page 26: ...ailable options OCR1 Sets the MAX II OCR1 register Refer to Table 6 1 for the list of available options SRST Resets the system and reloads the FPGA with a design from flash memory based on the other M...

Page 27: ...shows the GPIO tab The following sections describe the controls on the GPIO tab Character LCD The Character LCD controls allow you to display text strings on the character LCD on your board Type text...

Page 28: ...turn the board LEDs on and off Push Button Switches The read only Push button switches control displays the current state of the board user push buttons Press a push button on the board to see the gra...

Page 29: ...ents Flash The Flash control allows you to read and write the flash memory on your board Type a starting address in the text box and click Read Values starting at the specified address appear in the t...

Page 30: ...y on your board Figure 6 5 shows the DDR3 tab The following sections describe the controls on the DDR3 tab Start The Start control initiates DDR3 memory transaction performance analysis Stop The Stop...

Page 31: ...ream each time you click the button Insert Error is only enabled during transaction performance analysis Clear Resets the Detected errors and Inserted errors counters to zeros Number of Addresses to W...

Page 32: ...y on your board Figure 6 6 shows the DDR2 tab The following sections describe the controls on the DDR2 tab Start The Start control initiates DDR2 memory transaction performance analysis Stop The Stop...

Page 33: ...tion stream each time you click the button Insert Error is only enabled during transaction performance analysis Clear Resets the Detected errors and Inserted errors counters to zeros Number of Address...

Page 34: ...r that you are testing for this test to work correctly The following sections describe the controls on the HSMC tab Status The Status control displays the following status information during the loopb...

Page 35: ...the FPGA fabric Error Control The Error control controls display data errors detected during analysis and allow you to insert errors Detected errors Displays the number of data errors detected in the...

Page 36: ...5 GHz double data rate equating to a theoretical maximum bandwidth of 5312 5 MBps full duplex The Power Monitor The Power Monitor measures and reports current power information for the board To start...

Page 37: ...e Power Monitor controls General Information The General information controls display the following information about the MAX II device MAX II version Indicates the version of MAX II code currently ru...

Page 38: ...n to refresh the graph Reset This Reset control clears the graph resets the minimum and maximum values and restarts the Power Monitor Calculating Power The Power Monitor calculates power by measuring...

Page 39: ...ard 6G edition power to the board is on and no other applications that use the JTAG chain are running To configure the Arria II GX FPGA perform the following steps 1 Start the Quartus II Programmer 2...

Page 40: ...6 20 Chapter 6 Board Test System Configuring the FPGA Using the Quartus II Programmer Arria II GX FPGA Development Kit 6G Edition User Guide July 2010 Altera Corporation...

Page 41: ...e files were created using the Nios II EDS just as the hardware design was created using the Quartus II software f For more information about Altera development tools refer to the Design Software page...

Page 42: ...mory f For more information about Nios II EDS software tools and practices refer to the Embedded Software Development page of the Altera website Creating Flash Files Using the Nios II EDS If you have...

Page 43: ...proceed to step 8 If no output appears on the LCD or if the CONF DONE LED D14 does not illuminate continue to step 4 to load the FPGA with a flash writing design 4 Launch the Quartus II Programmer to...

Page 44: ...on 3 Click Add File and select install dir kits arriaIIGX_2agx260_fpga factory_recovery ArriaIIGX_2agx260_dev_ bup sof 4 Turn on the Program Configure option for the added file 5 Click Start to downlo...

Page 45: ...how to restore the original factory contents to the MAX II CPLD on the FPGA development board 6G edition Make sure you have the Nios II EDS installed and perform the following instructions 1 Set the...

Page 46: ...A 6 Chapter Restoring the MAX II CPLD to the Factory Settings Arria II GX FPGA Development Kit 6G Edition User Guide July 2010 Altera Corporation...

Page 47: ...al support General Email nacomp altera com Software Licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Visual Cue Mean...

Page 48: ...function names for example TRI r An angled arrow instructs you to press the Enter key 1 2 3 and a b c and so on Numbered steps indicate a list of items when the sequence of the items is important suc...

Page 49: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Intel DK DEV 2AGX260N...

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