Alpha Data ADM-XRC-7Z2, User Manual

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ADM-XRC-7Z2 User Manual
V1.2 - 24th Feb 2020
4.2.1.6 MPRESENT#
Module Present. This output signal is connected directly to 0V.
4.2.1.7 JTAG
See Section Section 4.4
4.2.2 P5 HSSIO Links
Eight pairs of HSSIO links from the Zynq PL are routed to XMC connector P6.
The pinout and coupling of these links are compatible with PCI Express.
The Transmit (Tx) side of all eight lanes are AC coupled by 100nF capacitors, placed at the output from the PL.
The Receive (Rx) side of all eight lanes are directly connected from the connector to the PL.
Alternative coupling options are available as a special ordering option. Please contact Alpha Data for details.
4.3 Secondary XMC Connector P6
Full pinout information for this connector is listed in Table 21
4.4 JTAG Interfaces
4.4.1 On-board Interface
By default, the 7Z2 is configured to have a single (cascaded) JTAG scan chain connected to header J4. This
allows the connection of the Xilinx JTAG cable for debug using the Xilinx ChipScope tools.
The board can also be set to have two independent scan chains using DIP switch SW2-3. (See Table 5 . In
independent mode, the main chain (with the Zynq PL, CPLD and XRM interface) is connected to J4, while the
Zynq PS is connected to header J3.
If the cascaded or main scan chain is connected to the XMC connector (when SW1-5 is ON), header J4 should
not be used.
4.4.2 XMC Interface
The JTAG interface on the XMC connector is normally unused and XMC_TDI connected directly to XMC_TDO.
The interface can be connected to the cascaded or main interface (through level-translators) by switching SW1-5
ON. See Table 4
4.4.3 JTAG Voltages
The on-board JTAG scan chains uses 1.8V. The Vcc supply provided on J3 and J4 to the JTAG cable is +1.8V
and is protected by a poly fuse rated at 350mA. 3.3V signals must not be used at header J3 or J4.
The JTAG signals at the XMC interface use 3.3V signals and are connected through level translators to the
on-board scan chain.
The JTAG signals at the XRM2 interface use the adjustable voltage XRM_VIO.
4.5 Clocks
The board has nine reference clocks: one from the carrier, and eight generated on-board.
The clocks MGTCLK250M, PROGCLK, REFCLK200M and ETH_CLK25M are generated by a single Silicon
Labs Si5338B and are all synchronous.
Page 9 Functional Description
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