Alpha Data ADM-SDEV-CFG1 User Manual Download Page 6

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ADM-SDEV-CFG1 User Manual

V1.2 - 18th March 2020

1.2 References & Specifications

ANSI/VITA 57.1

FPGA Mezzanine Card (FMC) Standard, July 2008, VITA, ISBN 1-885731-49-3

ANSI/VITA 57.4

FPGA Mezzanine Card Plus(FMC+) Standard, March 2016, VITA, Draft

Table 1 : References

Page 2

Introduction

ad-ug-1361_v1_2.pdf

Summary of Contents for ADM-SDEV-CFG1

Page 1: ...ADM SDEV CFG1 User Manual Document Revision 1 2 18th March 2020...

Page 2: ...or form without prior written consent from Alpha Data Parallel Systems Ltd Head Office Address Suite L4A 160 Dundee Street Edinburgh EH11 1DQ UK Telephone 44 131 558 2600 Fax 44 131 558 2700 email sal...

Page 3: ...ns 4 3 2 JTAG Interface 5 3 2 1 On board Interface 5 3 2 2 JTAG Voltages 5 3 3 Clocks 6 3 4 IPASS Connector 6 3 5 SATA Connectors 6 3 6 Health Monitoring 6 3 7 GPIO Loopback 7 List of Tables Table 1 R...

Page 4: ...ADM SDEV CFG1 User Manual V1 2 18th March 2020 Page Intentionally left blank...

Page 5: ...2x 256MB QSPI Flash devices connected to the configuration bank of the Base board FPGA IPASS Connector allowing remote PCIe connection to the Base board FPGA A JTAG header to allow Vivado Hardware Man...

Page 6: ...1 2 References Specifications ANSI VITA 57 1 FPGA Mezzanine Card FMC Standard July 2008 VITA ISBN 1 885731 49 3 ANSI VITA 57 4 FPGA Mezzanine Card Plus FMC Standard March 2016 VITA Draft Table 1 Refe...

Page 7: ...tic discharge ESD To prevent damage observe ESD precautions Always wear a wrist strap when handling the card Hold the board by the edges Avoid touching any components Store in ESD safe bag 2 2 2 Confi...

Page 8: ...EPROM I2C QSPI Flash 256M x2 CONFIG BUS Clock Generator CLK1_M2C Clock Output Connector DP_ 1 Clock Input Connector CLK0_M2C POWER GPIO Loopbacks LA_ 16 0 LA_ 33 17 CONFIG GPIO CLOCKS HSSIO Figure 2 A...

Page 9: ...ough the FPGA the LPC FMC if fitted and the FMC if fitted The scan chain is shown in JTAG Boundary Scan Chain FPGA XCKU060 LPC FMC J1 FMC1_PRESENT Level Shift FMC2_VIO 3V3 En FMC1_TDI FMC1_TDO FPGA_TD...

Page 10: ...he high speed serial lanes is connected to an IPASS connector for remote PCIe connection Connector Signal FPGA Bank P pin N pin IPASS J6 DP0_C2M MGT Quad 224 AW8 AW7 DP0_M2C MGT Quad 224 AW4 AW3 GBTCL...

Page 11: ...2 18th March 2020 ADM SDEV BASE user manual for more information 3 7 GPIO Loopback Many of the unused FMC GPIO signals are looped back on the ADM SDEV CFG1 board for test purposes Page 7 Functional De...

Page 12: ...1 1 Removed reference to CDROM in section 2 1 18 Mar 2020 1 2 Corrected typos Address Suite L4A 160 Dundee Street Edinburgh EH11 1DQ UK Telephone 44 131 558 2600 Fax 44 131 558 2700 email sales alpha...