Prosilica GE Technical Manual V2.2.1
48
Camera interfaces
Reserved
These signals are reserved for future use and should be left disconnected.
Camera I/O connector internal circuit diagram
Figure 21: Prosilica GE internal circuit diagram
HIROSE HR10A-10R-12SB
1
2
3
4
5
6
7
8
9
10
11
12
AS SEEN FROM
CAMERA REAR VIEW
1
2
3
4
5
6
7
8
9
10
12
11
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EN
C1+
V+
C1-
C2+
C2-
V-
RIN
FORCEOFF
VCC
GND
DOUT
FORCEON
DIN
INVALID
ROUT
0.1μ
0.1μ
MAXIM
MAX3221CPWR
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD2
GND2
OUT1
OUT2
IN3
IN4
NC
GND2
VDD1
GND1
IN1
IN2
OUT3
OUT4
NC
GND1
1A4
1A3
1A2
1A1
2A4
2A3
2A2
2A1
VCC
2OE
GND
1OE
1Y4
1Y3
1Y2
1Y1
2Y4
2Y3
2Y2
2Y1
3
5
7
9
12
14
16
18
8
6
4
2
17
15
13
11
10
20
19
1
ISO+5V
VDD -3.3
NVE
IL7 16-3
LOGIC SYNC OUT 1
LOGIC SYNC OUT 2
LOGIC TRIGGER INPUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD2
GND2
OUT1
OUT2
IN3
IN4
NC
GND2
VDD1
GND1
IN1
IN2
OUT3
OUT4
NC
GND1
ISO+5V
VDD -3.3
NVE
IL7 16-3
LOGIC SYNC OUT 3
LOGIC TXD
LOGIC RXD
ISO+5V
MINI-SMB
MINI-SMB
OUT
IN
TRIGGER INPUT
SYNC OUT 1
TRIGGER INPUT
ISO+5V
ISO+5V
RS232-TXD
ISO RXD
ISO TXD
ISOLATED 5V POWER
ISOLATED GROUND
RS232-RXD
SYNC OUT 2
SYNC OUT 3
RS-232 RXD
RS-232 TXD
CAMERA INTERNAL CIRCUIT
GALVANIC ISOLATION BOUNDARY
0.1μ
0.1μ
TEXAS INSTRUMENTS
SN74ACT244PWR
