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Alinx ARTIX-7 FPGA User Manual Download Page 16

ARTIX-7 FPGA Development Board AX7103 User Manual

16 / 55

www.alinx.com

Figure 2-4-2: The DDR3 on the Core Board

DDR3 DRAM pin assignment:

Net Name

FPGA PIN Name

FPGA P/N

DDR3_DQS0_P

IO_L3P_T0_DQS_AD5P_35

E1

DDR3_DQS0_N

IO_L3N_T0_DQS_AD5N_35

D1

DDR3_DQS1_P

IO_L9P_T1_DQS_AD7P_35

K2

DDR3_DQS1_N

IO_L9N_T1_DQS_AD7N_35

J2

DDR3_DQS2_P

IO_L15P_T2_DQS_35

M1

DDR3_DQS2_N

IO_L15N_T2_DQS_35

L1

DDR3_DQS3_P

IO_L21P_T3_DQS_35

P5

DDR3_DQS3_N

IO_L21N_T3_DQS_35

P4

DDR3_DQ[0]

IO_L2P_T0_AD12P_35

C2

DDR3_DQ [1]

IO_L5P_T0_AD13P_35

G1

DDR3_DQ [2]

IO_L1N_T0_AD4N_35

A1

DDR3_DQ [3]

IO_L6P_T0_35

F3

Summary of Contents for ARTIX-7 FPGA

Page 1: ...ARTIX 7 FPGA Development Board AX7103 User Manual...

Page 2: ...ARTIX 7 FPGA Development Board AX7103 User Manual 2 55 www alinx com Version Record Version Date Release By Description Rev 1 2 2020 10 30 Rachel Zhou First Release...

Page 3: ...y 19 Part 2 8 JTAG Interface 20 Part 2 9 Power Interface on the Core Board 21 Part 2 10 Board to Board Connectors pin assignment 22 Part 2 11 Power Supply 29 Part 2 12 Structure Diagram 31 Part 3 Carr...

Page 4: ...ARTIX 7 FPGA Development Board AX7103 User Manual 4 55 www alinx com Part 3 12 keys 51 Part 3 13 LED Light 52 Part 3 14 Power Supply 53...

Page 5: ...erface 2 Gigabit Ethernet interfaces 1 HDMI Output interface 1 HDMI Input interface Uart Interface SD card slot etc It meets user s requirements for PCIe high speed data exchange video transmission pr...

Page 6: ...DDR3 capacities are up to 8Gbit which meets the need for high buffers during data processing The selected FPGA is the XC7A100T chip of XILINX s ARTIX 7 series in BGA 484 package The communication freq...

Page 7: ...H There are two high precision Sitime LVDS differential crystals one at 200MHz and the other at 125MHz providing stable clock input for FPGA systems and GTP modules 1 channel PCIe x4 interface Support...

Page 8: ...the computer for user debugging The serial port chip is the USB UAR chip of Silicon Labs CP2102GM and the USB interface is the MINI USB interface Micro SD card holder 1 port Micro SD card holder supp...

Page 9: ...ON s MT41J256M16HA 125 DDR3 chip each DDR has a capacity of 4Gbit two DDR chips are combined into a 32 bit data bus width and the read write data bandwidth between FPGA and DDR3 is up to 25Gb such a c...

Page 10: ...ARTIX 7 FPGA Development Board AX7103 User Manual 10 55 www alinx com Figure 2 1 1 AC7100B Core Board Front View Figure 2 1 2 AC7100B Core Board Rear View...

Page 11: ...is a FGG484 package with 484 pins Xilinx ARTIX 7 FPGA chip naming rules as below Figure 2 2 1 The Specific Chip Model Definition of ARTIX 7 Series Figure 2 2 2 FPGA chip on board The main parameters o...

Page 12: ...transceiver connected to 1 2V The Artix 7 FPGA system requires that the power up sequence be powered by VCCINT then VCCBRAM then VCCAUX and finally VCCO If VCCINT and VCCBRAM have the same voltage the...

Page 13: ...to generate clocks of different frequencies Figure 2 3 1 200Mhz Active Differential Crystal Schematic Figure 2 3 2 200Mhz Active Differential Crystal on the Core Board 200Mhz Differential Clock Pin A...

Page 14: ...d to the GTP BANK216 clock pins MGTREFCLK0P F6 and MGTREFCLK0N E6 of the FPGA Figure 2 3 3 125Mhz Active Differential Crystal Schematic Figure 2 3 4 125Mhz Active Differential Crystal on the Core Boar...

Page 15: ...BANK35 of the FPGA The specific configuration of DDR3 SDRAM is shown in Table 2 4 1 Bit Number Chip Model Capacity Factory U5 U6 MT41J256M16HA 125 256M x 16bit Micron Table 2 4 1 DDR3 SDRAM Configurat...

Page 16: ...P_T0_DQS_AD5P_35 E1 DDR3_DQS0_N IO_L3N_T0_DQS_AD5N_35 D1 DDR3_DQS1_P IO_L9P_T1_DQS_AD7P_35 K2 DDR3_DQS1_N IO_L9N_T1_DQS_AD7N_35 J2 DDR3_DQS2_P IO_L15P_T2_DQS_35 M1 DDR3_DQS2_N IO_L15N_T2_DQS_35 L1 DDR...

Page 17: ...L3 DDR3_DQ 19 IO_L17N_T2_35 J6 DDR3_DQ 20 IO_L14N_T2_SRCC_35 K3 DDR3_DQ 21 IO_L17P_T2_35 K6 Part 2 5 QSPI Flash The FPGA core board AC7100B is equipped with one 128MBit QSPI FLASH and the model is N2...

Page 18: ...FCS pins of BANK14 respectively Figure 2 5 1 shows the hardware connection of QSPI Flash Figure 2 5 1 QSPI Flash Schematic QSPI Flash pin assignments Net Name FPGA PIN Name FPGA P N QSPI_CLK CCLK_0 L1...

Page 19: ...to the user LED is high the user LED is off When the connection IO voltage is low the user LED will be lit The schematic diagram of the LED light hardware connection is shown in Figure 2 6 1 Figure 2...

Page 20: ...pin assignment Signal Name ZYNQ Pin Name ZYNQ Pin Number Description RESET_N IO_L17N_T2_34 T6 Reset Key Part 2 8 JTAG Interface The JTAG test socket J1 is reserved on the AC7100B core board for JTAG d...

Page 21: ...ure 2 8 2 shows the JTAG interface J1 on the AC7100B FPGA core board Figure 2 8 2 JTAG Interface on Core Board Part 2 9 Power Interface on the Core Board In order to make the AC7100B FPGA core board w...

Page 22: ...r connectors by differential routing The pin spacing of the connectors is 0 5mm insert to the board to board connectors on the carrier board for high speed data communication Board to Board Connectors...

Page 23: ...3V PIN24 B13_L1_N AA16 3 3V PIN25 B13_L7_P AB11 3 3V PIN26 B13_L2_P AB16 3 3V PIN27 B13_L7_P AB12 3 3V PIN28 B13_L2_N AB17 3 3V PIN29 GND Ground PIN30 GND Ground PIN31 B13_L3_P AA13 3 3V PIN32 B13_L6_...

Page 24: ...Pin Signal Name FPGA Pin Voltage Level PIN1 B13_L16_P W15 3 3V PIN2 B14_L16_P V17 3 3V PIN3 B13_L16_N W16 3 3V PIN4 B14_L16_N W17 3 3V PIN5 B13_L15_P T14 3 3V PIN6 B13_L14_P U15 3 3V PIN7 B13_L15_N T1...

Page 25: ...d PIN60 GND Ground PIN61 B13_L17_P T16 3 3V PIN62 B14_L3_N V22 3 3V PIN63 B13_L17_N U16 3 3V PIN64 B14_L3_P U22 3 3V PIN65 B14_L21_N P17 3 3V PIN66 B14_L20_N T18 3 3V PIN67 B14_L21_P N17 3 3V PIN68 B1...

Page 26: ...PIN20 GND Ground PIN21 B15_L11_P J20 3 3V PIN22 B16_L24_P G21 3 3V PIN23 B15_L11_N J21 3 3V PIN24 B16_L24_N G22 3 3V PIN25 B15_L1_N G13 3 3V PIN26 B15_L8_N G20 3 3V PIN27 B15_L1_P H13 3 3V PIN28 B15_L...

Page 27: ...CON4 The 80 Pin connector CON4 is used to extend the normal IO and GTP high speed data and clock signals of the FPGA BANK16 The voltage standard of the IO port of BANK16 can be adjusted by an LDO chi...

Page 28: ...PIN39 GND Ground PIN40 GND Ground PIN41 B16_L5_P E16 3 3V PIN42 B16_L2_P F16 3 3V PIN43 B16_L5_N D16 3 3V PIN44 B16_L2_N E17 3 3V PIN45 B16_L7_P B15 3 3V PIN46 B16_L3_P C14 3 3V PIN47 B16_L7_N B16 3 3...

Page 29: ...n core board schematic The development board is powered by 5V and converted to 3 3V 1 5V 1 8V 1 0V four way power supply through four DC DC power supply chip TLV62130RGT The output current can be up t...

Page 30: ...Bank16 MGTAVTT 1 2V GTP Transceiver Bank216 of FPGA MGTVCCAUX 1 8V GTP Transceiver Bank216 of FPGA Because the power supply of Artix 7 FPGA has the power on sequence requirement in the circuit design...

Page 31: ...ARTIX 7 FPGA Development Board AX7103 User Manual 31 55 www alinx com Part 2 12 Structure Diagram Figure 2 12 1 AC7100B FPGA Core board Top view Figure 2 12 2 AC7100B FPGA Core board Bottom view...

Page 32: ...function of the carrier board part 1 channel PCIe x4 high speed data transmission interface 2 channel 10 100M 1000M Ethernet RJ 45 interface 1 channel HDMI video input interface 1 channel HDMI video...

Page 33: ...Configuration value PHYAD 2 0 MDIO MDC Mode PHY Address PHY Address 011 CLK125_EN 3 3V 2 5V 1 5 1 8V voltage selection 3 3V SELRGV Auto negotiation configuration 10 100 1000M adaptive AN 1 0 RX clock...

Page 34: ...GA Development Board AX7103 User Manual 34 55 www alinx com sampled on the rising edge of the clock Figure 3 2 1 Gigabit Ethernet Interface Schematic Figure 3 3 2 Gigabit Ethernet interface on the Car...

Page 35: ...DV A15 PHY1 receive data valid signal E1_MDC B16 PHY1 Management Clock E1_MDIO B15 PHY1 Management Data E1_RESET D16 PHY1 Reset Signal Gigabit Ethernet Chip PHY2 pin assignments are as follows Signal...

Page 36: ...face are directly connected to the GTP transceiver of the FPGA The four channels of TX and RX signals are connected to the FPGA in differential signals and the single channel communication rate can be...

Page 37: ...0 PCIE Channel 2 Data Receive Negative PCIE_RX3_P D9 PCIE Channel 3 Data Receive Positive PCIE_RX3_N C9 PCIE Channel 3 Data Receive Negative PCIE_TX0_P D5 PCIE Channel 0 Data Transmit Positive PCIE_TX...

Page 38: ...oding chip support up to 1080P 60Hz output support 3D output The IIC configuration interface of SIL9134 is also connected to the IO of the FPGA The SIL9134 is initialized and controlled by FPGA progra...

Page 39: ...T15 9134_VS T14 9134_DE V13 9134_D 0 V14 9134_D 1 H14 9134_D 2 J14 9134_D 3 K13 9134_D 4 K14 9134_D 5 L13 9134_D 6 L19 9134_D 7 L20 9134_D 8 K17 9134_D 9 J17 9134_D 10 L16 9134_D 11 K16 9134_D 12 L14...

Page 40: ...rt up to 1080P 60Hz input and support data output in different formats The IIC configuration interface of the SIL9013 is connected to the IO of the FPGA The SIL9013 is initialized and controlled throu...

Page 41: ...HS K19 9013_VS K18 9013_DE H17 9013_D 0 H18 9013_D 1 N22 9013_D 2 M22 9013_D 3 K22 9013_D 4 J22 9013_D 5 H22 9013_D 6 H20 9013_D 7 G20 9013_D 8 G22 9013_D 9 G21 9013_D 10 D22 9013_D 11 E22 9013_D 12 D...

Page 42: ...h and development In 2000 these companies launched the SD Association Secure Digital Association which has a strong lineup and attracted a large number of vendors These include IBM Microsoft Motorola...

Page 43: ...SD_CD_N F14 SD_DAT0 AA13 SD_DAT1 AB13 SD_DAT2 Y13 SD_DAT3 AA14 Part 3 7 USB to Serial Port The AX7103 FPGA development board includes the USB UAR chip of Silicon Labs CP2102GM The USB interface uses t...

Page 44: ...2 USB to serial port on the Carrier board Two LED indicators LED3 and LED4 are set for the serial port signal and the silkscreen on the PCB is TX and RX indicating that the serial port has data transm...

Page 45: ...ins an EEPROM model 24LC04 and has a capacity of 4Kbit 2 256 8bit It consists of two 256 byte blocks and communicates via the IIC bus The onboard EEPROM is to learn how to communicate with the IIC bus...

Page 46: ...by the user The expansion port has 40 signals of which 1 channel 5V power supply 2 channel 3 3 V power supply 3 channle ground and 34 IOs Do not directly connect the IO directly to the 5V device to av...

Page 47: ...Figure 3 9 2 Expansion header J11 on the Carrier board J11 Expansion Header Pin Assignment Pin Number FPGA Pin Pin Number FPGA Pin 1 GND 2 5V 3 P16 4 R17 5 R16 6 P15 7 N17 8 P17 9 U16 10 T16 11 U17 12...

Page 48: ...figure 3 9 4 detailed the J13 expansion port on the carrier board The Pin1 and Pin2 of the expansion port are already marked on the board Figure 3 9 4 Expansion header J13 on the carrier board J13 Ex...

Page 49: ...P14 35 N13 36 N14 37 GND 38 GND 39 3 3V 40 3 3V Part 3 10 JTAG Interface A JTAG interface is reserved on the AX7103 FPGA carrier board for downloading FPGA programs or firmware to FLASH In order to p...

Page 50: ...h pitch double row pin The XADC interface extends three pairs of ADC differential input interfaces to the 12 Bit 1Msps analog to digital converter of the FPGA One pair of differential interfaces is co...

Page 51: ...9N H15 Peak to peak 1V FPGA assisted XADC input channel 9 can be used as normal IO 9 10 AD0P H13 AD0N G13 Peak to peak 1V FPGA assisted XADC input channel 0 can be used as normal IO Part 3 12 keys The...

Page 52: ...arrier board one of which is the power indicator PWR two are USB Uart data receiving and transmitting indicators and four are users LED lights LED1 LED4 When the board is powered on the power indicato...

Page 53: ...Schematic Figure 3 13 2 The User LEDs on the Carrier board Pin assignment of user LED lights Signal Name FPGA PIN LED1 B13 LED2 C13 LED3 D14 LED4 D15 Part 3 14 Power Supply The power input voltage of...

Page 54: ...tage into 5V 3 3V 1 8V and 1 2V four way power supply through the 4 channel DC DC power supply chip MP1482 In addition the 5V power supply on the FPGA carrier board supplies power to the AC7100B FPGA...

Page 55: ...ARTIX 7 FPGA Development Board AX7103 User Manual 55 55 www alinx com Figure 3 14 3 Power Supply Circuit on the Carrier board...

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