AC7010B / AC7020B User Manual
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(PL).
On the AC7010B/AC7020B core board, the PS part of the ZYNQ7000 is
equipped with a wealth of external interfaces and devices for user convenience
and function verification. The IO ports on the PL side are all led to the 2.54mm
connector on the board for user expansion. In addition, there is a 7 x 2 JTAG
connector on the core board that can be downloaded and debugged via the
ALINX Xilinx USB Cable Downloader. Figure 1-2 shows the structure of the
entire AC7010B/AC7020B system:
Figure 1-1: The Schematic Diagram of the AC7010B/AC7020B
Through this diagram, you can see the interfaces and functions that the
AC7010B/AC7020B FPGA Core Board contains:
DC5V power input, maximum current does not exceed 500mA
Xilinx ARM+FPGA chip Zynq-7000 XC7Z010-1CLG400C for AC7010B,
Zynq-7000 XC7Z020-2CLG400I for AC7020B
DDR3
Two large-capacity 2Gbit (A total of 4Gbit) high-speed DDR3 SDRAMs
can be used as a cache for ZYNQ chip data or as a memory for the