ZYNQ7000 FPGA
Core Board
AC7010BB/AC7020BB
User Manual
Page 1: ...ZYNQ7000 FPGA Core Board AC7010BB AC7020BB User Manual...
Page 2: ...AC7010B AC7020B User Manual 2 39 www alinx com Version Record Revision Date Release By Description Rev 1 0 2022 09 07...
Page 3: ...iguration 15 Part 5 1 PS system clock source 15 Part 5 2 PL system clock source 16 Part 6 ZYNQ Processor System PS peripherals 16 Part 6 1 QSPI Flash 17 Part 6 2 DDR3 DRAM 18 Part 6 3 Gigabit Ethernet...
Page 4: ...ive peripheral interfaces such as Gigabit Ethernet USB2 0 serial port SD card etc are extended on the ARM side In addition the core board expands a large number of IOs to the outer three connectors in...
Page 5: ...vided The core board uses Xilinx s Zynq7000 series of chips the AC7010B uses the Zynq7000 s XC7Z010 1CLG400C chip and the AC7020B uses the Zynq7000 s XC7Z020 2CLG400I chip both of which are 400 pin FB...
Page 6: ...downloaded and debugged via the ALINX Xilinx USB Cable Downloader Figure 1 2 shows the structure of the entire AC7010B AC7020B system Figure 1 1 The Schematic Diagram of the AC7010B AC7020B Through th...
Page 7: ...USB Type A USB OTG Interface 1 channel high speed USB2 0 OTG interface for OTG communication with PC or USB devices USB Uart Interface 1 channel USB Uart interface for serial communication with PC or...
Page 8: ...fixing the development board The holes diameter of the positioning hole is 0 09 inch and the dxf structure diagram is provided in the documents Figure 2 1 FPGA Size Dimension Part 3 Power Supply The...
Page 9: ...he development board is powered by 5V and is converted into 1 5V 1 8V 1 0V three way power supply through three DC DC power supply chip TLV62130RGT Each output current can be up to 3A The 3 3V VCCIO34...
Page 10: ...4 VCCIO35 Figure 3 2 shows the circuit design of the power supply In the PCB design an 8 layer PCB is used and a separate power supply layer and GND layer are reserved so that the power supply of the...
Page 11: ...PU 512KB level 2 cache 2 CPU shares On chip boot ROM and 256KB on chip RAM External storage interface support 16 32 bit DDR2 DDR3 interface Two Gigabit NIC support divergent aggregate DMA GMII RGMII S...
Page 12: ...l input channels 1MBPS XC7Z010 1CLG400C or XC7Z020 2CLG400I chip package is BGA 400 pins the pin pitch is 0 024 inch Again let s talk about the BGA pin When we use the BGA package chip the pin name be...
Page 13: ...four signals TCK TMS TDO and TDI These four signals are connected to the JTAG pins of BANK0 of the Zynq7010 Zynq7020 chip TCK_0 TMS_0 TDO_0 and TDI_0 Figure 4 3 The JTAG port schematic The JTAG inter...
Page 14: ...em requires that the power up sequence be VCCPINT first then VCCPAUX and VCCPLL and finally PS VCCO The order of power outages is reversed The power supply for the PL section is VCCINT VCCBRAM VCCAUX...
Page 15: ...startup mode configuration Part 5 Clock Configuration The AC7010B AC7020B core board provides an active clock for the PS system and the clock of the PL logic part can be generated by the PLL of the PS...
Page 16: ...drive user logic in the FPGA The schematic diagram of the clock source is shown in Figure 5 3 Figure 5 3 PL system clock source PL Clock pin assignment Signal Name ZYNQ Pin 500_CLK U18 Part 6 ZYNQ Pro...
Page 17: ...mainly include FPGA bit files ARM application code and other user data files The specific models and related parameters of QSPI FLASH are shown in Table 6 1 Position Model Capacity Factory U6 W25Q256...
Page 18: ...ments Signal Name ZYNQ Pin Name ZYNQ Pin Number QSPI_SCK PS_MIO6_500 A5 QSPI_CS PS_MIO1_500 A7 QSPI_D0 PS_MIO2_500 B8 QSPI_D1 PS_MIO3_500 D6 QSPI_D2 PS_MIO4_500 B7 QSPI_D3 PS_MIO5_500 A6 Part 6 2 DDR3...
Page 19: ...terface of the BANK 502 of the ZYNQ Processing System PS The specific configuration of DDR3 SDRAM is shown in Table 6 2 Core Board Bit Number Chip Model Capacity Factory AC7010B U8 U9 H5TQ2G63FFR RDC...
Page 20: ...DR3_DQS0_P PS_DDR_DQS_P0_502 C2 DDR3_DQS0_N PS_DDR_DQS_N0_502 B2 DDR3_DQS1_P PS_DDR_DQS_P1_502 G2 DDR3_DQS1_N PS_DDR_DQS_N1_502 F2 DDR3_DQS2_P PS_DDR_DQS_P2_502 R2 DDR3_DQS2_N PS_DDR_DQS_N2_502 T2 DDR...
Page 21: ...DR_DQ18_502 R3 DDR3_DQ 19 PS_DDR_DQ19_502 R1 DDR3_DQ 20 PS_DDR_DQ20_502 T4 DDR3_DQ 21 PS_DDR_DQ21_502 U4 DDR3_DQ 22 PS_DDR_DQ22_502 U2 DDR3_DQ 23 PS_DDR_DQ23_502 U3 DDR3_DQ 24 PS_DDR_DQ24_502 V1 DDR3_...
Page 22: ...B_502 B4 DDR3_CLK_P PS_DDR_CKP_502 L2 DDR3_CLK_N PS_DDR_CKN_502 M2 DDR3_CKE PS_DDR_CKE_502 N3 Part 6 3 Gigabit Ethernet Interface The AC7010B AC7020B FPGA core board provides network communication ser...
Page 23: ...uration value When the network is connected to Gigabit Ethernet the data transmission of ZYNQ and PHY chip JL2121 N040I is communicated through the RGMII bus the transmission clock is 125Mhz and the d...
Page 24: ...DC PS_MIO52_501 C10 MDIO Management clock ETH_MDIO PS_MIO53_501 C11 MDIO Management data Part 6 4 USB2 0 Interface The USB2 0 transceiver used in the AC7010B AC7020B is a 1 8V high speed USB3320C EZK...
Page 25: ...lave peripherals J5 and J6 not installation jumper caps OTG Mode FPGA core board as a slave device USB port to connect to the computer Table 6 3 The USB interface mode switching instructions Figure 6...
Page 26: ...SB Clock Signal OTG_DATA5 PS_MIO37_501 A10 USB Data Bit5 OTG_DATA6 PS_MIO38_501 E13 USB Data Bit6 OTG_DATA7 PS_MIO39_501 C18 USB Data Bit7 OTG_RESETN PS_MIO46_501 D16 USB Reset Signal Part 6 5 USB to...
Page 27: ...in assignment Signal name ZYNQ Pin Name ZYNQ Pin Number Description UART_TX PS_MIO48_501 B12 Uart data input UART_RX PS_MIO49_501 C12 Uart data output Silicon Labs provides virtual COM port VCP driver...
Page 28: ...the SD card memory the BOOT program for storing the ZYNQ chip the Linux operating system kernel the file system and other user data files The SDIO signal is connected to the IO signal of the PS BANK50...
Page 29: ...CD PS_MIO47 B14 SD Card Insertion Signal Part 6 7 User LEDs On the AC7010B AC7020B core board one LED light emitting diode is connected to the BANK500 IO of the PS part and the user can use this LED l...
Page 30: ...anually reset In the design when the reset key is pressed the reset signal is low and the ZYNQ chip is reset When the key is released the ZYNQ chip starts to work normally Figure 6 16 shows the reset...
Page 31: ...1 the LED will be extinguished Figure 7 1 PL User LED Schematic Figure 7 2 PL User LEDs on the FPGA Core Board PL User LEDs pin assignment Signal Name ZYNQ Pin Name ZYNQ Pin Number Description LED2 IO...
Page 32: ...NQ PL The PCB design is differentially connected The default level is 3 3V The user can change the IO level of the BANK34 by replacing the power chip U20 on the core board In addition there are 8 IO p...
Page 33: ...N18 PIN8 IO34_L13N P19 PIN9 IO34_L7P Y16 PIN10 IO34_L7N Y17 PIN11 IO34_L10N W15 PIN12 IO34_L10P V15 PIN13 IO34_L8P W14 PIN14 IO34_L8N Y14 PIN15 IO34_L11P U14 PIN16 IO34_L11N U15 PIN17 IO34_L6P P14 PIN...
Page 34: ...face can be directly connected to the module provided by ALINX include ADDA module LCD module Gigabit Ethernet module audio input output module matrix keyboard module 500W binocular vision camera modu...
Page 35: ...1 on the FPGA Board J11 Expansion Header Pin Assignment J11 Pin Signal Name ZYNQ Pin Number PIN1 GND PIN2 5V PIN3 IO34_L23P N17 PIN4 IO34_L23N P18 PIN5 IO34_L24P P15 PIN6 IO34_L24N P16 PIN7 IO35_L9N L...
Page 36: ...0 IO34_L18N W16 PIN31 IO35_L21P N15 PIN32 IO35_L21N N16 PIN33 IO35_L23P M14 PIN34 IO35_L23N M15 PIN35 IO35_L22P L14 PIN36 IO35_L22N L15 PIN37 GND PIN38 GND PIN39 3 3V PIN40 3 3V Part 7 4 Expansion Por...
Page 37: ...upply 3 channle ground and 34 IOs 34 IO ports are connected to BANK34 and BANK35 of ZYNQ PL The PCB design is differentially connected The default level is 3 3V The user can change the level of IO by...
Page 38: ...35_L14N H18 PIN11 IO35_L17N H20 PIN12 IO35_L17P J20 PIN13 IO35_L12N K18 PIN14 IO35_L12P K17 PIN15 IO35_L16P G17 PIN16 IO35_L16N G18 PIN17 IO35_L13P H16 PIN18 IO35_L13N H17 PIN19 IO35_L10N J19 PIN20 IO...
Page 39: ...AC7010B AC7020B User Manual 39 39 www alinx com PIN35 PS_MIO10 E9 PIN36 PS_MIO12 D9 PIN37 GND PIN38 GND PIN39 3 3V PIN40 3 3V...
