5) Terminal function of CPU
No.
U*e1
ÜM2
U »*3
Pin Nam*
Remarks
I/O
Description
L
H
2
AVss
GNO
3
GNO
4
;
X2
XTAL, LOSC
s
X1
XTAL
6
Vss
GNO
7
OSC1
XTAL
8
OSC2
XTAL
9
/RES
/RST
I
10
MDO
SV?
I
11
P20
IR04
ADTRG
DCK
DIAL CLOCK
‘
Mam dial rolaton detection and pulse
number
Rise edge
Oeteclon
12
P21
UO
PCONT
POWER ON
O
Power control output
Power OFF
Power ON
13
P22
PSDET
POWER DfTT
'
Condition Oetecuon «when power switch is
turned ON.
Dunng power
OFF
During power QN
,4
P23
TKEY
TUNE KEY
’
Detection of worVing external antenna
tuner
At work
Waiting
IS
P24
UNLK
PLL UNLOCK
1
PLL unkxx detection
Unloc*
Lock
16
P2S
MCK
EEPROM CK
0
Ctock tor data trans>Tiissio<Vrec©p»ion to
EEPROM
P26
MDAT
EEPROM DATA
I/O
Data Transmission/Reception to
EEPROM
P27
EXT1N
EXT IN
'
External EEPROM transmission
eoce£*ance
EEPROM
Acceptance
19
P30
SCK1
CK1
SER1AL1 CK
o
HPL LPLdata tranjimisson
ckx*
20
P3i
Sn
DAT1
SERIAL 1 DATA
o
HPL. LPLdata transmission
25
P32
SOI
ENH
HPLL ENABLE
o
HPL data transmission enable
Enable
22
P33
SCK2
ENL
LPLL ENABLE
o
IP L data transmission enable
Enable
23
P34
SI2
CK2
SERIAL2 CK
0
MODE, BPF, etc. transmits«*' clock
24
P35
S02
DAT2
SERIAL2 DATA
o
MODE. BPF. etc. data transmission
2b
P36
STR8
ENA
SERIAL SELECT
0
MODE. BPF, etc. data enatxe select »on
Enatfe i
?6
P3?
CS
ENB
SERIAL SELECT
o
MODE, BPF. etc. data enable selection
Enable 2
27
Vss
GNO
28
V3
29
V2
30
V1
31
Vcc
5V
32
PA3
COM4
COM4
0
LCD COMMON
33
PA2
COM3
COM4
o
LCD COMMON
34
PA1
COM2
COM3
o
LCD COMMON
35
PAO
COM1
COM3
o
LCD COMMON
36
P50
SEG1
WKP0
DB0
1
SW. initial setting dttection
Detection
37
P51
SEG2
WKP1
OB1
1
SW. initial setting defection
Detection
38
P52
SEG3
WKP2
OB?
I
SW, initial setting detection
Detection
39
P53
SEG4
WKP3
DB3
1
SW, initial setting diitection
Detection
40
PS4
SEGS
WKP4
0B4
1
SW. initial setting diitection
Detection
41
P55
SEG6
WKP5
DBS
1
SW. initial setting detection
Detection
42
P56
SEG7
WKP6
DB6
1
SW , initial setting defection
Detecvon
43
P57
SEG6
WKP7
0
Detection
44
P60
SEG9
Y0
o
Panel SW (or ON detection
At detecting
45
P€1
SEG10
Y1
o
Pane1 SW for ON detection
At detecting
46
P€2
SEG1
Y2
o
Output tor initial condrtton settng
detection
47
P63
SEG12
Y3
o
Output tor initial condition setting
detection
48
P64
SEG13
GND
0
49
P65
SEG14
LCDEN
0
LCO driver enable
50
P66
SEG15
LCDCK
0
LCD driver doc*
51
P67
j SEG18
LCOATA
0
LCD dnver data
Summary of Contents for DX-70
Page 40: ...r j o 30 Transistor Diode and LED Outline Drawings To p View...
Page 41: ...C O M 2 C O M 1...
Page 42: ......
Page 44: ...4 PLL Unit and Fan 23...
Page 45: ...5 Top View 1 2 4...
Page 46: ...J...
Page 48: ...7 LPF Unit AJ0017 AJ0017 2 6 AJ0029...
Page 49: ...8 PA Unit and LPF Unit...
Page 93: ...7 Main Unit Side A 50...
Page 100: ...Ar x r i3 n 9s 74HC4040 s o 2 2 e yysw ry en...
Page 101: ...cn 0 3 BLOCK DIAGRAM P U J CC O U K T O y T j l iiii i ii i ii i i fi8 iH s fr 3 s...
Page 102: ...E x p l o d e d V i e w f o r E D X 1 1 Front V iew 2 R ear V iew 01 cn...
Page 103: ...ST0054...
Page 104: ...o C D BLACK PINK...
Page 105: ...AJ0017 AJ0017 AJ0017...
Page 106: ...C V 0 0 0 1 CD...
Page 107: ...UE0258...
Page 108: ...05 00...
Page 109: ......
Page 112: ...vj o C onnectionExam ple Supplied co ax cable A d ju stm en t Point...
Page 114: ...PC Bord View for EDX 1 S ide A S3 CN5 W2 p a t 5 B JP8 o O Svi SPPJ2 CN PV 71...
Page 116: ...S c h e m a t i c D i a g r a m f o r E D X 1 73...