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ELECTRICAL
CHARACTERISTICS
16
5.6 Latch-Up Test Results
Test Description:
Latch-Up testing was performed at room ambient using an
IMCS-4600 system which applies a stepped voltage to one pin per device with
all other pins open except Vdd and Vss which were biased to 5 Volts and
ground respectively.
Testing was started at 5.0 V (Positive) or 0 V(Negative), and the DUT was
biased for 0.5 seconds.
If neither the PUT current supply nor the device current supply reached the
predefined limit (DUT=0 mA , Icc=100 mA), then the voltage was increased
by 0.1 Volts and the pin was tested again.
This procedure was recommended by the JEDEC JC-40.2 CMOS Logic
standardization committee.
Notes:
1. DUT: Device Under Test.
2. PUT: Pin Under Test.
Vcc
DUT
GND
Pin
under
m
Untested
Output Open
Circuit
Untested
Input Tied
to V supply
Trigger
Source
V Supply
+
+
Icc Measurement
1 Source
Test Circuit : Positive Input/ output Overvoltage /Overcurrent
Summary of Contents for AU9381
Page 4: ...TABLE OF CONTENTS i...
Page 8: ...APPLICATION BLOCK DIAGRAM 4...
Page 12: ...SYSTEM ARCHITECTURE AND REFERENCE DESIGN 8...
Page 16: ...ELECTRICAL CHARACTERISTICS 12...
Page 22: ...PIN ASSIGNMENT 18...
Page 24: ...PIN ASSIGNMENT 20...