4. System Architecture and Reference
Design
4
4
.
.
1
1
A
A
U
U
6
6
3
3
7
7
1
1
B
B
l
l
o
o
c
c
k
k
D
D
i
i
a
a
g
g
r
r
a
a
m
m
Figure 4.1 AU6371 Block Diagram
3.3V
PLL
Card
Power
1.8V
Voltage
Regulator
/Power Switch
12MHz
XTAL
USB
SIE
RAM
CF/MD/SMC/
SD/MMC/MS/
xD Control FIFO
Processor
Arbitrator
ROM
XCVR
CF
MD
SMC
SD
MMC
MS
xD
USB
Upstream
Port
AU6371-JEL USB 2.0 Single LUN Multiple Flash Card Reader Controller V1.03W
6
