3
2.
Input Signals from Frame Cameras
Figure 3. Frame Camera Input Signals and Region of Interest
For digital frame cameras, the Data, Line Valid, Frame Valid, and CLK input signals come
directly from the digital input drivers. For analog frame cameras, the input data and
controls go through the Sync separators and A/D converters to be converted to the Data,
Line Valid, Frame Valid, and CLK signals.
3.
NTSC/PAL/S-Video Input Signals
Figure 4. NTSC/PAL/S-Video Input Signals
Composite or component video input to the Enhanced Video Input Processor (EVIP) is
converted to YUV data that can be processed directly by the TriMedia. The EVIP provides
Frame Valid and Odd/Even field signals.
F.
Image Capture, Distribution, Processing, and Output
Analog image data from the camera is captured, converted (as needed) into RGB or YUV
digital data by the front end and distributed to the TriMedia processors and to any enabled
outputs (SVGA/TV, PMC daughtercards, Host PMC bus).
Digital data inputs pass through two FPGAs, each with an external SDRAM. The FPGAs can
perform multiplexing and re-order incoming data for Odd/Even and Left/Right tapped
cameras. When using three or four tap cameras, half the bits from each tap are routed to
each FPGA, allowing the two parts to operate identically.
EVIP
Image
Capture
NTSC/PAL
or S-Video
YUV Data
Frame Valid
Odd/Even Field
Image
Capture
To Distribution
8
Data
Line Valid
CLK
Frame Valid
